diff options
Diffstat (limited to 'firmware/target/arm/pp/system-pp5002.c')
-rw-r--r-- | firmware/target/arm/pp/system-pp5002.c | 227 |
1 files changed, 227 insertions, 0 deletions
diff --git a/firmware/target/arm/pp/system-pp5002.c b/firmware/target/arm/pp/system-pp5002.c new file mode 100644 index 0000000000..3186d3739a --- /dev/null +++ b/firmware/target/arm/pp/system-pp5002.c | |||
@@ -0,0 +1,227 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2002 by Alan Korr | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #include "system.h" | ||
22 | |||
23 | #ifndef BOOTLOADER | ||
24 | #include "adc-target.h" | ||
25 | #include "button-target.h" | ||
26 | |||
27 | extern void TIMER1(void); | ||
28 | extern void TIMER2(void); | ||
29 | |||
30 | void __attribute__((interrupt("IRQ"))) irq_handler(void) | ||
31 | { | ||
32 | if(CURRENT_CORE == CPU) | ||
33 | { | ||
34 | if (CPU_INT_STAT & TIMER1_MASK) | ||
35 | TIMER1(); | ||
36 | else if (CPU_INT_STAT & TIMER2_MASK) | ||
37 | TIMER2(); | ||
38 | else if (CPU_INT_STAT & GPIO_MASK) | ||
39 | { | ||
40 | if (GPIOA_INT_STAT) | ||
41 | ipod_3g_button_int(); | ||
42 | #ifdef IPOD_1G2G | ||
43 | if (GPIOB_INT_STAT & 0x04) | ||
44 | ipod_2g_adc_int(); | ||
45 | #endif | ||
46 | } | ||
47 | } | ||
48 | else | ||
49 | { | ||
50 | if (COP_INT_STAT & TIMER2_MASK) | ||
51 | TIMER2(); | ||
52 | } | ||
53 | } | ||
54 | |||
55 | #endif | ||
56 | |||
57 | #ifndef BOOTLOADER | ||
58 | void ICODE_ATTR __attribute__((naked)) commit_dcache(void) | ||
59 | { | ||
60 | asm volatile( | ||
61 | "mov r0, #0xf0000000 \n" | ||
62 | "add r0, r0, #0xc000 \n" /* r0 = CACHE_FLUSH_BASE */ | ||
63 | "add r1, r0, #0x2000 \n" /* r1 = CACHE_FLUSH_BASE + CACHE_SIZE */ | ||
64 | "mov r2, #0 \n" | ||
65 | "1: \n" | ||
66 | "str r2, [r0], #16 \n" /* Commit */ | ||
67 | "cmp r0, r1 \n" | ||
68 | "blo 1b \n" | ||
69 | "bx lr \n" | ||
70 | ); | ||
71 | } | ||
72 | |||
73 | void ICODE_ATTR __attribute__((naked)) commit_discard_idcache(void) | ||
74 | { | ||
75 | asm volatile( | ||
76 | "mov r0, #0xf0000000 \n" | ||
77 | "add r2, r0, #0x4000 \n" /* r1 = CACHE_INVALIDATE_BASE */ | ||
78 | "add r0, r0, #0xc000 \n" /* r0 = CACHE_FLUSH_BASE */ | ||
79 | "add r1, r0, #0x2000 \n" /* r2 = CACHE_FLUSH_BASE + CACHE_SIZE */ | ||
80 | "mov r3, #0 \n" | ||
81 | "1: \n" | ||
82 | "str r3, [r0], #16 \n" /* Commit */ | ||
83 | "str r3, [r2], #16 \n" /* Discard */ | ||
84 | "cmp r0, r1 \n" | ||
85 | "blo 1b \n" | ||
86 | "bx lr \n" | ||
87 | ); | ||
88 | } | ||
89 | |||
90 | void commit_discard_dcache(void) __attribute__((alias("commit_discard_idcache"))); | ||
91 | |||
92 | static void ipod_init_cache(void) | ||
93 | { | ||
94 | /* Initialising the cache in the iPod bootloader prevents Rockbox from starting */ | ||
95 | PROC_STAT &= ~0x700; | ||
96 | outl(0x4000, 0xcf004020); | ||
97 | |||
98 | CACHE_CTL = CACHE_CTL_INIT; | ||
99 | |||
100 | asm volatile( | ||
101 | "mov r0, #0xf0000000 \n" | ||
102 | "add r0, r0, #0x4000 \n" /* r0 = CACHE_INVALIDATE_BASE */ | ||
103 | "add r1, r0, #0x2000 \n" /* r1 = CACHE_INVALIDATE_BASE + CACHE_SIZE */ | ||
104 | "mov r2, #0 \n" | ||
105 | "1: \n" | ||
106 | "str r2, [r0], #16 \n" /* Invalidate */ | ||
107 | "cmp r0, r1 \n" | ||
108 | "blo 1b \n" | ||
109 | : : : "r0", "r1", "r2" | ||
110 | ); | ||
111 | |||
112 | /* Cache if (addr & mask) >> 16 == (mask & match) >> 16: | ||
113 | * yes: 0x00000000 - 0x03ffffff | ||
114 | * no: 0x04000000 - 0x1fffffff | ||
115 | * yes: 0x20000000 - 0x23ffffff | ||
116 | * no: 0x24000000 - 0x3fffffff <= range containing uncached alias | ||
117 | */ | ||
118 | CACHE_MASK = 0x00001c00; | ||
119 | CACHE_OPERATION = 0x3fc0; | ||
120 | |||
121 | CACHE_CTL = CACHE_CTL_INIT | CACHE_CTL_RUN; | ||
122 | } | ||
123 | |||
124 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ | ||
125 | void set_cpu_frequency(long frequency) | ||
126 | #else | ||
127 | static void pp_set_cpu_frequency(long frequency) | ||
128 | #endif | ||
129 | { | ||
130 | cpu_frequency = frequency; | ||
131 | |||
132 | PLL_CONTROL |= 0x6000; /* make sure some enable bits are set */ | ||
133 | CLOCK_ENABLE = 0x01; /* select source #1 */ | ||
134 | |||
135 | switch (frequency) | ||
136 | { | ||
137 | case CPUFREQ_MAX: | ||
138 | PLL_UNLOCK = 0xd19b; /* unlock frequencies > 66MHz */ | ||
139 | CLOCK_SOURCE = 0xa9; /* source #1: 24 Mhz, source #2..#4: PLL */ | ||
140 | PLL_CONTROL = 0xe000; /* PLL enabled */ | ||
141 | PLL_DIV = 3; /* 10/3 * 24MHz */ | ||
142 | PLL_MULT = 10; | ||
143 | udelay(200); /* wait for relock */ | ||
144 | break; | ||
145 | |||
146 | case CPUFREQ_NORMAL: | ||
147 | CLOCK_SOURCE = 0xa9; /* source #1: 24 Mhz, source #2..#4: PLL */ | ||
148 | PLL_CONTROL = 0xe000; /* PLL enabled */ | ||
149 | PLL_DIV = 4; /* 5/4 * 24MHz */ | ||
150 | PLL_MULT = 5; | ||
151 | udelay(200); /* wait for relock */ | ||
152 | break; | ||
153 | |||
154 | case CPUFREQ_SLEEP: | ||
155 | CLOCK_SOURCE = 0x51; /* source #2: 32kHz, #1, #2, #4: 24MHz */ | ||
156 | PLL_CONTROL = 0x6000; /* PLL disabled */ | ||
157 | udelay(10000); /* let 32kHz source stabilize? */ | ||
158 | break; | ||
159 | |||
160 | default: | ||
161 | CLOCK_SOURCE = 0x55; /* source #1..#4: 24 Mhz */ | ||
162 | PLL_CONTROL = 0x6000; /* PLL disabled */ | ||
163 | cpu_frequency = CPUFREQ_DEFAULT; | ||
164 | break; | ||
165 | } | ||
166 | CLOCK_ENABLE = 0x02; /* select source #2 */ | ||
167 | } | ||
168 | #endif /* !BOOTLOADER */ | ||
169 | |||
170 | void system_init(void) | ||
171 | { | ||
172 | #ifndef BOOTLOADER | ||
173 | if (CURRENT_CORE == CPU) | ||
174 | { | ||
175 | /* Remap the flash ROM on CPU, keep hidden from COP: | ||
176 | * 0x00000000-0x03ffffff = 0x20000000-0x23ffffff */ | ||
177 | MMAP1_LOGICAL = 0x20003c00; | ||
178 | MMAP1_PHYSICAL = 0x00003f84; | ||
179 | |||
180 | #if defined(IPOD_1G2G) || defined(IPOD_3G) | ||
181 | DEV_EN = 0x0b9f; /* don't clock unused PP5002 hardware components */ | ||
182 | outl(0x0035, 0xcf005004); /* DEV_EN2 ? */ | ||
183 | #endif | ||
184 | |||
185 | INT_FORCED_CLR = -1; | ||
186 | CPU_INT_DIS = -1; | ||
187 | COP_INT_DIS = -1; | ||
188 | |||
189 | GPIOA_INT_EN = 0; | ||
190 | GPIOB_INT_EN = 0; | ||
191 | GPIOC_INT_EN = 0; | ||
192 | GPIOD_INT_EN = 0; | ||
193 | |||
194 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ | ||
195 | #if NUM_CORES > 1 | ||
196 | cpu_boost_init(); | ||
197 | #endif | ||
198 | #else | ||
199 | pp_set_cpu_frequency(CPUFREQ_MAX); | ||
200 | #endif | ||
201 | } | ||
202 | ipod_init_cache(); | ||
203 | #endif | ||
204 | } | ||
205 | |||
206 | void system_reboot(void) | ||
207 | { | ||
208 | DEV_RS |= 4; | ||
209 | while (1); | ||
210 | } | ||
211 | |||
212 | void system_exception_wait(void) | ||
213 | { | ||
214 | /* FIXME: we just need the right buttons */ | ||
215 | CPU_INT_DIS = -1; | ||
216 | COP_INT_DIS = -1; | ||
217 | |||
218 | /* Halt */ | ||
219 | sleep_core(CURRENT_CORE); | ||
220 | while (1); | ||
221 | } | ||
222 | |||
223 | int system_memory_guard(int newmode) | ||
224 | { | ||
225 | (void)newmode; | ||
226 | return 0; | ||
227 | } | ||