diff options
Diffstat (limited to 'firmware/target/arm/pp/crt0-pp-bl.S')
-rw-r--r-- | firmware/target/arm/pp/crt0-pp-bl.S | 217 |
1 files changed, 217 insertions, 0 deletions
diff --git a/firmware/target/arm/pp/crt0-pp-bl.S b/firmware/target/arm/pp/crt0-pp-bl.S new file mode 100644 index 0000000000..01681288f9 --- /dev/null +++ b/firmware/target/arm/pp/crt0-pp-bl.S | |||
@@ -0,0 +1,217 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2002 by Linus Nielsen Feltzing | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #include "config.h" | ||
22 | #include "cpu.h" | ||
23 | |||
24 | .section .init.text,"ax",%progbits | ||
25 | |||
26 | .global start | ||
27 | start: | ||
28 | |||
29 | /* PortalPlayer bootloader and startup code based on startup.s from the iPodLinux | ||
30 | * loader | ||
31 | * | ||
32 | * Copyright (c) 2003, Daniel Palffy (dpalffy (at) rainstorm.org) | ||
33 | * Copyright (c) 2005, Bernard Leach <leachbj@bouncycastle.org> | ||
34 | * | ||
35 | */ | ||
36 | #if CONFIG_CPU == PP5002 | ||
37 | .equ PROC_ID, 0xc4000000 | ||
38 | .equ CPU_CTRL, 0xcf004054 | ||
39 | .equ CPU_STATUS, 0xcf004050 | ||
40 | .equ COP_CTRL, 0xcf004058 | ||
41 | .equ COP_STATUS, 0xcf004050 | ||
42 | .equ IIS_CONFIG, 0xc0002500 | ||
43 | .equ SLEEP, 0xca | ||
44 | .equ WAKE, 0xce | ||
45 | .equ CPUSLEEPING, 0x8000 | ||
46 | .equ COPSLEEPING, 0x4000 | ||
47 | .equ CACHE_CTRL, 0xcf004024 | ||
48 | .equ CACHE_ENAB, 0x2 /* Actually the CACHE_CTL_INIT flag */ | ||
49 | #else | ||
50 | .equ PROC_ID, 0x60000000 | ||
51 | .equ CPU_CTRL, 0x60007000 | ||
52 | .equ CPU_STATUS, 0x60007000 | ||
53 | .equ COP_CTRL, 0x60007004 | ||
54 | .equ COP_STATUS, 0x60007004 | ||
55 | .equ IIS_CONFIG, 0x70002800 | ||
56 | .equ SLEEP, 0x80000000 | ||
57 | .equ WAKE, 0x0 | ||
58 | .equ CPUSLEEPING, 0x80000000 | ||
59 | .equ COPSLEEPING, 0x80000000 | ||
60 | .equ CACHE_CTRL, 0x6000c000 | ||
61 | .equ CACHE_ENAB, 0x1 | ||
62 | #endif | ||
63 | |||
64 | msr cpsr_c, #0xdf /* enter sys mode, disable IRQ */ | ||
65 | #ifndef E200R_INSTALLER | ||
66 | /* 1 - Copy the bootloader to IRAM */ | ||
67 | /* get the high part of our execute address */ | ||
68 | bic r0, pc, #0xff /* r4 = pc & 0xffffff00 */ | ||
69 | |||
70 | /* Copy bootloader to safe area - 0x40000000 (IRAM) */ | ||
71 | mov r1, #0x40000000 | ||
72 | ldr r2, =_dataend | ||
73 | 1: | ||
74 | cmp r2, r1 | ||
75 | ldrhi r3, [r0], #4 | ||
76 | strhi r3, [r1], #4 | ||
77 | bhi 1b | ||
78 | |||
79 | #ifndef IPOD_ARCH | ||
80 | /* For builds on targets with mi4 firmware, scramble writes data to | ||
81 | 0xe0-0xeb, so jump past that. pad_skip must then exist at an | ||
82 | address >= 0xec */ | ||
83 | b pad_skip | ||
84 | |||
85 | .space 60*4 | ||
86 | |||
87 | pad_skip: | ||
88 | #endif /* IPOD_ARCH */ | ||
89 | |||
90 | |||
91 | /* 2 - Jump both CPU and COP there */ | ||
92 | ldr pc, =start_loc /* jump to the relocated start_loc: */ | ||
93 | #endif /* E200R_INSTALLER */ | ||
94 | |||
95 | start_loc: | ||
96 | /* Find out which processor we are */ | ||
97 | ldr r0, =PROC_ID | ||
98 | ldrb r0, [r0] | ||
99 | cmp r0, #0x55 | ||
100 | beq cpu | ||
101 | |||
102 | cop: | ||
103 | /* put us (co-processor) to sleep */ | ||
104 | ldr r0, =COP_CTRL | ||
105 | mov r1, #SLEEP | ||
106 | str r1, [r0] | ||
107 | nop | ||
108 | nop | ||
109 | |||
110 | /* Invalidate cache */ | ||
111 | mov r0, #1 | ||
112 | bl cache_op | ||
113 | |||
114 | ldr r0, =startup_loc | ||
115 | ldr pc, [r0] | ||
116 | |||
117 | cpu: | ||
118 | /* Wait for COP to be sleeping */ | ||
119 | ldr r0, =COP_STATUS | ||
120 | 1: | ||
121 | ldr r1, [r0] | ||
122 | tst r1, #COPSLEEPING | ||
123 | beq 1b | ||
124 | |||
125 | /* Initialise bss section to zero */ | ||
126 | ldr r0, =_edata | ||
127 | ldr r1, =_end | ||
128 | mov r2, #0 | ||
129 | 1: | ||
130 | cmp r1, r0 | ||
131 | strhi r2, [r0], #4 | ||
132 | bhi 1b | ||
133 | |||
134 | /* Set up some stack and munge it with 0xdeadbeef */ | ||
135 | ldr sp, =stackend | ||
136 | ldr r0, =stackbegin | ||
137 | ldr r1, =0xdeadbeef | ||
138 | 1: | ||
139 | cmp sp, r0 | ||
140 | strhi r1, [r0], #4 | ||
141 | bhi 1b | ||
142 | |||
143 | /* execute the loader - this will load an image to 0x10000000 */ | ||
144 | bl main | ||
145 | |||
146 | /* store actual startup location returned by main() */ | ||
147 | ldr r1, =startup_loc | ||
148 | str r0, [r1] | ||
149 | |||
150 | /* flush cache */ | ||
151 | mov r0, #0 | ||
152 | bl cache_op | ||
153 | |||
154 | /* Wake up the coprocessor before executing the firmware */ | ||
155 | ldr r0, =COP_CTRL | ||
156 | mov r1, #WAKE | ||
157 | str r1, [r0] | ||
158 | |||
159 | #if defined(SANSA_C200) || defined(PHILIPS_HDD1630) | ||
160 | /* Magic for loading the c200 OF */ | ||
161 | ldr r0, =0xb00d10ad | ||
162 | mov r1, #0x700 | ||
163 | ldr r2, =0xfff0 | ||
164 | mov r3, #0x7 | ||
165 | #endif | ||
166 | |||
167 | #if defined(PHILIPS_HDD6330) | ||
168 | /* Magic for loading the HDD6XX0 OF */ | ||
169 | ldr r0, =0xb00d10ad | ||
170 | mov r1, #0x800 | ||
171 | ldr r2, =0xfff0 | ||
172 | mov r3, #0x7 | ||
173 | #endif | ||
174 | |||
175 | ldr r4, =startup_loc | ||
176 | ldr pc, [r4] | ||
177 | |||
178 | startup_loc: | ||
179 | .word 0x0 | ||
180 | |||
181 | #ifdef IPOD_ARCH | ||
182 | .align 8 /* starts at 0x100 */ | ||
183 | .global boot_table | ||
184 | boot_table: | ||
185 | /* here comes the boot table, don't move its offset - preceding | ||
186 | code+data must stay <= 256 bytes */ | ||
187 | .space 400 | ||
188 | #endif | ||
189 | |||
190 | cache_op: | ||
191 | ldr r2, =CACHE_CTRL | ||
192 | ldr r1, [r2] | ||
193 | tst r1, #CACHE_ENAB | ||
194 | bxeq lr | ||
195 | cmp r0, #0 | ||
196 | #ifdef CPU_PP502x | ||
197 | ldr r0, =0xf000f044 | ||
198 | ldr r1, [r0] | ||
199 | orrne r1, r1, #0x6 | ||
200 | orreq r1, r1, #0x2 | ||
201 | str r1, [r0] | ||
202 | 1: | ||
203 | ldr r1, [r2] | ||
204 | tst r1, #0x8000 | ||
205 | bne 1b | ||
206 | #elif CONFIG_CPU == PP5002 | ||
207 | ldrne r0, =0xf0004000 | ||
208 | ldreq r0, =0xf000c000 | ||
209 | add r1, r0, #0x2000 | ||
210 | mov r2, #0 | ||
211 | 1: | ||
212 | cmp r1, r0 | ||
213 | strhi r2, [r0], #16 | ||
214 | bhi 1b | ||
215 | #endif /* CPU type */ | ||
216 | bx lr | ||
217 | |||