diff options
Diffstat (limited to 'firmware/target/arm/pp/boot-pp502x-bl-usb.lds')
-rw-r--r-- | firmware/target/arm/pp/boot-pp502x-bl-usb.lds | 133 |
1 files changed, 133 insertions, 0 deletions
diff --git a/firmware/target/arm/pp/boot-pp502x-bl-usb.lds b/firmware/target/arm/pp/boot-pp502x-bl-usb.lds new file mode 100644 index 0000000000..e721991c5a --- /dev/null +++ b/firmware/target/arm/pp/boot-pp502x-bl-usb.lds | |||
@@ -0,0 +1,133 @@ | |||
1 | /* Will have been included from boot.lds */ | ||
2 | ENTRY(start) | ||
3 | OUTPUT_FORMAT(elf32-littlearm) | ||
4 | OUTPUT_ARCH(arm) | ||
5 | STARTUP(target/arm/crt0-pp502x-bl-usb.o) | ||
6 | |||
7 | #define DRAMORIG 0x01000000 /* Load at 16 MB */ | ||
8 | #define DRAMSIZE 0x00100000 /* 1MB for bootloader */ | ||
9 | #define MEMEND (MEMORYSIZE*0x100000) /* From virtual mapping at 0 */ | ||
10 | #define NOCACHE_BASE 0x10000000 | ||
11 | #ifndef IRAMORIG | ||
12 | #define IRAMORIG 0x40000000 | ||
13 | #endif | ||
14 | #define IRAMSIZE 0x20000 | ||
15 | #define FLASHORIG 0x001f0000 | ||
16 | #define FLASHSIZE 2M | ||
17 | |||
18 | #define CACHEALIGN_SIZE 16 | ||
19 | |||
20 | MEMORY | ||
21 | { | ||
22 | DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE | ||
23 | IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE | ||
24 | } | ||
25 | |||
26 | SECTIONS | ||
27 | { | ||
28 | . = DRAMORIG; | ||
29 | _loadaddress = . + NOCACHE_BASE; | ||
30 | |||
31 | .text : | ||
32 | { | ||
33 | *(.init.text) | ||
34 | *(.text*) | ||
35 | *(.glue_7) | ||
36 | *(.glue_7t) | ||
37 | . = ALIGN(0x4); | ||
38 | } > DRAM | ||
39 | |||
40 | .rodata : | ||
41 | { | ||
42 | *(.rodata*) | ||
43 | . = ALIGN(0x4); | ||
44 | } > DRAM | ||
45 | |||
46 | .data : | ||
47 | { | ||
48 | *(.data*) | ||
49 | . = ALIGN(0x4); | ||
50 | } > DRAM | ||
51 | |||
52 | /* .ncdata section is placed at uncached physical alias address and is | ||
53 | * loaded at the proper cached virtual address - no copying is | ||
54 | * performed in the init code */ | ||
55 | .ncdata . + NOCACHE_BASE : | ||
56 | { | ||
57 | . = ALIGN(CACHEALIGN_SIZE); | ||
58 | *(.ncdata*) | ||
59 | . = ALIGN(CACHEALIGN_SIZE); | ||
60 | } AT> DRAM | ||
61 | |||
62 | /DISCARD/ . - NOCACHE_BASE : | ||
63 | { | ||
64 | *(.eh_frame) | ||
65 | } > DRAM | ||
66 | |||
67 | _noloaddram = .; | ||
68 | |||
69 | .ibss IRAMORIG (NOLOAD) : | ||
70 | { | ||
71 | _iedata = .; | ||
72 | *(.qharray) | ||
73 | *(.ibss*) | ||
74 | . = ALIGN(0x4); | ||
75 | _iend = .; | ||
76 | } > IRAM | ||
77 | |||
78 | .iram _iend : | ||
79 | { | ||
80 | _iramstart = .; | ||
81 | *(.icode*) | ||
82 | *(.irodata*) | ||
83 | *(.idata*) | ||
84 | _iramend = .; | ||
85 | } > IRAM AT> DRAM | ||
86 | |||
87 | _iramcopy = LOADADDR(.iram); | ||
88 | |||
89 | .loadaddressend : | ||
90 | { | ||
91 | _loadaddressend = . + NOCACHE_BASE; | ||
92 | } AT> DRAM | ||
93 | |||
94 | .stack (NOLOAD) : | ||
95 | { | ||
96 | . = ALIGN(8); | ||
97 | *(.stack) | ||
98 | stackbegin = .; | ||
99 | . += 0x2000; | ||
100 | stackend = .; | ||
101 | } > IRAM | ||
102 | |||
103 | /* .bss and .ncbss are treated as a single section to use one init loop | ||
104 | * to zero them - note "_edata" and "_end" */ | ||
105 | .bss _noloaddram (NOLOAD) : | ||
106 | { | ||
107 | _edata = .; | ||
108 | *(.bss*) | ||
109 | *(COMMON) | ||
110 | } > DRAM | ||
111 | |||
112 | .ncbss . + NOCACHE_BASE (NOLOAD) : | ||
113 | { | ||
114 | . = ALIGN(CACHEALIGN_SIZE); | ||
115 | *(.ncbss*) | ||
116 | . = ALIGN(CACHEALIGN_SIZE); | ||
117 | } AT> DRAM | ||
118 | |||
119 | /* This will be aligned by preceding alignments */ | ||
120 | .endaddr . - NOCACHE_BASE (NOLOAD) : | ||
121 | { | ||
122 | _end = .; | ||
123 | } > DRAM | ||
124 | |||
125 | /* Reference to all DRAM after loaded bootloader image */ | ||
126 | .freebuffer _end (NOLOAD) : | ||
127 | { | ||
128 | . = ALIGN(4); | ||
129 | freebuffer = .; | ||
130 | . = MEMEND-1; | ||
131 | freebufferend = .; | ||
132 | } | ||
133 | } | ||