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1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2008 by Jens Arnold
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#include "config.h"
21#include "cpu.h"
22
23#if CONFIG_CPU == PP5002
24 .section .icode,"ax",%progbits
25#else
26 .text
27#endif
28 .align 2
29
30
31 .global lcd_write_data
32 .type lcd_write_data,%function
33
34lcd_write_data:
35 stmfd sp!, {r4, lr}
36 ldr r2, =LCD1_BASE
37
38.loop:
39 ldrb r3, [r0], #1
40
41#ifdef IPOD_MINI2G
42 ldrb r4, [r0], #1
43 orr r3, r4, r3, lsl #8
44 orr r3, r3, #0x760000
451:
46 ldr r4, [r2]
47 tst r4, #0x8000
48 bne 1b
49 str r3, [r2, #0x08]
50#else
511:
52 ldr r4, [r2]
53 tst r4, #0x8000
54 bne 1b
55 str r3, [r2, #0x10]
56
57 ldrb r3, [r0], #1
581:
59 ldr r4, [r2]
60 tst r4, #0x8000
61 bne 1b
62 str r3, [r2, #0x10]
63#endif
64
65 subs r1, r1, #1
66 bne .loop
67
68 ldmfd sp!, {r4, pc}
69
70.wd_end:
71 .size lcd_write_data,.wd_end-lcd_write_data
72
73
74#ifdef IPOD_MINI2G
75
76 .global lcd_write_data_shifted
77 .type lcd_write_data_shifted,%function
78
79lcd_write_data_shifted:
80 stmfd sp!, {r4-r6, lr}
81 ldr r2, =LCD1_BASE
82 mov r6, #0x760000
83 ldrb r3, [r0], #1
84
85.sloop:
86 ldrb r4, [r0], #1
87 orr r3, r4, r3, lsl #8
88 ldrb r4, [r0], #1
89 orr r3, r4, r3, lsl #8
90 mov r5, r3, lsl #12
91 orr r5, r6, r5, lsr #16
921:
93 ldr r4, [r2]
94 tst r4, #0x8000
95 bne 1b
96 str r5, [r2, #0x08]
97
98 subs r1, r1, #1
99 bne .sloop
100
101 ldmfd sp!, {r4-r6, pc}
102
103.wds_end:
104 .size lcd_write_data_shifted,.wds_end-lcd_write_data_shifted
105
106#elif defined IPOD_MINI
107
108 .global lcd_write_data_shifted
109 .type lcd_write_data_shifted,%function
110
111lcd_write_data_shifted:
112 stmfd sp!, {r4, r5, lr}
113 ldr r2, =LCD1_BASE
114 ldrb r3, [r0], #1
115
116.sloop:
117 ldrb r4, [r0], #1
118 orr r3, r4, r3, lsl #8
119 mov r5, r3, lsr #4
1201:
121 ldr r4, [r2]
122 tst r4, #0x8000
123 bne 1b
124 str r5, [r2, #0x10]
125
126 ldrb r4, [r0], #1
127 orr r3, r4, r3, lsl #8
128 mov r5, r3, lsr #4
1291:
130 ldr r4, [r2]
131 tst r4, #0x8000
132 bne 1b
133 str r5, [r2, #0x10]
134
135 subs r1, r1, #1
136 bne .sloop
137
138 ldmfd sp!, {r4, r5, pc}
139.wds_end:
140 .size lcd_write_data_shifted,.wds_end-lcd_write_data_shifted
141
142#endif
143
144 .global lcd_mono_data
145 .type lcd_mono_data,%function
146
147lcd_mono_data:
148 stmfd sp!, {r4-r6, lr}
149 ldr r2, =LCD1_BASE
150 adr r6, .dibits
151
152.mloop:
153 ldrb r3, [r0], #1
154 mov r4, r3, lsr #4
155 ldrb r5, [r6, r4]
156
157#ifdef IPOD_MINI2G
158 and r4, r3, #0x0f
159 ldrb r4, [r6, r4]
160 orr r5, r4, r5, lsl #8
161 orr r5, r5, #0x760000
1621:
163 ldr r4, [r2]
164 tst r4, #0x8000
165 bne 1b
166 str r5, [r2, #0x08]
167#else
1681:
169 ldr r4, [r2]
170 tst r4, #0x8000
171 bne 1b
172 str r5, [r2, #0x10]
173
174 and r4, r3, #0x0f
175 ldrb r5, [r6, r4]
1761:
177 ldr r4, [r2]
178 tst r4, #0x8000
179 bne 1b
180 str r5, [r2, #0x10]
181#endif
182
183 subs r1, r1, #1
184 bne .mloop
185
186 ldmfd sp!, {r4-r6, pc}
187
188.dibits:
189 .byte 0x00, 0x03, 0x0C, 0x0F, 0x30, 0x33, 0x3C, 0x3F
190 .byte 0xC0, 0xC3, 0xCC, 0xCF, 0xF0, 0xF3, 0xFC, 0xFF
191
192.md_end:
193 .size lcd_mono_data,.md_end-lcd_mono_data
194
195
196 .global lcd_grey_data
197 .type lcd_grey_data,%function
198
199/* A high performance function to write grey phase data to the display,
200 * one or multiple pixels.
201 *
202 * Arguments:
203 * r0 - pixel value data address
204 * r1 - pixel phase data address
205 * r2 - pixel block count
206 *
207 * Register usage:
208 * r3/r4 - current block of phases
209 * r5/r6 - current block of values
210 * r7 - lcd data accumulator
211 * r8 - phase signs mask
212 * r9 - lcd bridge address
213 */
214
215lcd_grey_data:
216 stmfd sp!, {r4-r9, lr}
217 mov r8, #0x80
218 orr r8, r8, r8, lsl #8
219 orr r8, r8, r8, lsl #16
220 ldr r9, =LCD1_BASE
221
222.greyloop:
223 ldmia r1, {r3-r4} /* Fetch 8 pixel phases */
224 ldmia r0!, {r5-r6} /* Fetch 8 pixel values */
225
226#ifdef IPOD_MINI2G /* Serial bridge mode */
227 mov r7, #0x760000
228 tst r3, #0x80
229 orreq r7, r7, #0xc000
230 tst r3, #0x8000
231 orreq r7, r7, #0x3000
232 tst r3, #0x800000
233 orreq r7, r7, #0x0c00
234 tst r3, #0x80000000
235 orreq r7, r7, #0x0300
236 bic r3, r3, r8
237 add r3, r3, r5
238#else /* Parallel bridge mode */
239 mov r7, #0
240 tst r3, #0x80
241 orreq r7, r7, #0xc0
242 tst r3, #0x8000
243 orreq r7, r7, #0x30
244 tst r3, #0x800000
245 orreq r7, r7, #0x0c
246 tst r3, #0x80000000
247 orreq r7, r7, #0x03
248 bic r3, r3, r8
249 add r3, r3, r5
250
2511:
252 ldr r5, [r9]
253 tst r5, #0x8000
254 bne 1b
255
256 str r7, [r9, #0x10]
257 mov r7, #0
258#endif
259
260 tst r4, #0x80
261 orreq r7, r7, #0xc0
262 tst r4, #0x8000
263 orreq r7, r7, #0x30
264 tst r4, #0x800000
265 orreq r7, r7, #0x0c
266 tst r4, #0x80000000
267 orreq r7, r7, #0x03
268 bic r4, r4, r8
269 add r4, r4, r6
270
271 stmia r1!, {r3-r4}
272
2731:
274 ldr r5, [r9]
275 tst r5, #0x8000
276 bne 1b
277#ifdef IPOD_MINI2G
278 str r7, [r9, #0x08]
279#else
280 str r7, [r9, #0x10]
281#endif
282
283 subs r2, r2, #1
284 bne .greyloop
285
286 ldmfd sp!, {r4-r9, pc}
287
288.gd_end:
289 .size lcd_grey_data,.gd_end-lcd_grey_data
290