diff options
Diffstat (limited to 'firmware/target/arm/imx31')
-rw-r--r-- | firmware/target/arm/imx31/avic-imx31.c | 65 | ||||
-rw-r--r-- | firmware/target/arm/imx31/avic-imx31.h | 151 | ||||
-rw-r--r-- | firmware/target/arm/imx31/i2c-imx31.c | 86 | ||||
-rw-r--r-- | firmware/target/arm/imx31/i2c-imx31.h | 14 | ||||
-rw-r--r-- | firmware/target/arm/imx31/spi-imx31.c | 88 | ||||
-rw-r--r-- | firmware/target/arm/imx31/spi-imx31.h | 13 |
6 files changed, 130 insertions, 287 deletions
diff --git a/firmware/target/arm/imx31/avic-imx31.c b/firmware/target/arm/imx31/avic-imx31.c index e349c97d82..5bf7275e07 100644 --- a/firmware/target/arm/imx31/avic-imx31.c +++ b/firmware/target/arm/imx31/avic-imx31.c | |||
@@ -25,7 +25,23 @@ | |||
25 | #include "panic.h" | 25 | #include "panic.h" |
26 | #include "debug.h" | 26 | #include "debug.h" |
27 | 27 | ||
28 | static const char * avic_int_names[64] = | 28 | #define avic ((unsigned long * const)AVIC_BASE_ADDR) |
29 | #define INTCNTL (0x000 / sizeof (unsigned long)) /* 000h */ | ||
30 | #define NIMASK (0x004 / sizeof (unsigned long)) /* 004h */ | ||
31 | #define INTENNUM (0x008 / sizeof (unsigned long)) /* 008h */ | ||
32 | #define INTDISNUM (0x00c / sizeof (unsigned long)) /* 00Ch */ | ||
33 | #define INTENABLE (0x010 / sizeof (unsigned long)) /* 010h H,L */ | ||
34 | #define INTTYPE (0x018 / sizeof (unsigned long)) /* 018h H,L */ | ||
35 | #define NIPRIORITY (0x020 / sizeof (unsigned long)) /* 020h 7-0 */ | ||
36 | #define NIVECSR (0x040 / sizeof (unsigned long)) /* 040h */ | ||
37 | #define FIVECSR (0x044 / sizeof (unsigned long)) /* 044h */ | ||
38 | #define INTSRC (0x048 / sizeof (unsigned long)) /* 048h H,L */ | ||
39 | #define INTFRC (0x050 / sizeof (unsigned long)) /* 050h H,L */ | ||
40 | #define NIPND (0x058 / sizeof (unsigned long)) /* 058h H,L */ | ||
41 | #define FIPND (0x060 / sizeof (unsigned long)) /* 060h H,L */ | ||
42 | #define VECTOR (0x100 / sizeof (unsigned long)) /* 100h */ | ||
43 | |||
44 | static const char * const avic_int_names[64] = | ||
29 | { | 45 | { |
30 | "RESERVED0", "RESERVED1", "RESERVED2", "I2C3", | 46 | "RESERVED0", "RESERVED1", "RESERVED2", "I2C3", |
31 | "I2C2", "MPEG4_ENCODER", "RTIC", "FIR", | 47 | "I2C2", "MPEG4_ENCODER", "RTIC", "FIR", |
@@ -47,7 +63,7 @@ static const char * avic_int_names[64] = | |||
47 | 63 | ||
48 | void UIE_VECTOR(void) | 64 | void UIE_VECTOR(void) |
49 | { | 65 | { |
50 | int mode; | 66 | unsigned long mode; |
51 | int offset; | 67 | int offset; |
52 | 68 | ||
53 | asm volatile ( | 69 | asm volatile ( |
@@ -58,8 +74,7 @@ void UIE_VECTOR(void) | |||
58 | : "=&r"(mode) | 74 | : "=&r"(mode) |
59 | ); | 75 | ); |
60 | 76 | ||
61 | offset = mode == 0x11 ? | 77 | offset = mode == 0x11 ? (long)avic[FIVECSR] : ((long)avic[NIVECSR] >> 16); |
62 | (int32_t)AVIC_FIVECSR : ((int32_t)AVIC_NIVECSR >> 16); | ||
63 | 78 | ||
64 | panicf("Unhandled %s %d: %s", | 79 | panicf("Unhandled %s %d: %s", |
65 | mode == 0x11 ? "FIQ" : "IRQ", offset, | 80 | mode == 0x11 ? "FIQ" : "IRQ", offset, |
@@ -70,7 +85,7 @@ void UIE_VECTOR(void) | |||
70 | /* We use the AVIC */ | 85 | /* We use the AVIC */ |
71 | void __attribute__((interrupt("IRQ"))) irq_handler(void) | 86 | void __attribute__((interrupt("IRQ"))) irq_handler(void) |
72 | { | 87 | { |
73 | const int offset = (int32_t)AVIC_NIVECSR >> 16; | 88 | int offset = (long)avic[NIVECSR] >> 16; |
74 | 89 | ||
75 | if (offset == -1) | 90 | if (offset == -1) |
76 | { | 91 | { |
@@ -103,26 +118,25 @@ void __attribute__((naked)) fiq_handler(void) | |||
103 | 118 | ||
104 | void avic_init(void) | 119 | void avic_init(void) |
105 | { | 120 | { |
106 | struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR; | ||
107 | int i; | 121 | int i; |
108 | 122 | ||
109 | /* Disable all interrupts and set to unhandled */ | 123 | /* Disable all interrupts and set to unhandled */ |
110 | avic_disable_int(INT_ALL); | 124 | avic_disable_int(INT_ALL); |
111 | 125 | ||
112 | /* Reset AVIC control */ | 126 | /* Reset AVIC control */ |
113 | avic->intcntl = 0; | 127 | avic[INTCNTL] = 0; |
114 | 128 | ||
115 | /* Init all interrupts to type IRQ */ | 129 | /* Init all interrupts to type IRQ */ |
116 | avic_set_int_type(INT_ALL, INT_TYPE_IRQ); | 130 | avic_set_int_type(INT_ALL, INT_TYPE_IRQ); |
117 | 131 | ||
118 | /* Set all normal to lowest priority */ | 132 | /* Set all normal to lowest priority */ |
119 | for (i = 0; i < 8; i++) | 133 | for (i = 0; i < 8; i++) |
120 | avic->nipriority[i] = 0; | 134 | avic[NIPRIORITY + i] = 0; |
121 | 135 | ||
122 | /* Set NM bit to enable VIC. Mask fast interrupts. Core arbiter rise | 136 | /* Set NM bit to enable VIC. Mask fast interrupts. Core arbiter rise |
123 | * for normal interrupts (for lowest latency). */ | 137 | * for normal interrupts (for lowest latency). */ |
124 | avic->intcntl |= AVIC_INTCNTL_NM | AVIC_INTCNTL_FIDIS | | 138 | avic[INTCNTL] |= AVIC_INTCNTL_NM | AVIC_INTCNTL_FIDIS | |
125 | AVIC_INTCNTL_NIAD; | 139 | AVIC_INTCNTL_NIAD; |
126 | 140 | ||
127 | /* Enable VE bit in CP15 Control reg to enable VIC */ | 141 | /* Enable VE bit in CP15 Control reg to enable VIC */ |
128 | asm volatile ( | 142 | asm volatile ( |
@@ -132,30 +146,28 @@ void avic_init(void) | |||
132 | : : : "r0"); | 146 | : : : "r0"); |
133 | 147 | ||
134 | /* Enable normal interrupts at all priorities */ | 148 | /* Enable normal interrupts at all priorities */ |
135 | avic->nimask = AVIC_NIL_ENABLE; | 149 | avic[NIMASK] = AVIC_NIL_ENABLE; |
136 | } | 150 | } |
137 | 151 | ||
138 | void avic_set_int_priority(enum IMX31_INT_LIST ints, | 152 | void avic_set_int_priority(enum IMX31_INT_LIST ints, |
139 | unsigned long ni_priority) | 153 | unsigned long ni_priority) |
140 | { | 154 | { |
141 | struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR; | 155 | volatile unsigned long * const reg = &avic[NIPRIORITY + 7 - (ints >> 3)]; |
142 | volatile uint32_t *reg = &avic->nipriority[7 - (ints >> 3)]; | ||
143 | unsigned int shift = (ints & 0x7) << 2; | 156 | unsigned int shift = (ints & 0x7) << 2; |
144 | uint32_t mask = 0xful << shift; | 157 | unsigned long mask = 0xful << shift; |
145 | *reg = (*reg & ~mask) | ((ni_priority << shift) & mask); | 158 | *reg = (*reg & ~mask) | ((ni_priority << shift) & mask); |
146 | } | 159 | } |
147 | 160 | ||
148 | void avic_enable_int(enum IMX31_INT_LIST ints, enum INT_TYPE intstype, | 161 | void avic_enable_int(enum IMX31_INT_LIST ints, enum INT_TYPE intstype, |
149 | unsigned long ni_priority, void (*handler)(void)) | 162 | unsigned long ni_priority, void (*handler)(void)) |
150 | { | 163 | { |
151 | struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR; | ||
152 | int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS); | 164 | int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS); |
153 | 165 | ||
154 | if (ints != INT_ALL) /* No mass-enable allowed */ | 166 | if (ints != INT_ALL) /* No mass-enable allowed */ |
155 | { | 167 | { |
156 | avic_set_int_type(ints, intstype); | 168 | avic_set_int_type(ints, intstype); |
157 | avic->vector[ints] = (long)handler; | 169 | avic[VECTOR + ints] = (unsigned long)handler; |
158 | avic->intennum = ints; | 170 | avic[INTENNUM] = ints; |
159 | avic_set_int_priority(ints, ni_priority); | 171 | avic_set_int_priority(ints, ni_priority); |
160 | } | 172 | } |
161 | 173 | ||
@@ -164,30 +176,27 @@ void avic_enable_int(enum IMX31_INT_LIST ints, enum INT_TYPE intstype, | |||
164 | 176 | ||
165 | void avic_disable_int(enum IMX31_INT_LIST ints) | 177 | void avic_disable_int(enum IMX31_INT_LIST ints) |
166 | { | 178 | { |
167 | struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR; | ||
168 | uint32_t i; | ||
169 | |||
170 | if (ints == INT_ALL) | 179 | if (ints == INT_ALL) |
171 | { | 180 | { |
181 | int i; | ||
172 | for (i = 0; i < 64; i++) | 182 | for (i = 0; i < 64; i++) |
173 | { | 183 | { |
174 | avic->intdisnum = i; | 184 | avic[INTDISNUM] = i; |
175 | avic->vector[i] = (long)UIE_VECTOR; | 185 | avic[VECTOR + i] = (unsigned long)UIE_VECTOR; |
176 | } | 186 | } |
177 | } | 187 | } |
178 | else | 188 | else |
179 | { | 189 | { |
180 | avic->intdisnum = ints; | 190 | avic[INTDISNUM] = ints; |
181 | avic->vector[ints] = (long)UIE_VECTOR; | 191 | avic[VECTOR + ints] = (unsigned long)UIE_VECTOR; |
182 | } | 192 | } |
183 | } | 193 | } |
184 | 194 | ||
185 | static void set_int_type(int i, enum INT_TYPE intstype) | 195 | static void set_int_type(int i, enum INT_TYPE intstype) |
186 | { | 196 | { |
187 | /* INTTYPEH: vectors 63-32, INTTYPEL: vectors 31-0 */ | 197 | /* INTTYPEH: vectors 63-32, INTTYPEL: vectors 31-0 */ |
188 | struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR; | 198 | volatile unsigned long * const reg = &avic[INTTYPE + 1 - (i >> 5)]; |
189 | volatile uint32_t *reg = &avic->inttype[1 - (i >> 5)]; | 199 | unsigned long val = 1L << (i & 0x1f); |
190 | uint32_t val = 1L << (i & 0x1f); | ||
191 | 200 | ||
192 | if (intstype == INT_TYPE_IRQ) | 201 | if (intstype == INT_TYPE_IRQ) |
193 | val = *reg & ~val; | 202 | val = *reg & ~val; |
@@ -222,5 +231,5 @@ void avic_set_ni_level(int level) | |||
222 | else if (level > 15) | 231 | else if (level > 15) |
223 | level = 15; | 232 | level = 15; |
224 | 233 | ||
225 | AVIC_NIMASK = level; | 234 | avic[NIMASK] = level; |
226 | } | 235 | } |
diff --git a/firmware/target/arm/imx31/avic-imx31.h b/firmware/target/arm/imx31/avic-imx31.h index ba9e50652d..04a2856b50 100644 --- a/firmware/target/arm/imx31/avic-imx31.h +++ b/firmware/target/arm/imx31/avic-imx31.h | |||
@@ -21,157 +21,6 @@ | |||
21 | #ifndef AVIC_IMX31_H | 21 | #ifndef AVIC_IMX31_H |
22 | #define AVIC_IMX31_H | 22 | #define AVIC_IMX31_H |
23 | 23 | ||
24 | struct avic_map | ||
25 | { | ||
26 | volatile uint32_t intcntl; /* 00h */ | ||
27 | volatile uint32_t nimask; /* 04h */ | ||
28 | volatile uint32_t intennum; /* 08h */ | ||
29 | volatile uint32_t intdisnum; /* 0Ch */ | ||
30 | union /* 10h */ | ||
31 | { | ||
32 | struct | ||
33 | { | ||
34 | volatile uint32_t intenableh; /* 10h */ | ||
35 | volatile uint32_t intenablel; /* 14h */ | ||
36 | }; | ||
37 | volatile uint32_t intenable[2]; /* H,L */ | ||
38 | }; | ||
39 | union | ||
40 | { | ||
41 | struct | ||
42 | { | ||
43 | volatile uint32_t inttypeh; /* 18h */ | ||
44 | volatile uint32_t inttypel; /* 1Ch */ | ||
45 | }; | ||
46 | volatile uint32_t inttype[2]; /* H,L */ | ||
47 | }; | ||
48 | union | ||
49 | { | ||
50 | struct | ||
51 | { | ||
52 | volatile uint32_t nipriority7; /* 20h */ | ||
53 | volatile uint32_t nipriority6; /* 24h */ | ||
54 | volatile uint32_t nipriority5; /* 28h */ | ||
55 | volatile uint32_t nipriority4; /* 2Ch */ | ||
56 | volatile uint32_t nipriority3; /* 30h */ | ||
57 | volatile uint32_t nipriority2; /* 34h */ | ||
58 | volatile uint32_t nipriority1; /* 38h */ | ||
59 | volatile uint32_t nipriority0; /* 3Ch */ | ||
60 | }; | ||
61 | volatile uint32_t nipriority[8]; /* 7-0 */ | ||
62 | }; | ||
63 | volatile uint32_t nivecsr; /* 40h */ | ||
64 | volatile uint32_t fivecsr; /* 44h */ | ||
65 | union | ||
66 | { | ||
67 | struct | ||
68 | { | ||
69 | volatile uint32_t intsrch; /* 48h */ | ||
70 | volatile uint32_t intsrcl; /* 4Ch */ | ||
71 | }; | ||
72 | volatile uint32_t intsrc[2]; /* H,L */ | ||
73 | }; | ||
74 | union | ||
75 | { | ||
76 | struct | ||
77 | { | ||
78 | volatile uint32_t intfrch; /* 50h */ | ||
79 | volatile uint32_t intfrcl; /* 54h */ | ||
80 | }; | ||
81 | volatile uint32_t intfrc[2]; /* H,L */ | ||
82 | }; | ||
83 | union | ||
84 | { | ||
85 | struct | ||
86 | { | ||
87 | volatile uint32_t nipndh; /* 58h */ | ||
88 | volatile uint32_t nipndl; /* 5Ch */ | ||
89 | }; | ||
90 | volatile uint32_t nipnd[2]; /* H,L */ | ||
91 | }; | ||
92 | union | ||
93 | { | ||
94 | struct | ||
95 | { | ||
96 | volatile uint32_t fipndh; /* 60h */ | ||
97 | volatile uint32_t fipndl; /* 64h */ | ||
98 | }; | ||
99 | volatile uint32_t fipnd[2]; /* H,L */ | ||
100 | }; | ||
101 | volatile uint32_t skip1[0x26]; /* 68h */ | ||
102 | union /* 100h */ | ||
103 | { | ||
104 | struct | ||
105 | { | ||
106 | volatile uint32_t reserved0; | ||
107 | volatile uint32_t reserved1; | ||
108 | volatile uint32_t reserved2; | ||
109 | volatile uint32_t i2c3; | ||
110 | volatile uint32_t i2c2; | ||
111 | volatile uint32_t mpeg4encoder; | ||
112 | volatile uint32_t rtic; | ||
113 | volatile uint32_t fir; | ||
114 | volatile uint32_t mmc_sdhc2; | ||
115 | volatile uint32_t mmc_sdhc1; | ||
116 | volatile uint32_t i2c1; | ||
117 | volatile uint32_t ssi2; | ||
118 | volatile uint32_t ssi1; | ||
119 | volatile uint32_t cspi2; | ||
120 | volatile uint32_t cspi1; | ||
121 | volatile uint32_t ata; | ||
122 | volatile uint32_t mbx; | ||
123 | volatile uint32_t cspi3; | ||
124 | volatile uint32_t uart3; | ||
125 | volatile uint32_t iim; | ||
126 | volatile uint32_t sim1; | ||
127 | volatile uint32_t sim2; | ||
128 | volatile uint32_t rnga; | ||
129 | volatile uint32_t evtmon; | ||
130 | volatile uint32_t kpp; | ||
131 | volatile uint32_t rtc; | ||
132 | volatile uint32_t pwn; | ||
133 | volatile uint32_t epit2; | ||
134 | volatile uint32_t epit1; | ||
135 | volatile uint32_t gpt; | ||
136 | volatile uint32_t pwr_fail; | ||
137 | volatile uint32_t ccm_dvfs; | ||
138 | volatile uint32_t uart2; | ||
139 | volatile uint32_t nandfc; | ||
140 | volatile uint32_t sdma; | ||
141 | volatile uint32_t usb_host1; | ||
142 | volatile uint32_t usb_host2; | ||
143 | volatile uint32_t usb_otg; | ||
144 | volatile uint32_t reserved3; | ||
145 | volatile uint32_t mshc1; | ||
146 | volatile uint32_t mshc2; | ||
147 | volatile uint32_t ipu_err; | ||
148 | volatile uint32_t ipu; | ||
149 | volatile uint32_t reserved4; | ||
150 | volatile uint32_t reserved5; | ||
151 | volatile uint32_t uart1; | ||
152 | volatile uint32_t uart4; | ||
153 | volatile uint32_t uart5; | ||
154 | volatile uint32_t etc_irq; | ||
155 | volatile uint32_t scc_scm; | ||
156 | volatile uint32_t scc_smn; | ||
157 | volatile uint32_t gpio2; | ||
158 | volatile uint32_t gpio1; | ||
159 | volatile uint32_t ccm_clk; | ||
160 | volatile uint32_t pcmcia; | ||
161 | volatile uint32_t wdog; | ||
162 | volatile uint32_t gpio3; | ||
163 | volatile uint32_t reserved6; | ||
164 | volatile uint32_t ext_pwmg; | ||
165 | volatile uint32_t ext_temp; | ||
166 | volatile uint32_t ext_sense1; | ||
167 | volatile uint32_t ext_sense2; | ||
168 | volatile uint32_t ext_wdog; | ||
169 | volatile uint32_t ext_tv; | ||
170 | }; | ||
171 | volatile uint32_t vector[0x40]; /* 100h */ | ||
172 | }; | ||
173 | }; | ||
174 | |||
175 | /* #define IRQ priorities for different modules (0-15) */ | 24 | /* #define IRQ priorities for different modules (0-15) */ |
176 | #define INT_PRIO_DEFAULT 7 | 25 | #define INT_PRIO_DEFAULT 7 |
177 | #define INT_PRIO_DVFS (INT_PRIO_DEFAULT+1) | 26 | #define INT_PRIO_DVFS (INT_PRIO_DEFAULT+1) |
diff --git a/firmware/target/arm/imx31/i2c-imx31.c b/firmware/target/arm/imx31/i2c-imx31.c index 1ffdce38ea..4e810c588f 100644 --- a/firmware/target/arm/imx31/i2c-imx31.c +++ b/firmware/target/arm/imx31/i2c-imx31.c | |||
@@ -37,25 +37,31 @@ static __attribute__((interrupt("IRQ"))) void I2C2_HANDLER(void); | |||
37 | static __attribute__((interrupt("IRQ"))) void I2C3_HANDLER(void); | 37 | static __attribute__((interrupt("IRQ"))) void I2C3_HANDLER(void); |
38 | #endif | 38 | #endif |
39 | 39 | ||
40 | #define IADR (0x00 / sizeof (unsigned short)) /* 00h */ | ||
41 | #define IFDR (0x04 / sizeof (unsigned short)) /* 04h */ | ||
42 | #define I2CR (0x08 / sizeof (unsigned short)) /* 08h */ | ||
43 | #define I2SR (0x0c / sizeof (unsigned short)) /* 0ch */ | ||
44 | #define I2DR (0x10 / sizeof (unsigned short)) /* 10h */ | ||
45 | |||
40 | static struct i2c_module_descriptor | 46 | static struct i2c_module_descriptor |
41 | { | 47 | { |
42 | struct i2c_map *base; /* Module base address */ | 48 | volatile unsigned short * const base; /* Module base address */ |
43 | enum IMX31_CG_LIST cg; /* Clock gating index */ | 49 | void (* const handler)(void); /* Module interrupt handler */ |
44 | enum IMX31_INT_LIST ints; /* Module interrupt number */ | 50 | struct mutex m; /* Node mutual-exclusion */ |
45 | int enable; /* Enable count */ | 51 | struct wakeup w; /* I2C done signal */ |
46 | void (*handler)(void); /* Module interrupt handler */ | 52 | unsigned char *addr_data; /* Additional addressing data */ |
47 | struct mutex m; /* Node mutual-exclusion */ | 53 | int addr_count; /* Addressing byte count */ |
48 | struct wakeup w; /* I2C done signal */ | 54 | unsigned char *data; /* TX/RX buffer (actual data) */ |
49 | unsigned char *addr_data; /* Additional addressing data */ | 55 | int data_count; /* TX/RX byte count */ |
50 | int addr_count; /* Addressing byte count */ | 56 | unsigned char addr; /* Address + r/w bit */ |
51 | unsigned char *data; /* TX/RX buffer (actual data) */ | 57 | uint8_t enable; /* Enable count */ |
52 | int data_count; /* TX/RX byte count */ | 58 | const uint8_t cg; /* Clock gating index */ |
53 | unsigned char addr; /* Address + r/w bit */ | 59 | const uint8_t ints; /* Module interrupt number */ |
54 | } i2c_descs[I2C_NUM_I2C] = | 60 | } i2c_descs[I2C_NUM_I2C] = |
55 | { | 61 | { |
56 | #if (I2C_MODULE_MASK & USE_I2C1_MODULE) | 62 | #if (I2C_MODULE_MASK & USE_I2C1_MODULE) |
57 | { | 63 | { |
58 | .base = (struct i2c_map *)I2C1_BASE_ADDR, | 64 | .base = (unsigned short *)I2C1_BASE_ADDR, |
59 | .cg = CG_I2C1, | 65 | .cg = CG_I2C1, |
60 | .ints = INT_I2C1, | 66 | .ints = INT_I2C1, |
61 | .handler = I2C1_HANDLER, | 67 | .handler = I2C1_HANDLER, |
@@ -63,7 +69,7 @@ static struct i2c_module_descriptor | |||
63 | #endif | 69 | #endif |
64 | #if (I2C_MODULE_MASK & USE_I2C2_MODULE) | 70 | #if (I2C_MODULE_MASK & USE_I2C2_MODULE) |
65 | { | 71 | { |
66 | .base = (struct i2c_map *)I2C2_BASE_ADDR, | 72 | .base = (unsigned short *)I2C2_BASE_ADDR, |
67 | .cg = CG_I2C2, | 73 | .cg = CG_I2C2, |
68 | .ints = INT_I2C2, | 74 | .ints = INT_I2C2, |
69 | .handler = I2C2_HANDLER, | 75 | .handler = I2C2_HANDLER, |
@@ -71,7 +77,7 @@ static struct i2c_module_descriptor | |||
71 | #endif | 77 | #endif |
72 | #if (I2C_MODULE_MASK & USE_I2C3_MODULE) | 78 | #if (I2C_MODULE_MASK & USE_I2C3_MODULE) |
73 | { | 79 | { |
74 | .base = (struct i2c_map *)I2C3_BASE_ADDR, | 80 | .base = (unsigned short *)I2C3_BASE_ADDR, |
75 | .cg = CG_I2C3, | 81 | .cg = CG_I2C3, |
76 | .ints = INT_I2C3, | 82 | .ints = INT_I2C3, |
77 | .handler = I2C3_HANDLER, | 83 | .handler = I2C3_HANDLER, |
@@ -81,11 +87,11 @@ static struct i2c_module_descriptor | |||
81 | 87 | ||
82 | static void i2c_interrupt(enum i2c_module_number i2c) | 88 | static void i2c_interrupt(enum i2c_module_number i2c) |
83 | { | 89 | { |
84 | struct i2c_module_descriptor *const desc = &i2c_descs[i2c]; | 90 | struct i2c_module_descriptor * const desc = &i2c_descs[i2c]; |
85 | struct i2c_map * const base = desc->base; | 91 | volatile unsigned short * const base = desc->base; |
86 | uint16_t i2sr = base->i2sr; | 92 | unsigned short i2sr = base[I2SR]; |
87 | 93 | ||
88 | base->i2sr = 0; /* Clear IIF */ | 94 | base[I2SR] = 0; /* Clear IIF */ |
89 | 95 | ||
90 | if (desc->addr_count >= 0) | 96 | if (desc->addr_count >= 0) |
91 | { | 97 | { |
@@ -100,8 +106,8 @@ static void i2c_interrupt(enum i2c_module_number i2c) | |||
100 | /* Switching to data cycle */ | 106 | /* Switching to data cycle */ |
101 | if (desc->addr & 0x1) | 107 | if (desc->addr & 0x1) |
102 | { | 108 | { |
103 | base->i2cr &= ~I2C_I2CR_MTX; /* Switch to RX mode */ | 109 | base[I2CR] &= ~I2C_I2CR_MTX; /* Switch to RX mode */ |
104 | base->i2dr; /* Dummy read */ | 110 | base[I2DR]; /* Dummy read */ |
105 | return; | 111 | return; |
106 | } | 112 | } |
107 | /* else remaining data is TX - handle below */ | 113 | /* else remaining data is TX - handle below */ |
@@ -109,12 +115,12 @@ static void i2c_interrupt(enum i2c_module_number i2c) | |||
109 | } | 115 | } |
110 | else | 116 | else |
111 | { | 117 | { |
112 | base->i2dr = *desc->addr_data++; /* Send next addressing byte */ | 118 | base[I2DR] = *desc->addr_data++; /* Send next addressing byte */ |
113 | return; | 119 | return; |
114 | } | 120 | } |
115 | } | 121 | } |
116 | 122 | ||
117 | if (base->i2cr & I2C_I2CR_MTX) | 123 | if (base[I2CR] & I2C_I2CR_MTX) |
118 | { | 124 | { |
119 | /* Transmitting data */ | 125 | /* Transmitting data */ |
120 | if ((i2sr & I2C_I2SR_RXAK) == 0) | 126 | if ((i2sr & I2C_I2SR_RXAK) == 0) |
@@ -123,7 +129,7 @@ i2c_transmit: | |||
123 | if (desc->data_count > 0) | 129 | if (desc->data_count > 0) |
124 | { | 130 | { |
125 | /* More bytes to send, got ACK from previous byte */ | 131 | /* More bytes to send, got ACK from previous byte */ |
126 | base->i2dr = *desc->data++; | 132 | base[I2DR] = *desc->data++; |
127 | desc->data_count--; | 133 | desc->data_count--; |
128 | return; | 134 | return; |
129 | } | 135 | } |
@@ -138,24 +144,24 @@ i2c_transmit: | |||
138 | if (desc->data_count == 1) | 144 | if (desc->data_count == 1) |
139 | { | 145 | { |
140 | /* 2nd to Last byte - NACK */ | 146 | /* 2nd to Last byte - NACK */ |
141 | base->i2cr |= I2C_I2CR_TXAK; | 147 | base[I2CR] |= I2C_I2CR_TXAK; |
142 | } | 148 | } |
143 | 149 | ||
144 | *desc->data++ = base->i2dr; /* Read data from I2DR and store */ | 150 | *desc->data++ = base[I2DR]; /* Read data from I2DR and store */ |
145 | return; | 151 | return; |
146 | } | 152 | } |
147 | else | 153 | else |
148 | { | 154 | { |
149 | /* Generate STOP signal before reading data */ | 155 | /* Generate STOP signal before reading data */ |
150 | base->i2cr &= ~(I2C_I2CR_MSTA | I2C_I2CR_IIEN); | 156 | base[I2CR] &= ~(I2C_I2CR_MSTA | I2C_I2CR_IIEN); |
151 | *desc->data++ = base->i2dr; /* Read data from I2DR and store */ | 157 | *desc->data++ = base[I2DR]; /* Read data from I2DR and store */ |
152 | goto i2c_done; | 158 | goto i2c_done; |
153 | } | 159 | } |
154 | } | 160 | } |
155 | 161 | ||
156 | i2c_stop: | 162 | i2c_stop: |
157 | /* Generate STOP signal */ | 163 | /* Generate STOP signal */ |
158 | base->i2cr &= ~(I2C_I2CR_MSTA | I2C_I2CR_IIEN); | 164 | base[I2CR] &= ~(I2C_I2CR_MSTA | I2C_I2CR_IIEN); |
159 | i2c_done: | 165 | i2c_done: |
160 | /* Signal thread we're done */ | 166 | /* Signal thread we're done */ |
161 | wakeup_signal(&desc->w); | 167 | wakeup_signal(&desc->w); |
@@ -183,18 +189,18 @@ static __attribute__((interrupt("IRQ"))) void I2C3_HANDLER(void) | |||
183 | static int i2c_transfer(struct i2c_node * const node, | 189 | static int i2c_transfer(struct i2c_node * const node, |
184 | struct i2c_module_descriptor *const desc) | 190 | struct i2c_module_descriptor *const desc) |
185 | { | 191 | { |
186 | struct i2c_map * const base = desc->base; | 192 | volatile unsigned short * const base = desc->base; |
187 | int count = desc->data_count; | 193 | int count = desc->data_count; |
188 | uint16_t i2cr; | 194 | uint16_t i2cr; |
189 | 195 | ||
190 | /* Make sure bus is idle. */ | 196 | /* Make sure bus is idle. */ |
191 | while (base->i2sr & I2C_I2SR_IBB); | 197 | while (base[I2SR] & I2C_I2SR_IBB); |
192 | 198 | ||
193 | /* Set speed */ | 199 | /* Set speed */ |
194 | base->ifdr = node->ifdr; | 200 | base[IFDR] = node->ifdr; |
195 | 201 | ||
196 | /* Enable module */ | 202 | /* Enable module */ |
197 | base->i2cr = I2C_I2CR_IEN; | 203 | base[I2CR] = I2C_I2CR_IEN; |
198 | 204 | ||
199 | /* Enable Interrupt, Master */ | 205 | /* Enable Interrupt, Master */ |
200 | i2cr = I2C_I2CR_IEN | I2C_I2CR_IIEN | I2C_I2CR_MTX; | 206 | i2cr = I2C_I2CR_IEN | I2C_I2CR_IIEN | I2C_I2CR_MTX; |
@@ -206,13 +212,13 @@ static int i2c_transfer(struct i2c_node * const node, | |||
206 | } | 212 | } |
207 | 213 | ||
208 | /* Set config */ | 214 | /* Set config */ |
209 | base->i2cr = i2cr; | 215 | base[I2CR] = i2cr; |
210 | 216 | ||
211 | /* Generate START */ | 217 | /* Generate START */ |
212 | base->i2cr = i2cr | I2C_I2CR_MSTA; | 218 | base[I2CR] = i2cr | I2C_I2CR_MSTA; |
213 | 219 | ||
214 | /* Address slave (first byte sent) and begin session. */ | 220 | /* Address slave (first byte sent) and begin session. */ |
215 | base->i2dr = desc->addr; | 221 | base[I2DR] = desc->addr; |
216 | 222 | ||
217 | /* Wait for transfer to complete */ | 223 | /* Wait for transfer to complete */ |
218 | if (wakeup_wait(&desc->w, HZ) == OBJ_WAIT_SUCCEEDED) | 224 | if (wakeup_wait(&desc->w, HZ) == OBJ_WAIT_SUCCEEDED) |
@@ -222,7 +228,7 @@ static int i2c_transfer(struct i2c_node * const node, | |||
222 | else | 228 | else |
223 | { | 229 | { |
224 | /* Generate STOP if timeout */ | 230 | /* Generate STOP if timeout */ |
225 | base->i2cr &= ~(I2C_I2CR_MSTA | I2C_I2CR_IIEN); | 231 | base[I2CR] &= ~(I2C_I2CR_MSTA | I2C_I2CR_IIEN); |
226 | count = -1; | 232 | count = -1; |
227 | } | 233 | } |
228 | 234 | ||
@@ -289,7 +295,7 @@ void i2c_init(void) | |||
289 | ccm_module_clock_gating(desc->cg, CGM_ON_RUN_WAIT); | 295 | ccm_module_clock_gating(desc->cg, CGM_ON_RUN_WAIT); |
290 | mutex_init(&desc->m); | 296 | mutex_init(&desc->m); |
291 | wakeup_init(&desc->w); | 297 | wakeup_init(&desc->w); |
292 | desc->base->i2cr = 0; | 298 | desc->base[I2CR] = 0; |
293 | ccm_module_clock_gating(desc->cg, CGM_OFF); | 299 | ccm_module_clock_gating(desc->cg, CGM_OFF); |
294 | } | 300 | } |
295 | } | 301 | } |
@@ -315,8 +321,8 @@ void i2c_enable_node(struct i2c_node *node, bool enable) | |||
315 | if (desc->enable > 0 && --desc->enable == 0) | 321 | if (desc->enable > 0 && --desc->enable == 0) |
316 | { | 322 | { |
317 | /* Last enable */ | 323 | /* Last enable */ |
318 | while (desc->base->i2sr & I2C_I2SR_IBB); /* Wait for STOP */ | 324 | while (desc->base[I2SR] & I2C_I2SR_IBB); /* Wait for STOP */ |
319 | desc->base->i2cr &= ~I2C_I2CR_IEN; | 325 | desc->base[I2CR] &= ~I2C_I2CR_IEN; |
320 | avic_disable_int(desc->ints); | 326 | avic_disable_int(desc->ints); |
321 | ccm_module_clock_gating(desc->cg, CGM_OFF); | 327 | ccm_module_clock_gating(desc->cg, CGM_OFF); |
322 | } | 328 | } |
diff --git a/firmware/target/arm/imx31/i2c-imx31.h b/firmware/target/arm/imx31/i2c-imx31.h index b36acecfcb..a29c7ce96b 100644 --- a/firmware/target/arm/imx31/i2c-imx31.h +++ b/firmware/target/arm/imx31/i2c-imx31.h | |||
@@ -43,20 +43,6 @@ enum i2c_module_number | |||
43 | I2C_NUM_I2C, | 43 | I2C_NUM_I2C, |
44 | }; | 44 | }; |
45 | 45 | ||
46 | /* Module interface map structure */ | ||
47 | struct i2c_map | ||
48 | { | ||
49 | volatile uint16_t iadr; /* 0x00 */ | ||
50 | volatile uint16_t unused1; | ||
51 | volatile uint16_t ifdr; /* 0x04 */ | ||
52 | volatile uint16_t unused2; | ||
53 | volatile uint16_t i2cr; /* 0x08 */ | ||
54 | volatile uint16_t unused3; | ||
55 | volatile uint16_t i2sr; /* 0x0C */ | ||
56 | volatile uint16_t unused4; | ||
57 | volatile uint16_t i2dr; /* 0x10 */ | ||
58 | }; | ||
59 | |||
60 | struct i2c_node | 46 | struct i2c_node |
61 | { | 47 | { |
62 | enum i2c_module_number num; /* Module that this node uses */ | 48 | enum i2c_module_number num; /* Module that this node uses */ |
diff --git a/firmware/target/arm/imx31/spi-imx31.c b/firmware/target/arm/imx31/spi-imx31.c index 3f66257c95..e6dddd65c1 100644 --- a/firmware/target/arm/imx31/spi-imx31.c +++ b/firmware/target/arm/imx31/spi-imx31.c | |||
@@ -37,25 +37,34 @@ static __attribute__((interrupt("IRQ"))) void CSPI2_HANDLER(void); | |||
37 | static __attribute__((interrupt("IRQ"))) void CSPI3_HANDLER(void); | 37 | static __attribute__((interrupt("IRQ"))) void CSPI3_HANDLER(void); |
38 | #endif | 38 | #endif |
39 | 39 | ||
40 | #define RXDATA (0x000 / sizeof (unsigned long)) /* 000h */ | ||
41 | #define TXDATA (0x004 / sizeof (unsigned long)) /* 004h */ | ||
42 | #define CONREG (0x008 / sizeof (unsigned long)) /* 008h */ | ||
43 | #define INTREG (0x00c / sizeof (unsigned long)) /* 00Ch */ | ||
44 | #define DMAREG (0x010 / sizeof (unsigned long)) /* 010h */ | ||
45 | #define STATREG (0x014 / sizeof (unsigned long)) /* 014h */ | ||
46 | #define PERIODREG (0x01c / sizeof (unsigned long)) /* 018h */ | ||
47 | #define TESTREG (0x1c0 / sizeof (unsigned long)) /* 1C0h */ | ||
48 | |||
40 | /* State data associatated with each CSPI module */ | 49 | /* State data associatated with each CSPI module */ |
41 | static struct spi_module_desc | 50 | static struct spi_module_desc |
42 | { | 51 | { |
43 | struct cspi_map * const base; /* CSPI module address */ | 52 | volatile unsigned long * const base; /* CSPI module address */ |
44 | struct spi_transfer_desc *head; /* Running job */ | 53 | struct spi_transfer_desc *head; /* Running job */ |
45 | struct spi_transfer_desc *tail; /* Most recent job added */ | 54 | struct spi_transfer_desc *tail; /* Most recent job added */ |
46 | const struct spi_node *last_node; /* Last node used for module */ | 55 | const struct spi_node *last_node; /* Last node used for module */ |
47 | void (*handler)(void); /* Interrupt handler */ | 56 | void (* const handler)(void); /* Interrupt handler */ |
48 | int rxcount; /* Independent copy of txcount */ | 57 | int rxcount; /* Independent copy of txcount */ |
49 | int8_t enab; /* Enable count */ | 58 | int8_t enab; /* Enable count */ |
50 | int8_t byte_size; /* Size of transfers in bytes */ | 59 | int8_t byte_size; /* Size of transfers in bytes */ |
51 | int8_t cg; /* Clock-gating value */ | 60 | const int8_t cg; /* Clock-gating value */ |
52 | int8_t ints; /* AVIC vector number */ | 61 | const int8_t ints; /* AVIC vector number */ |
53 | } spi_descs[SPI_NUM_CSPI] = | 62 | } spi_descs[SPI_NUM_CSPI] = |
54 | /* Init non-zero members */ | 63 | /* Init non-zero members */ |
55 | { | 64 | { |
56 | #if (SPI_MODULE_MASK & USE_CSPI1_MODULE) | 65 | #if (SPI_MODULE_MASK & USE_CSPI1_MODULE) |
57 | { | 66 | { |
58 | .base = (struct cspi_map *)CSPI1_BASE_ADDR, | 67 | .base = (unsigned long *)CSPI1_BASE_ADDR, |
59 | .cg = CG_CSPI1, | 68 | .cg = CG_CSPI1, |
60 | .ints = INT_CSPI1, | 69 | .ints = INT_CSPI1, |
61 | .handler = CSPI1_HANDLER, | 70 | .handler = CSPI1_HANDLER, |
@@ -63,7 +72,7 @@ static struct spi_module_desc | |||
63 | #endif | 72 | #endif |
64 | #if (SPI_MODULE_MASK & USE_CSPI2_MODULE) | 73 | #if (SPI_MODULE_MASK & USE_CSPI2_MODULE) |
65 | { | 74 | { |
66 | .base = (struct cspi_map *)CSPI2_BASE_ADDR, | 75 | .base = (unsigned long *)CSPI2_BASE_ADDR, |
67 | .cg = CG_CSPI2, | 76 | .cg = CG_CSPI2, |
68 | .ints = INT_CSPI2, | 77 | .ints = INT_CSPI2, |
69 | .handler = CSPI2_HANDLER, | 78 | .handler = CSPI2_HANDLER, |
@@ -71,7 +80,7 @@ static struct spi_module_desc | |||
71 | #endif | 80 | #endif |
72 | #if (SPI_MODULE_MASK & USE_CSPI3_MODULE) | 81 | #if (SPI_MODULE_MASK & USE_CSPI3_MODULE) |
73 | { | 82 | { |
74 | .base = (struct cspi_map *)CSPI3_BASE_ADDR, | 83 | .base = (unsigned long *)CSPI3_BASE_ADDR, |
75 | .cg = CG_CSPI3, | 84 | .cg = CG_CSPI3, |
76 | .ints = INT_CSPI3, | 85 | .ints = INT_CSPI3, |
77 | .handler = CSPI3_HANDLER, | 86 | .handler = CSPI3_HANDLER, |
@@ -83,8 +92,7 @@ static struct spi_module_desc | |||
83 | static void spi_reset(struct spi_module_desc * const desc) | 92 | static void spi_reset(struct spi_module_desc * const desc) |
84 | { | 93 | { |
85 | /* Reset by leaving it disabled */ | 94 | /* Reset by leaving it disabled */ |
86 | struct cspi_map * const base = desc->base; | 95 | desc->base[CONREG] &= ~CSPI_CONREG_EN; |
87 | base->conreg &= ~CSPI_CONREG_EN; | ||
88 | } | 96 | } |
89 | 97 | ||
90 | /* Write the context for the node and remember it to avoid unneeded reconfigure */ | 98 | /* Write the context for the node and remember it to avoid unneeded reconfigure */ |
@@ -92,7 +100,7 @@ static bool spi_set_context(struct spi_module_desc *desc, | |||
92 | struct spi_transfer_desc *xfer) | 100 | struct spi_transfer_desc *xfer) |
93 | { | 101 | { |
94 | const struct spi_node * const node = xfer->node; | 102 | const struct spi_node * const node = xfer->node; |
95 | struct cspi_map * const base = desc->base; | 103 | volatile unsigned long * const base = desc->base; |
96 | 104 | ||
97 | if (desc->enab == 0) | 105 | if (desc->enab == 0) |
98 | return false; | 106 | return false; |
@@ -101,17 +109,17 @@ static bool spi_set_context(struct spi_module_desc *desc, | |||
101 | return true; | 109 | return true; |
102 | 110 | ||
103 | /* Errata says CSPI should be disabled when writing PERIODREG. */ | 111 | /* Errata says CSPI should be disabled when writing PERIODREG. */ |
104 | base->conreg &= ~CSPI_CONREG_EN; | 112 | base[CONREG] &= ~CSPI_CONREG_EN; |
105 | 113 | ||
106 | /* Switch the module's node */ | 114 | /* Switch the module's node */ |
107 | desc->last_node = node; | 115 | desc->last_node = node; |
108 | desc->byte_size = (((node->conreg >> 8) & 0x1f) + 1 + 7) / 8 - 1; | 116 | desc->byte_size = (((node->conreg >> 8) & 0x1f) + 1 + 7) / 8 - 1; |
109 | 117 | ||
110 | /* Set the wait-states */ | 118 | /* Set the wait-states */ |
111 | base->periodreg = node->periodreg & 0xffff; | 119 | base[PERIODREG] = node->periodreg & 0xffff; |
112 | 120 | ||
113 | /* Keep reserved and start bits cleared. Keep enabled bit. */ | 121 | /* Keep reserved and start bits cleared. Keep enabled bit. */ |
114 | base->conreg = | 122 | base[CONREG] = |
115 | (node->conreg & ~(0xfcc8e000 | CSPI_CONREG_XCH | CSPI_CONREG_SMC)); | 123 | (node->conreg & ~(0xfcc8e000 | CSPI_CONREG_XCH | CSPI_CONREG_SMC)); |
116 | return true; | 124 | return true; |
117 | } | 125 | } |
@@ -119,13 +127,13 @@ static bool spi_set_context(struct spi_module_desc *desc, | |||
119 | 127 | ||
120 | /* Fill the TX fifo. Returns the number of remaining words. */ | 128 | /* Fill the TX fifo. Returns the number of remaining words. */ |
121 | static int tx_fill_fifo(struct spi_module_desc * const desc, | 129 | static int tx_fill_fifo(struct spi_module_desc * const desc, |
122 | struct cspi_map * const base, | 130 | volatile unsigned long * const base, |
123 | struct spi_transfer_desc * const xfer) | 131 | struct spi_transfer_desc * const xfer) |
124 | { | 132 | { |
125 | int count = xfer->count; | 133 | int count = xfer->count; |
126 | int size = desc->byte_size; | 134 | int size = desc->byte_size; |
127 | 135 | ||
128 | while ((base->statreg & CSPI_STATREG_TF) == 0) | 136 | while ((base[STATREG] & CSPI_STATREG_TF) == 0) |
129 | { | 137 | { |
130 | uint32_t word = 0; | 138 | uint32_t word = 0; |
131 | 139 | ||
@@ -143,7 +151,7 @@ static int tx_fill_fifo(struct spi_module_desc * const desc, | |||
143 | 151 | ||
144 | xfer->txbuf += size + 1; /* Increment buffer */ | 152 | xfer->txbuf += size + 1; /* Increment buffer */ |
145 | 153 | ||
146 | base->txdata = word; /* Write to FIFO */ | 154 | base[TXDATA] = word; /* Write to FIFO */ |
147 | 155 | ||
148 | if (--count == 0) | 156 | if (--count == 0) |
149 | break; | 157 | break; |
@@ -158,13 +166,13 @@ static int tx_fill_fifo(struct spi_module_desc * const desc, | |||
158 | static bool start_transfer(struct spi_module_desc * const desc, | 166 | static bool start_transfer(struct spi_module_desc * const desc, |
159 | struct spi_transfer_desc * const xfer) | 167 | struct spi_transfer_desc * const xfer) |
160 | { | 168 | { |
161 | struct cspi_map * const base = desc->base; | 169 | volatile unsigned long * const base = desc->base; |
162 | unsigned long intreg; | 170 | unsigned long intreg; |
163 | 171 | ||
164 | if (!spi_set_context(desc, xfer)) | 172 | if (!spi_set_context(desc, xfer)) |
165 | return false; | 173 | return false; |
166 | 174 | ||
167 | base->conreg |= CSPI_CONREG_EN; /* Enable module */ | 175 | base[CONREG] |= CSPI_CONREG_EN; /* Enable module */ |
168 | 176 | ||
169 | desc->rxcount = xfer->count; | 177 | desc->rxcount = xfer->count; |
170 | 178 | ||
@@ -178,9 +186,9 @@ static bool start_transfer(struct spi_module_desc * const desc, | |||
178 | 186 | ||
179 | tx_fill_fifo(desc, base, xfer); | 187 | tx_fill_fifo(desc, base, xfer); |
180 | 188 | ||
181 | base->statreg = CSPI_STATREG_TC; /* Ack 'complete' */ | 189 | base[STATREG] = CSPI_STATREG_TC; /* Ack 'complete' */ |
182 | base->intreg = intreg; /* Enable interrupts */ | 190 | base[INTREG] = intreg; /* Enable interrupts */ |
183 | base->conreg |= CSPI_CONREG_XCH; /* Begin transfer */ | 191 | base[CONREG] |= CSPI_CONREG_XCH; /* Begin transfer */ |
184 | 192 | ||
185 | return true; | 193 | return true; |
186 | } | 194 | } |
@@ -189,15 +197,15 @@ static bool start_transfer(struct spi_module_desc * const desc, | |||
189 | static void spi_interrupt(enum spi_module_number spi) | 197 | static void spi_interrupt(enum spi_module_number spi) |
190 | { | 198 | { |
191 | struct spi_module_desc *desc = &spi_descs[spi]; | 199 | struct spi_module_desc *desc = &spi_descs[spi]; |
192 | struct cspi_map * const base = desc->base; | 200 | volatile unsigned long * const base = desc->base; |
193 | unsigned long intreg = base->intreg; | 201 | unsigned long intreg = base[INTREG]; |
194 | struct spi_transfer_desc *xfer = desc->head; | 202 | struct spi_transfer_desc *xfer = desc->head; |
195 | int inc = desc->byte_size + 1; | 203 | int inc = desc->byte_size + 1; |
196 | 204 | ||
197 | /* Data received - empty out RXFIFO */ | 205 | /* Data received - empty out RXFIFO */ |
198 | while ((base->statreg & CSPI_STATREG_RR) != 0) | 206 | while ((base[STATREG] & CSPI_STATREG_RR) != 0) |
199 | { | 207 | { |
200 | uint32_t word = base->rxdata; | 208 | uint32_t word = base[RXDATA]; |
201 | 209 | ||
202 | if (desc->rxcount <= 0) | 210 | if (desc->rxcount <= 0) |
203 | continue; | 211 | continue; |
@@ -226,14 +234,14 @@ static void spi_interrupt(enum spi_module_number spi) | |||
226 | { | 234 | { |
227 | /* No more to receive - stop RX interrupts */ | 235 | /* No more to receive - stop RX interrupts */ |
228 | intreg &= ~(CSPI_INTREG_RHEN | CSPI_INTREG_RREN); | 236 | intreg &= ~(CSPI_INTREG_RHEN | CSPI_INTREG_RREN); |
229 | base->intreg = intreg; | 237 | base[INTREG] = intreg; |
230 | } | 238 | } |
231 | else if (intreg & CSPI_INTREG_RHEN) | 239 | else if (intreg & CSPI_INTREG_RHEN) |
232 | { | 240 | { |
233 | /* < 4 words expected - switch to RX ready */ | 241 | /* < 4 words expected - switch to RX ready */ |
234 | intreg &= ~CSPI_INTREG_RHEN; | 242 | intreg &= ~CSPI_INTREG_RHEN; |
235 | intreg |= CSPI_INTREG_RREN; | 243 | intreg |= CSPI_INTREG_RREN; |
236 | base->intreg = intreg; | 244 | base[INTREG] = intreg; |
237 | } | 245 | } |
238 | } | 246 | } |
239 | } | 247 | } |
@@ -247,15 +255,15 @@ static void spi_interrupt(enum spi_module_number spi) | |||
247 | /* Out of data - stop TX interrupts, enable TC interrupt. */ | 255 | /* Out of data - stop TX interrupts, enable TC interrupt. */ |
248 | intreg &= ~CSPI_INTREG_THEN; | 256 | intreg &= ~CSPI_INTREG_THEN; |
249 | intreg |= CSPI_INTREG_TCEN; | 257 | intreg |= CSPI_INTREG_TCEN; |
250 | base->intreg = intreg; | 258 | base[INTREG] = intreg; |
251 | } | 259 | } |
252 | 260 | ||
253 | if ((intreg & CSPI_INTREG_TCEN) && (base->statreg & CSPI_STATREG_TC)) | 261 | if ((intreg & CSPI_INTREG_TCEN) && (base[STATREG] & CSPI_STATREG_TC)) |
254 | { | 262 | { |
255 | /* Outbound transfer is complete. */ | 263 | /* Outbound transfer is complete. */ |
256 | intreg &= ~CSPI_INTREG_TCEN; | 264 | intreg &= ~CSPI_INTREG_TCEN; |
257 | base->intreg = intreg; | 265 | base[INTREG] = intreg; |
258 | base->statreg = CSPI_STATREG_TC; /* Ack 'complete' */ | 266 | base[STATREG] = CSPI_STATREG_TC; /* Ack 'complete' */ |
259 | } | 267 | } |
260 | 268 | ||
261 | if (intreg != 0) | 269 | if (intreg != 0) |
@@ -268,7 +276,7 @@ static void spi_interrupt(enum spi_module_number spi) | |||
268 | spi_transfer_cb_fn_type callback = xfer->callback; | 276 | spi_transfer_cb_fn_type callback = xfer->callback; |
269 | xfer->next = NULL; | 277 | xfer->next = NULL; |
270 | 278 | ||
271 | base->conreg &= ~CSPI_CONREG_EN; /* Disable module */ | 279 | base[CONREG] &= ~CSPI_CONREG_EN; /* Disable module */ |
272 | 280 | ||
273 | if (next == xfer) | 281 | if (next == xfer) |
274 | { | 282 | { |
@@ -361,8 +369,6 @@ void spi_disable_module(const struct spi_node *node) | |||
361 | if (desc->enab > 0 && --desc->enab == 0) | 369 | if (desc->enab > 0 && --desc->enab == 0) |
362 | { | 370 | { |
363 | /* Last enable for this module */ | 371 | /* Last enable for this module */ |
364 | struct cspi_map * const base = desc->base; | ||
365 | |||
366 | /* Wait for outstanding transactions */ | 372 | /* Wait for outstanding transactions */ |
367 | while (*(void ** volatile)&desc->head != NULL); | 373 | while (*(void ** volatile)&desc->head != NULL); |
368 | 374 | ||
@@ -370,7 +376,7 @@ void spi_disable_module(const struct spi_node *node) | |||
370 | avic_disable_int(desc->ints); | 376 | avic_disable_int(desc->ints); |
371 | 377 | ||
372 | /* Disable interface */ | 378 | /* Disable interface */ |
373 | base->conreg &= ~CSPI_CONREG_EN; | 379 | desc->base[CONREG] &= ~CSPI_CONREG_EN; |
374 | 380 | ||
375 | /* Disable interface clock */ | 381 | /* Disable interface clock */ |
376 | ccm_module_clock_gating(desc->cg, CGM_OFF); | 382 | ccm_module_clock_gating(desc->cg, CGM_OFF); |
diff --git a/firmware/target/arm/imx31/spi-imx31.h b/firmware/target/arm/imx31/spi-imx31.h index b5e31d46f2..71f9512103 100644 --- a/firmware/target/arm/imx31/spi-imx31.h +++ b/firmware/target/arm/imx31/spi-imx31.h | |||
@@ -41,19 +41,6 @@ enum spi_module_number | |||
41 | SPI_NUM_CSPI, | 41 | SPI_NUM_CSPI, |
42 | }; | 42 | }; |
43 | 43 | ||
44 | struct cspi_map | ||
45 | { | ||
46 | volatile uint32_t rxdata; /* 00h */ | ||
47 | volatile uint32_t txdata; /* 04h */ | ||
48 | volatile uint32_t conreg; /* 08h */ | ||
49 | volatile uint32_t intreg; /* 0Ch */ | ||
50 | volatile uint32_t dmareg; /* 10h */ | ||
51 | volatile uint32_t statreg; /* 14h */ | ||
52 | volatile uint32_t periodreg; /* 18h */ | ||
53 | volatile uint32_t skip1[0x69]; /* 1Ch */ | ||
54 | volatile uint32_t testreg; /* 1C0h */ | ||
55 | }; | ||
56 | |||
57 | struct spi_node | 44 | struct spi_node |
58 | { | 45 | { |
59 | enum spi_module_number num; /* Module number (CSPIx_NUM) */ | 46 | enum spi_module_number num; /* Module number (CSPIx_NUM) */ |