summaryrefslogtreecommitdiff
path: root/firmware/target/arm/imx31/gpio-imx31.h
diff options
context:
space:
mode:
Diffstat (limited to 'firmware/target/arm/imx31/gpio-imx31.h')
-rw-r--r--firmware/target/arm/imx31/gpio-imx31.h209
1 files changed, 170 insertions, 39 deletions
diff --git a/firmware/target/arm/imx31/gpio-imx31.h b/firmware/target/arm/imx31/gpio-imx31.h
index a1358672e8..86ca964f94 100644
--- a/firmware/target/arm/imx31/gpio-imx31.h
+++ b/firmware/target/arm/imx31/gpio-imx31.h
@@ -26,62 +26,193 @@
26#define USE_GPIO2_EVENTS (1 << 1) 26#define USE_GPIO2_EVENTS (1 << 1)
27#define USE_GPIO3_EVENTS (1 << 2) 27#define USE_GPIO3_EVENTS (1 << 2)
28 28
29/* Module indexes defined by which GPIO modules are used */ 29/* Module logical indexes */
30enum gpio_module_number 30enum gpio_module_number
31{ 31{
32 __GPIO_NUM_START = -1, 32 GPIO1_NUM, /* ID 0..31 */
33#if (GPIO_EVENT_MASK & USE_GPIO1_EVENTS) 33 GPIO2_NUM, /* ID 32..63 */
34 GPIO1_NUM, 34 GPIO3_NUM, /* ID 64..95 */
35#endif
36#if (GPIO_EVENT_MASK & USE_GPIO2_EVENTS)
37 GPIO2_NUM,
38#endif
39#if (GPIO_EVENT_MASK & USE_GPIO3_EVENTS)
40 GPIO3_NUM,
41#endif
42 GPIO_NUM_GPIO, 35 GPIO_NUM_GPIO,
43}; 36};
44 37
45/* Possible values for gpio interrupt line config */ 38enum gpio_id
46enum gpio_int_sense_enum
47{ 39{
48 GPIO_SENSE_LOW_LEVEL = 0, /* High-level sensitive */ 40 /* GPIO1 */
49 GPIO_SENSE_HIGH_LEVEL, /* Low-level sensitive */ 41 GPIO1_0_ID = 0,
50 GPIO_SENSE_RISING, /* Rising-edge sensitive */ 42 GPIO1_1_ID,
51 GPIO_SENSE_FALLING, /* Falling-edge sensitive */ 43 GPIO1_2_ID,
44 GPIO1_3_ID,
45 GPIO1_4_ID,
46 GPIO1_5_ID,
47 GPIO1_6_ID,
48 GPIO1_7_ID,
49 GPIO1_8_ID,
50 GPIO1_9_ID,
51 GPIO1_10_ID,
52 GPIO1_11_ID,
53 GPIO1_12_ID,
54 GPIO1_13_ID,
55 GPIO1_14_ID,
56 GPIO1_15_ID,
57 GPIO1_16_ID,
58 GPIO1_17_ID,
59 GPIO1_18_ID,
60 GPIO1_19_ID,
61 GPIO1_20_ID,
62 GPIO1_21_ID,
63 GPIO1_22_ID,
64 GPIO1_23_ID,
65 GPIO1_24_ID,
66 GPIO1_25_ID,
67 GPIO1_26_ID,
68 GPIO1_27_ID,
69 GPIO1_28_ID,
70 GPIO1_29_ID,
71 GPIO1_30_ID,
72 GPIO1_31_ID,
73 /* GPIO2 */
74 GPIO2_0_ID = 32,
75 GPIO2_1_ID,
76 GPIO2_2_ID,
77 GPIO2_3_ID,
78 GPIO2_4_ID,
79 GPIO2_5_ID,
80 GPIO2_6_ID,
81 GPIO2_7_ID,
82 GPIO2_8_ID,
83 GPIO2_9_ID,
84 GPIO2_10_ID,
85 GPIO2_11_ID,
86 GPIO2_12_ID,
87 GPIO2_13_ID,
88 GPIO2_14_ID,
89 GPIO2_15_ID,
90 GPIO2_16_ID,
91 GPIO2_17_ID,
92 GPIO2_18_ID,
93 GPIO2_19_ID,
94 GPIO2_20_ID,
95 GPIO2_21_ID,
96 GPIO2_22_ID,
97 GPIO2_23_ID,
98 GPIO2_24_ID,
99 GPIO2_25_ID,
100 GPIO2_26_ID,
101 GPIO2_27_ID,
102 GPIO2_28_ID,
103 GPIO2_29_ID,
104 GPIO2_30_ID,
105 GPIO2_31_ID,
106 /* GPIO3 */
107 GPIO3_0_ID = 64,
108 GPIO3_1_ID,
109 GPIO3_2_ID,
110 GPIO3_3_ID,
111 GPIO3_4_ID,
112 GPIO3_5_ID,
113 GPIO3_6_ID,
114 GPIO3_7_ID,
115 GPIO3_8_ID,
116 GPIO3_9_ID,
117 GPIO3_10_ID,
118 GPIO3_11_ID,
119 GPIO3_12_ID,
120 GPIO3_13_ID,
121 GPIO3_14_ID,
122 GPIO3_15_ID,
123 GPIO3_16_ID,
124 GPIO3_17_ID,
125 GPIO3_18_ID,
126 GPIO3_19_ID,
127 GPIO3_20_ID,
128 GPIO3_21_ID,
129 GPIO3_22_ID,
130 GPIO3_23_ID,
131 GPIO3_24_ID,
132 GPIO3_25_ID,
133 GPIO3_26_ID,
134 GPIO3_27_ID,
135 GPIO3_28_ID,
136 GPIO3_29_ID,
137 GPIO3_30_ID,
138 GPIO3_31_ID,
52}; 139};
53 140
54#define GPIO_SENSE_CONFIG_MASK 0x3 141/* Possible values for gpio interrupt line config */
142enum gpio_int_sense
143{
144 GPIO_SENSE_LOW_LEVEL, /* High-level sensitive */
145 GPIO_SENSE_HIGH_LEVEL, /* Low-level sensitive */
146 GPIO_SENSE_RISING, /* Rising-edge sensitive */
147 GPIO_SENSE_FALLING, /* Falling-edge sensitive */
148 GPIO_SENSE_EDGE_SEL, /* Detect any edge */
149};
55 150
56/* Pending events will be called in array order which allows easy 151/* Handlers will be called in declared order for a given module
57 * pioritization */ 152 Handlers of same module should be grouped together; module order
153 doesn't matter */
154#ifdef DEFINE_GPIO_VECTOR_TABLE
58 155
59/* Describes a single event for a pin */ 156/* Describes a single event for a pin */
60struct gpio_event 157struct gpio_event
61{ 158{
62 unsigned long mask; /* mask: 1 << (0...31) */ 159 uint8_t id; /* GPIOx_y_ID */
63 enum gpio_int_sense_enum sense; /* Type of sense */ 160 uint8_t sense; /* GPIO_SENSE_x */
64 void (*callback)(void); /* Callback function */ 161 void (*callback)(void); /* GPIOx_y_EVENT_CB */
65}; 162};
66 163
67/* Module corresponding to the event ID is identified by range */ 164#define GPIO_VECTOR_TBL_START() \
68enum gpio_event_bases 165 static FORCE_INLINE uintptr_t __gpio_event_vector_tbl(int __what) \
69{ 166 { \
70#if (GPIO_EVENT_MASK & USE_GPIO1_EVENTS) 167 static const struct gpio_event __tbl[] = {
71 GPIO1_EVENT_FIRST = 32*GPIO1_NUM, 168
72#endif 169#define GPIO_EVENT_VECTOR(__name, __sense) \
73#if (GPIO_EVENT_MASK & USE_GPIO2_EVENTS) 170 { .id = (__name##_ID), \
74 GPIO2_EVENT_FIRST = 32*GPIO2_NUM, 171 .sense = (__sense), \
75#endif 172 .callback = ({ void __name##_EVENT_CB(void); \
76#if (GPIO_EVENT_MASK & USE_GPIO3_EVENTS) 173 __name##_EVENT_CB; }) },
77 GPIO3_EVENT_FIRST = 32*GPIO3_NUM, 174
78#endif 175#define GPIO_VECTOR_TBL_END() \
79}; 176 }; \
177 switch (__what) \
178 { \
179 default: return (uintptr_t)__tbl; \
180 case 1: return (uintptr_t)ARRAYLEN(__tbl); \
181 } \
182 }
80 183
81#include "gpio-target.h" 184#define gpio_event_vector_tbl \
185 ((const struct gpio_event *)__gpio_event_vector_tbl(0))
186
187#define gpio_event_vector_tbl_len \
188 ((unsigned int)__gpio_event_vector_tbl(1))
189
190#endif /* DEFINE_GPIO_VECTOR_TABLE */
191
192#define GPIO_BASE_ADDR \
193 (volatile unsigned long * const [GPIO_NUM_GPIO]) { \
194 (volatile unsigned long *)GPIO1_BASE_ADDR, \
195 (volatile unsigned long *)GPIO2_BASE_ADDR, \
196 (volatile unsigned long *)GPIO3_BASE_ADDR }
197
198#define GPIO_DR (0x00 / sizeof (unsigned long)) /* 00h */
199#define GPIO_GDIR (0x04 / sizeof (unsigned long)) /* 04h */
200#define GPIO_PSR (0x08 / sizeof (unsigned long)) /* 08h */
201#define GPIO_ICR (0x0C / sizeof (unsigned long)) /* 0Ch ICR1,2 */
202#define GPIO_IMR (0x14 / sizeof (unsigned long)) /* 14h */
203#define GPIO_ISR (0x18 / sizeof (unsigned long)) /* 18h */
204#define GPIO_EDGE_SEL (0x1C / sizeof (unsigned long)) /* 1Ch */
82 205
83void gpio_init(void); 206void gpio_init(void);
84bool gpio_enable_event(enum gpio_event_ids id); 207bool gpio_enable_event(enum gpio_id id, bool enable);
85void gpio_disable_event(enum gpio_event_ids id); 208
209static FORCE_INLINE void gpio_int_clear(enum gpio_id id)
210 { GPIO_BASE_ADDR[id / 32][GPIO_ISR] = 1ul << (id % 32); }
211
212static FORCE_INLINE void gpio_int_enable(enum gpio_id id)
213 { bitset32(&GPIO_BASE_ADDR[id / 32][GPIO_IMR], 1ul << (id % 32)); }
214
215static FORCE_INLINE void gpio_int_disable(enum gpio_id id)
216 { bitclr32(&GPIO_BASE_ADDR[id / 32][GPIO_IMR], 1ul << (id % 32)); }
86 217
87#endif /* GPIO_IMX31_H */ 218#endif /* GPIO_IMX31_H */
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-04 23:27:17 +0000