diff options
Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s')
9 files changed, 36 insertions, 84 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c index f720921fad..39a2cdab04 100644 --- a/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c | |||
@@ -38,14 +38,14 @@ static struct i2c_node si4700_i2c_node = | |||
38 | void fmradio_i2c_init(void) | 38 | void fmradio_i2c_init(void) |
39 | { | 39 | { |
40 | /* RST: LOW */ | 40 | /* RST: LOW */ |
41 | imx31_regclr32(&GPIO1_DR, (1 << 26)); | 41 | bitclr32(&GPIO1_DR, (1 << 26)); |
42 | /* RST: OUT */ | 42 | /* RST: OUT */ |
43 | imx31_regset32(&GPIO1_GDIR, (1 << 26)); | 43 | bitset32(&GPIO1_GDIR, (1 << 26)); |
44 | 44 | ||
45 | /* I2C2 SCL: IN, I2C2: SDA IN */ | 45 | /* I2C2 SCL: IN, I2C2: SDA IN */ |
46 | imx31_regclr32(&GPIO2_GDIR, (3 << 14)); | 46 | bitclr32(&GPIO2_GDIR, (3 << 14)); |
47 | /* I2C2 SCL LO, I2C2 SDA LO */ | 47 | /* I2C2 SCL LO, I2C2 SDA LO */ |
48 | imx31_regclr32(&GPIO2_DR, (3 << 14)); | 48 | bitclr32(&GPIO2_DR, (3 << 14)); |
49 | 49 | ||
50 | /* open-drain pins - external pullups on PCB. Pullup default but | 50 | /* open-drain pins - external pullups on PCB. Pullup default but |
51 | * disabled */ | 51 | * disabled */ |
@@ -73,17 +73,17 @@ void fmradio_i2c_enable(bool enable) | |||
73 | { | 73 | { |
74 | /* place in GPIO mode to hold SDIO low during RESET release, | 74 | /* place in GPIO mode to hold SDIO low during RESET release, |
75 | * SEN1 should be high already (pullup) and GPIO3 left alone */ | 75 | * SEN1 should be high already (pullup) and GPIO3 left alone */ |
76 | imx31_regset32(&GPIO2_GDIR, (1 << 15)); /* SDIO OUT */ | 76 | bitset32(&GPIO2_GDIR, (1 << 15)); /* SDIO OUT */ |
77 | /* I2C2_SDA => MCU2_15 */ | 77 | /* I2C2_SDA => MCU2_15 */ |
78 | iomuxc_set_pin_mux(IOMUXC_DCD_DTE1, | 78 | iomuxc_set_pin_mux(IOMUXC_DCD_DTE1, |
79 | IOMUXC_MUX_OUT_GPIO | IOMUXC_MUX_IN_GPIO); | 79 | IOMUXC_MUX_OUT_GPIO | IOMUXC_MUX_IN_GPIO); |
80 | /* enable CLK32KMCU clock */ | 80 | /* enable CLK32KMCU clock */ |
81 | mc13783_set(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN); | 81 | mc13783_set(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN); |
82 | /* enable the fm chip (release RESET) */ | 82 | /* enable the fm chip (release RESET) */ |
83 | imx31_regset32(&GPIO1_DR, (1 << 26)); | 83 | bitset32(&GPIO1_DR, (1 << 26)); |
84 | sleep(HZ/100); | 84 | sleep(HZ/100); |
85 | /* busmode should be selected - OK to release SDIO */ | 85 | /* busmode should be selected - OK to release SDIO */ |
86 | imx31_regclr32(&GPIO2_GDIR, (1 << 15)); /* SDIO IN */ | 86 | bitclr32(&GPIO2_GDIR, (1 << 15)); /* SDIO IN */ |
87 | /* restore pin mux (MCU2_15 => I2C2_SDA) */ | 87 | /* restore pin mux (MCU2_15 => I2C2_SDA) */ |
88 | iomuxc_set_pin_mux(IOMUXC_DCD_DTE1, | 88 | iomuxc_set_pin_mux(IOMUXC_DCD_DTE1, |
89 | IOMUXC_MUX_OUT_ALT2 | IOMUXC_MUX_IN_ALT2); | 89 | IOMUXC_MUX_OUT_ALT2 | IOMUXC_MUX_IN_ALT2); |
@@ -97,7 +97,7 @@ void fmradio_i2c_enable(bool enable) | |||
97 | we can diable the i2c module when not in use */ | 97 | we can diable the i2c module when not in use */ |
98 | i2c_enable_node(&si4700_i2c_node, false); | 98 | i2c_enable_node(&si4700_i2c_node, false); |
99 | /* disable the fm chip */ | 99 | /* disable the fm chip */ |
100 | imx31_regclr32(&GPIO1_DR, (1 << 26)); | 100 | bitclr32(&GPIO1_DR, (1 << 26)); |
101 | /* disable CLK32KMCU clock */ | 101 | /* disable CLK32KMCU clock */ |
102 | mc13783_clear(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN); | 102 | mc13783_clear(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN); |
103 | } | 103 | } |
diff --git a/firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c index c2ec0d6cab..6291a9cf18 100644 --- a/firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c | |||
@@ -35,11 +35,11 @@ void i2s_reset(void) | |||
35 | * WM Codec post divider (MCLKDIV=1.5): | 35 | * WM Codec post divider (MCLKDIV=1.5): |
36 | * INT_BIT_CLK (MCLK) / 1.5 = 11289600Hz = 256*fs = SYSCLK | 36 | * INT_BIT_CLK (MCLK) / 1.5 = 11289600Hz = 256*fs = SYSCLK |
37 | */ | 37 | */ |
38 | imx31_regmod32(&CCM_PDR1, | 38 | bitmod32(&CCM_PDR1, |
39 | ((1-1) << CCM_PDR1_SSI1_PRE_PODF_POS) | | 39 | ((1-1) << CCM_PDR1_SSI1_PRE_PODF_POS) | |
40 | ((5-1) << CCM_PDR1_SSI1_PODF_POS) | | 40 | ((5-1) << CCM_PDR1_SSI1_PODF_POS) | |
41 | ((8-1) << CCM_PDR1_SSI2_PRE_PODF_POS) | | 41 | ((8-1) << CCM_PDR1_SSI2_PRE_PODF_POS) | |
42 | ((64-1) << CCM_PDR1_SSI2_PODF_POS), | 42 | ((64-1) << CCM_PDR1_SSI2_PODF_POS), |
43 | CCM_PDR1_SSI1_PODF | CCM_PDR1_SSI2_PODF | | 43 | CCM_PDR1_SSI1_PODF | CCM_PDR1_SSI2_PODF | |
44 | CCM_PDR1_SSI1_PRE_PODF | CCM_PDR1_SSI2_PRE_PODF); | 44 | CCM_PDR1_SSI1_PRE_PODF | CCM_PDR1_SSI2_PRE_PODF); |
45 | } | 45 | } |
diff --git a/firmware/target/arm/imx31/gigabeat-s/lcd-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/lcd-gigabeat-s.c index cadd0e7ae8..cd583ecd6b 100644 --- a/firmware/target/arm/imx31/gigabeat-s/lcd-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/lcd-gigabeat-s.c | |||
@@ -133,13 +133,13 @@ static void lcd_set_power(bool powered) | |||
133 | lcd_powered = false; | 133 | lcd_powered = false; |
134 | lcd_write_reg(0x04, 0x00); | 134 | lcd_write_reg(0x04, 0x00); |
135 | lcd_enable_interface(false); | 135 | lcd_enable_interface(false); |
136 | imx31_regclr32(&GPIO3_DR, (1 << 12)); | 136 | bitclr32(&GPIO3_DR, (1 << 12)); |
137 | mc13783_clear(MC13783_REGULATOR_MODE1, MC13783_VCAMEN); | 137 | mc13783_clear(MC13783_REGULATOR_MODE1, MC13783_VCAMEN); |
138 | } | 138 | } |
139 | else | 139 | else |
140 | { | 140 | { |
141 | mc13783_set(MC13783_REGULATOR_MODE1, MC13783_VCAMEN); | 141 | mc13783_set(MC13783_REGULATOR_MODE1, MC13783_VCAMEN); |
142 | imx31_regset32(&GPIO3_DR, (1 << 12)); | 142 | bitset32(&GPIO3_DR, (1 << 12)); |
143 | lcd_enable_interface(true); | 143 | lcd_enable_interface(true); |
144 | lcd_write_reg(0x04, 0x01); | 144 | lcd_write_reg(0x04, 0x01); |
145 | lcd_powered = true; | 145 | lcd_powered = true; |
diff --git a/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c index cfd83f0794..15f9d0bd1c 100644 --- a/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c | |||
@@ -458,7 +458,7 @@ void pcm_rec_dma_stop(void) | |||
458 | /* Stop receiving data */ | 458 | /* Stop receiving data */ |
459 | sdma_channel_stop(DMA_REC_CH_NUM); | 459 | sdma_channel_stop(DMA_REC_CH_NUM); |
460 | 460 | ||
461 | imx31_regclr32(&SSI_SIER1, SSI_SIER_RDMAE); | 461 | bitclr32(&SSI_SIER1, SSI_SIER_RDMAE); |
462 | 462 | ||
463 | SSI_SCR1 &= ~SSI_SCR_RE; /* Disable RX */ | 463 | SSI_SCR1 &= ~SSI_SCR_RE; /* Disable RX */ |
464 | SSI_SRCR1 &= ~SSI_SRCR_RFEN0; /* Disable RX FIFO */ | 464 | SSI_SRCR1 &= ~SSI_SRCR_RFEN0; /* Disable RX FIFO */ |
diff --git a/firmware/target/arm/imx31/gigabeat-s/power-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/power-gigabeat-s.c index 4540be671a..9d7d30547b 100644 --- a/firmware/target/arm/imx31/gigabeat-s/power-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/power-gigabeat-s.c | |||
@@ -85,17 +85,17 @@ void ide_power_enable(bool on) | |||
85 | if (!on) | 85 | if (!on) |
86 | { | 86 | { |
87 | /* Bus must be isolated before power off */ | 87 | /* Bus must be isolated before power off */ |
88 | imx31_regset32(&GPIO2_DR, (1 << 16)); | 88 | bitset32(&GPIO2_DR, (1 << 16)); |
89 | } | 89 | } |
90 | 90 | ||
91 | /* HD power switch */ | 91 | /* HD power switch */ |
92 | imx31_regmod32(&GPIO3_DR, on ? (1 << 5) : 0, (1 << 5)); | 92 | bitmod32(&GPIO3_DR, on ? (1 << 5) : 0, (1 << 5)); |
93 | 93 | ||
94 | if (on) | 94 | if (on) |
95 | { | 95 | { |
96 | /* Bus switch may be turned on after powerup */ | 96 | /* Bus switch may be turned on after powerup */ |
97 | sleep(HZ/10); | 97 | sleep(HZ/10); |
98 | imx31_regclr32(&GPIO2_DR, (1 << 16)); | 98 | bitclr32(&GPIO2_DR, (1 << 16)); |
99 | } | 99 | } |
100 | } | 100 | } |
101 | 101 | ||
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c index 80b6f22397..f458561731 100644 --- a/firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c | |||
@@ -186,18 +186,18 @@ void INIT_ATTR system_init(void) | |||
186 | cpu_frequency = ccm_get_mcu_clk(); | 186 | cpu_frequency = ccm_get_mcu_clk(); |
187 | 187 | ||
188 | /* MCR WFI enables wait mode (CCM_CCMR_LPM_WAIT_MODE = 0) */ | 188 | /* MCR WFI enables wait mode (CCM_CCMR_LPM_WAIT_MODE = 0) */ |
189 | imx31_regclr32(&CCM_CCMR, CCM_CCMR_LPM); | 189 | bitclr32(&CCM_CCMR, CCM_CCMR_LPM); |
190 | 190 | ||
191 | iim_init(); | 191 | iim_init(); |
192 | 192 | ||
193 | imx31_regset32(&SDHC1_CLOCK_CONTROL, STOP_CLK); | 193 | bitset32(&SDHC1_CLOCK_CONTROL, STOP_CLK); |
194 | imx31_regset32(&SDHC2_CLOCK_CONTROL, STOP_CLK); | 194 | bitset32(&SDHC2_CLOCK_CONTROL, STOP_CLK); |
195 | imx31_regset32(&RNGA_CONTROL, RNGA_CONTROL_SLEEP); | 195 | bitset32(&RNGA_CONTROL, RNGA_CONTROL_SLEEP); |
196 | imx31_regclr32(&UCR1_1, EUARTUCR1_UARTEN); | 196 | bitclr32(&UCR1_1, EUARTUCR1_UARTEN); |
197 | imx31_regclr32(&UCR1_2, EUARTUCR1_UARTEN); | 197 | bitclr32(&UCR1_2, EUARTUCR1_UARTEN); |
198 | imx31_regclr32(&UCR1_3, EUARTUCR1_UARTEN); | 198 | bitclr32(&UCR1_3, EUARTUCR1_UARTEN); |
199 | imx31_regclr32(&UCR1_4, EUARTUCR1_UARTEN); | 199 | bitclr32(&UCR1_4, EUARTUCR1_UARTEN); |
200 | imx31_regclr32(&UCR1_5, EUARTUCR1_UARTEN); | 200 | bitclr32(&UCR1_5, EUARTUCR1_UARTEN); |
201 | 201 | ||
202 | for (i = 0; i < ARRAYLEN(disable_clocks); i++) | 202 | for (i = 0; i < ARRAYLEN(disable_clocks); i++) |
203 | ccm_module_clock_gating(disable_clocks[i], CGM_OFF); | 203 | ccm_module_clock_gating(disable_clocks[i], CGM_OFF); |
@@ -207,49 +207,6 @@ void INIT_ATTR system_init(void) | |||
207 | gpio_init(); | 207 | gpio_init(); |
208 | } | 208 | } |
209 | 209 | ||
210 | void __attribute__((naked)) imx31_regmod32(volatile uint32_t *reg_p, | ||
211 | uint32_t value, | ||
212 | uint32_t mask) | ||
213 | { | ||
214 | asm volatile("and r1, r1, r2 \n" | ||
215 | "mrs ip, cpsr \n" | ||
216 | "cpsid if \n" | ||
217 | "ldr r3, [r0] \n" | ||
218 | "bic r3, r3, r2 \n" | ||
219 | "orr r3, r3, r1 \n" | ||
220 | "str r3, [r0] \n" | ||
221 | "msr cpsr_c, ip \n" | ||
222 | "bx lr \n"); | ||
223 | (void)reg_p; (void)value; (void)mask; | ||
224 | } | ||
225 | |||
226 | void __attribute__((naked)) imx31_regset32(volatile uint32_t *reg_p, | ||
227 | uint32_t mask) | ||
228 | { | ||
229 | asm volatile("mrs r3, cpsr \n" | ||
230 | "cpsid if \n" | ||
231 | "ldr r2, [r0] \n" | ||
232 | "orr r2, r2, r1 \n" | ||
233 | "str r2, [r0] \n" | ||
234 | "msr cpsr_c, r3 \n" | ||
235 | "bx lr \n"); | ||
236 | (void)reg_p; (void)mask; | ||
237 | } | ||
238 | |||
239 | void __attribute__((naked)) imx31_regclr32(volatile uint32_t *reg_p, | ||
240 | uint32_t mask) | ||
241 | { | ||
242 | asm volatile("mrs r3, cpsr \n" | ||
243 | "cpsid if \n" | ||
244 | "ldr r2, [r0] \n" | ||
245 | "bic r2, r2, r1 \n" | ||
246 | "str r2, [r0] \n" | ||
247 | "msr cpsr_c, r3 \n" | ||
248 | "bx lr \n"); | ||
249 | (void)reg_p; (void)mask; | ||
250 | } | ||
251 | |||
252 | |||
253 | void system_prepare_fw_start(void) | 210 | void system_prepare_fw_start(void) |
254 | { | 211 | { |
255 | dvfs_dptc_stop(); | 212 | dvfs_dptc_stop(); |
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-target.h b/firmware/target/arm/imx31/gigabeat-s/system-target.h index af95471db6..a13f87a4cd 100644 --- a/firmware/target/arm/imx31/gigabeat-s/system-target.h +++ b/firmware/target/arm/imx31/gigabeat-s/system-target.h | |||
@@ -51,11 +51,6 @@ void tick_stop(void); | |||
51 | void kernel_device_init(void); | 51 | void kernel_device_init(void); |
52 | void system_halt(void); | 52 | void system_halt(void); |
53 | 53 | ||
54 | void imx31_regmod32(volatile uint32_t *reg_p, uint32_t value, | ||
55 | uint32_t mask); | ||
56 | void imx31_regset32(volatile uint32_t *reg_p, uint32_t mask); | ||
57 | void imx31_regclr32(volatile uint32_t *reg_p, uint32_t mask); | ||
58 | |||
59 | #define KDEV_INIT | 54 | #define KDEV_INIT |
60 | 55 | ||
61 | struct ARM_REGS { | 56 | struct ARM_REGS { |
diff --git a/firmware/target/arm/imx31/gigabeat-s/usb-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/usb-gigabeat-s.c index d873c19ed3..016f24fc48 100644 --- a/firmware/target/arm/imx31/gigabeat-s/usb-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/usb-gigabeat-s.c | |||
@@ -40,16 +40,16 @@ static void enable_transceiver(bool enable) | |||
40 | { | 40 | { |
41 | if (GPIO1_DR & (1 << 30)) | 41 | if (GPIO1_DR & (1 << 30)) |
42 | { | 42 | { |
43 | imx31_regclr32(&GPIO3_DR, (1 << 16)); /* Reset ISP1504 */ | 43 | bitclr32(&GPIO3_DR, (1 << 16)); /* Reset ISP1504 */ |
44 | sleep(HZ/100); | 44 | sleep(HZ/100); |
45 | imx31_regset32(&GPIO3_DR, (1 << 16)); | 45 | bitset32(&GPIO3_DR, (1 << 16)); |
46 | sleep(HZ/10); | 46 | sleep(HZ/10); |
47 | imx31_regclr32(&GPIO1_DR, (1 << 30)); /* Select ISP1504 */ | 47 | bitclr32(&GPIO1_DR, (1 << 30)); /* Select ISP1504 */ |
48 | } | 48 | } |
49 | } | 49 | } |
50 | else | 50 | else |
51 | { | 51 | { |
52 | imx31_regset32(&GPIO1_DR, (1 << 30)); /* Deselect ISP1504 */ | 52 | bitset32(&GPIO1_DR, (1 << 30)); /* Deselect ISP1504 */ |
53 | } | 53 | } |
54 | } | 54 | } |
55 | 55 | ||
diff --git a/firmware/target/arm/imx31/gigabeat-s/wmcodec-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/wmcodec-gigabeat-s.c index 96324cc162..36ab33a5dc 100644 --- a/firmware/target/arm/imx31/gigabeat-s/wmcodec-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/wmcodec-gigabeat-s.c | |||
@@ -48,13 +48,13 @@ void audiohw_init(void) | |||
48 | 48 | ||
49 | audiohw_preinit(); | 49 | audiohw_preinit(); |
50 | 50 | ||
51 | imx31_regset32(&GPIO3_DR, (1 << 21)); /* Turn on analogue LDO */ | 51 | bitset32(&GPIO3_DR, (1 << 21)); /* Turn on analogue LDO */ |
52 | } | 52 | } |
53 | 53 | ||
54 | void audiohw_enable_headphone_jack(bool enable) | 54 | void audiohw_enable_headphone_jack(bool enable) |
55 | { | 55 | { |
56 | /* Turn headphone jack output on or off. */ | 56 | /* Turn headphone jack output on or off. */ |
57 | imx31_regmod32(&GPIO3_DR, enable ? (1 << 22) : 0, (1 << 22)); | 57 | bitmod32(&GPIO3_DR, enable ? (1 << 22) : 0, (1 << 22)); |
58 | } | 58 | } |
59 | 59 | ||
60 | void wmcodec_write(int reg, int data) | 60 | void wmcodec_write(int reg, int data) |