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Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c')
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c b/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c
index e307057978..542f6eb633 100644
--- a/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c
@@ -44,17 +44,17 @@ void audiohw_init(void)
44 /* How SYSCLK for codec is derived (USBPLL=338.688MHz). 44 /* How SYSCLK for codec is derived (USBPLL=338.688MHz).
45 * 45 *
46 * SSI post dividers (SSI2 PODF=4, SSI2 PRE PODF=0): 46 * SSI post dividers (SSI2 PODF=4, SSI2 PRE PODF=0):
47 * 338688000Hz / 5 = 67737600Hz = ssi2_clk 47 * 338688000Hz / 5 = 67737600Hz = ssi1_clk
48 * 48 *
49 * SSI bit clock dividers (DIV2=1, PSR=0, PM=0): 49 * SSI bit clock dividers (DIV2=1, PSR=0, PM=0):
50 * ssi2_clk / 4 = 16934400Hz = INT_BIT_CLK (MCLK) 50 * ssi1_clk / 4 = 16934400Hz = INT_BIT_CLK (MCLK)
51 * 51 *
52 * WM Codec post divider (MCLKDIV=1.5): 52 * WM Codec post divider (MCLKDIV=1.5):
53 * INT_BIT_CLK (MCLK) / 1.5 = 11289600Hz = 256*fs = SYSCLK 53 * INT_BIT_CLK (MCLK) / 1.5 = 11289600Hz = 256*fs = SYSCLK
54 */ 54 */
55 imx31_regmod32(&CLKCTL_PDR1, 55 imx31_regmod32(&CLKCTL_PDR1,
56 PDR1_SSI1_PODFw(64-1) | PDR1_SSI2_PODFw(5-1) | 56 PDR1_SSI1_PODFw(5-1) | PDR1_SSI2_PODFw(64-1) |
57 PDR1_SSI1_PRE_PODFw(8-1) | PDR1_SSI2_PRE_PODFw(1-1), 57 PDR1_SSI1_PRE_PODFw(1-1) | PDR1_SSI2_PRE_PODFw(8-1),
58 PDR1_SSI1_PODF | PDR1_SSI2_PODF | 58 PDR1_SSI1_PODF | PDR1_SSI2_PODF |
59 PDR1_SSI1_PRE_PODF | PDR1_SSI2_PRE_PODF); 59 PDR1_SSI1_PRE_PODF | PDR1_SSI2_PRE_PODF);
60 60