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Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c')
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c20
1 files changed, 15 insertions, 5 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c b/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c
index 7a877e1415..0bb9e49506 100644
--- a/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c
@@ -41,13 +41,23 @@ static struct i2c_node wm8978_i2c_node =
41 41
42void audiohw_init(void) 42void audiohw_init(void)
43{ 43{
44 /* USB PLL = 338.688MHz, /30 = 11.2896MHz = 256Fs */ 44 /* How SYSCLK for codec is derived (USBPLL=338.688MHz).
45 *
46 * SSI post dividers (SSI2 PODF=4, SSI2 PRE PODF=0):
47 * 338688000Hz / 5 = 67737600Hz = ssi2_clk
48 *
49 * SSI bit clock dividers (DIV2=1, PSR=0, PM=0):
50 * ssi2_clk / 4 = 16934400Hz = INT_BIT_CLK (MCLK)
51 *
52 * WM Codec post divider (MCLKDIV=1.5):
53 * INT_BIT_CLK (MCLK) / 1.5 = 11289600Hz = 256*fs = SYSCLK
54 */
45 imx31_regmod32(&CLKCTL_PDR1, 55 imx31_regmod32(&CLKCTL_PDR1,
46 PDR1_SSI1_PODFw(64-1) | PDR1_SSI2_PODFw(5-1), 56 PDR1_SSI1_PODFw(64-1) | PDR1_SSI2_PODFw(5-1) |
47 PDR1_SSI1_PODF | PDR1_SSI2_PODF); 57 PDR1_SSI1_PRE_PODFw(8-1) | PDR1_SSI2_PRE_PODFw(1-1),
48 imx31_regmod32(&CLKCTL_PDR1, 58 PDR1_SSI1_PODF | PDR1_SSI2_PODF |
49 PDR1_SSI1_PRE_PODFw(4-1) | PDR1_SSI2_PRE_PODFw(1-1),
50 PDR1_SSI1_PRE_PODF | PDR1_SSI2_PRE_PODF); 59 PDR1_SSI1_PRE_PODF | PDR1_SSI2_PRE_PODF);
60
51 i2c_enable_node(&wm8978_i2c_node, true); 61 i2c_enable_node(&wm8978_i2c_node, true);
52 62
53 audiohw_preinit(); 63 audiohw_preinit();