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Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/system-target.h')
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/system-target.h14
1 files changed, 9 insertions, 5 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-target.h b/firmware/target/arm/imx31/gigabeat-s/system-target.h
index 1f7a2475af..327d72b7bc 100644
--- a/firmware/target/arm/imx31/gigabeat-s/system-target.h
+++ b/firmware/target/arm/imx31/gigabeat-s/system-target.h
@@ -33,24 +33,28 @@ static inline void udelay(unsigned int usecs)
33#define __dbg_hw_info(...) 0 33#define __dbg_hw_info(...) 0
34#define __dbg_ports(...) 0 34#define __dbg_ports(...) 0
35 35
36void system_prepare_fw_start(void);
37void tick_stop(void);
38
36#define HAVE_INVALIDATE_ICACHE 39#define HAVE_INVALIDATE_ICACHE
37static inline void invalidate_icache(void) 40static inline void invalidate_icache(void)
38{ 41{
39 long rd = 0;
40 asm volatile( 42 asm volatile(
41 "mcr p15, 0, %0, c7, c10, 0 \n" 43 /* Clean and invalidate entire data cache */
44 "mcr p15, 0, %0, c7, c14, 0 \n"
45 /* Invalidate entire instruction cache */
42 "mcr p15, 0, %0, c7, c5, 0 \n" 46 "mcr p15, 0, %0, c7, c5, 0 \n"
43 : : "r"(rd) 47 : : "r"(0)
44 ); 48 );
45} 49}
46 50
47#define HAVE_FLUSH_ICACHE 51#define HAVE_FLUSH_ICACHE
48static inline void flush_icache(void) 52static inline void flush_icache(void)
49{ 53{
50 long rd = 0;
51 asm volatile ( 54 asm volatile (
55 /* Clean entire data cache */
52 "mcr p15, 0, %0, c7, c10, 0 \n" 56 "mcr p15, 0, %0, c7, c10, 0 \n"
53 : : "r"(rd) 57 : : "r"(0)
54 ); 58 );
55} 59}
56 60