summaryrefslogtreecommitdiff
path: root/firmware/target/arm/imx31/gigabeat-s/system-target.h
diff options
context:
space:
mode:
Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/system-target.h')
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/system-target.h9
1 files changed, 8 insertions, 1 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-target.h b/firmware/target/arm/imx31/gigabeat-s/system-target.h
index 17f1593f62..e48b5d1ed1 100644
--- a/firmware/target/arm/imx31/gigabeat-s/system-target.h
+++ b/firmware/target/arm/imx31/gigabeat-s/system-target.h
@@ -42,8 +42,13 @@ static inline void invalidate_icache(void)
42 asm volatile( 42 asm volatile(
43 /* Clean and invalidate entire data cache */ 43 /* Clean and invalidate entire data cache */
44 "mcr p15, 0, %0, c7, c14, 0 \n" 44 "mcr p15, 0, %0, c7, c14, 0 \n"
45 /* Invalidate entire instruction cache */ 45 /* Invalidate entire intruction cache
46 * Also flushes the branch target cache */
46 "mcr p15, 0, %0, c7, c5, 0 \n" 47 "mcr p15, 0, %0, c7, c5, 0 \n"
48 /* Data synchronization barrier */
49 "mcr p15, 0, %0, c7, c10, 4 \n"
50 /* Flush prefetch buffer */
51 "mcr p15, 0, %0, c7, c5, 4 \n"
47 : : "r"(0) 52 : : "r"(0)
48 ); 53 );
49} 54}
@@ -54,6 +59,8 @@ static inline void flush_icache(void)
54 asm volatile ( 59 asm volatile (
55 /* Clean entire data cache */ 60 /* Clean entire data cache */
56 "mcr p15, 0, %0, c7, c10, 0 \n" 61 "mcr p15, 0, %0, c7, c10, 0 \n"
62 /* Data synchronization barrier */
63 "mcr p15, 0, r2, c7, c10, 4 \n"
57 : : "r"(0) 64 : : "r"(0)
58 ); 65 );
59} 66}