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Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/mc13783-imx31.c')
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/mc13783-imx31.c360
1 files changed, 0 insertions, 360 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/mc13783-imx31.c b/firmware/target/arm/imx31/gigabeat-s/mc13783-imx31.c
deleted file mode 100644
index 2c5af8d5b7..0000000000
--- a/firmware/target/arm/imx31/gigabeat-s/mc13783-imx31.c
+++ /dev/null
@@ -1,360 +0,0 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (c) 2008 by Michael Sevakis
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21#include "system.h"
22#include "cpu.h"
23#include "spi-imx31.h"
24#include "gpio-imx31.h"
25#include "mc13783.h"
26#include "debug.h"
27#include "kernel.h"
28
29#include "power-imx31.h"
30#include "button-target.h"
31#include "adc-target.h"
32#include "usb-target.h"
33
34#ifdef BOOTLOADER
35#define PMIC_DRIVER_CLOSE
36#endif
37
38/* This is all based on communicating with the MC13783 PMU which is on
39 * CSPI2 with the chip select at 0. The LCD controller resides on
40 * CSPI3 cs1, but we have no idea how to communicate to it */
41static struct spi_node mc13783_spi =
42{
43 CSPI2_NUM, /* CSPI module 2 */
44 CSPI_CONREG_CHIP_SELECT_SS0 | /* Chip select 0 */
45 CSPI_CONREG_DRCTL_DONT_CARE | /* Don't care about CSPI_RDY */
46 CSPI_CONREG_DATA_RATE_DIV_4 | /* Clock = IPG_CLK/4 - 16.5MHz */
47 CSPI_BITCOUNT(32-1) | /* All 32 bits are to be transferred */
48 CSPI_CONREG_SSPOL | /* SS active high */
49 CSPI_CONREG_SSCTL | /* Negate SS between SPI bursts */
50 CSPI_CONREG_MODE, /* Master mode */
51 0, /* SPI clock - no wait states */
52};
53
54extern const struct mc13783_event_list mc13783_event_list;
55
56static int mc13783_thread_stack[DEFAULT_STACK_SIZE/sizeof(int)];
57static const char *mc13783_thread_name = "pmic";
58static struct wakeup mc13783_wake;
59
60/* Tracking for which interrupts are enabled */
61static uint32_t pmic_int_enabled[2] =
62 { 0x00000000, 0x00000000 };
63
64static const unsigned char pmic_intm_regs[2] =
65 { MC13783_INTERRUPT_MASK0, MC13783_INTERRUPT_MASK1 };
66
67static const unsigned char pmic_ints_regs[2] =
68 { MC13783_INTERRUPT_STATUS0, MC13783_INTERRUPT_STATUS1 };
69
70#ifdef PMIC_DRIVER_CLOSE
71static bool pmic_close = false;
72static unsigned int mc13783_thread_id = 0;
73#endif
74
75static void mc13783_interrupt_thread(void)
76{
77 uint32_t pending[2];
78
79 /* Enable mc13783 GPIO event */
80 gpio_enable_event(MC13783_EVENT_ID);
81
82 while (1)
83 {
84 const struct mc13783_event *event, *event_last;
85
86 wakeup_wait(&mc13783_wake, TIMEOUT_BLOCK);
87
88#ifdef PMIC_DRIVER_CLOSE
89 if (pmic_close)
90 break;
91#endif
92
93 mc13783_read_regset(pmic_ints_regs, pending, 2);
94
95 /* Only clear interrupts being dispatched */
96 pending[0] &= pmic_int_enabled[0];
97 pending[1] &= pmic_int_enabled[1];
98
99 mc13783_write_regset(pmic_ints_regs, pending, 2);
100
101 /* Whatever is going to be serviced in this loop has been
102 * acknowledged. Reenable interrupt and if anything was still
103 * pending or became pending again, another signal will be
104 * generated. */
105 imx31_regset32(&MC13783_GPIO_IMR, 1ul << MC13783_GPIO_LINE);
106
107 event = mc13783_event_list.events;
108 event_last = event + mc13783_event_list.count;
109
110 /* .count is surely expected to be > 0 */
111 do
112 {
113 enum mc13783_event_sets set = event->set;
114 uint32_t pnd = pending[set];
115 uint32_t mask = event->mask;
116
117 if (pnd & mask)
118 {
119 event->callback();
120 pnd &= ~mask;
121 pending[set] = pnd;
122 }
123
124 if ((pending[0] | pending[1]) == 0)
125 break; /* Teminate early if nothing more to service */
126 }
127 while (++event < event_last);
128 }
129
130#ifdef PMIC_DRIVER_CLOSE
131 gpio_disable_event(MC13783_EVENT_ID);
132#endif
133}
134
135/* GPIO interrupt handler for mc13783 */
136void mc13783_event(void)
137{
138 /* Mask the interrupt (unmasked when PMIC thread services it). */
139 imx31_regclr32(&MC13783_GPIO_IMR, 1ul << MC13783_GPIO_LINE);
140 MC13783_GPIO_ISR = (1ul << MC13783_GPIO_LINE);
141 wakeup_signal(&mc13783_wake);
142}
143
144void mc13783_init(void)
145{
146 /* Serial interface must have been initialized first! */
147 wakeup_init(&mc13783_wake);
148
149 /* Enable the PMIC SPI module */
150 spi_enable_module(&mc13783_spi);
151
152 /* Mask any PMIC interrupts for now - modules will enable them as
153 * required */
154 mc13783_write(MC13783_INTERRUPT_MASK0, 0xffffff);
155 mc13783_write(MC13783_INTERRUPT_MASK1, 0xffffff);
156
157 MC13783_GPIO_ISR = (1ul << MC13783_GPIO_LINE);
158
159#ifdef PMIC_DRIVER_CLOSE
160 mc13783_thread_id =
161#endif
162 create_thread(mc13783_interrupt_thread,
163 mc13783_thread_stack, sizeof(mc13783_thread_stack), 0,
164 mc13783_thread_name IF_PRIO(, PRIORITY_REALTIME) IF_COP(, CPU));
165}
166
167#ifdef PMIC_DRIVER_CLOSE
168void mc13783_close(void)
169{
170 unsigned int thread_id = mc13783_thread_id;
171
172 if (thread_id == 0)
173 return;
174
175 mc13783_thread_id = 0;
176
177 pmic_close = true;
178 wakeup_signal(&mc13783_wake);
179 thread_wait(thread_id);
180}
181#endif /* PMIC_DRIVER_CLOSE */
182
183bool mc13783_enable_event(enum mc13783_event_ids id)
184{
185 const struct mc13783_event * const event =
186 &mc13783_event_list.events[id];
187 int set = event->set;
188 uint32_t mask = event->mask;
189
190 spi_lock(&mc13783_spi);
191
192 pmic_int_enabled[set] |= mask;
193 mc13783_clear(pmic_intm_regs[set], mask);
194
195 spi_unlock(&mc13783_spi);
196
197 return true;
198}
199
200void mc13783_disable_event(enum mc13783_event_ids id)
201{
202 const struct mc13783_event * const event =
203 &mc13783_event_list.events[id];
204 int set = event->set;
205 uint32_t mask = event->mask;
206
207 spi_lock(&mc13783_spi);
208
209 pmic_int_enabled[set] &= ~mask;
210 mc13783_set(pmic_intm_regs[set], mask);
211
212 spi_unlock(&mc13783_spi);
213}
214
215uint32_t mc13783_set(unsigned address, uint32_t bits)
216{
217 spi_lock(&mc13783_spi);
218
219 uint32_t data = mc13783_read(address);
220
221 if (data != MC13783_DATA_ERROR)
222 mc13783_write(address, data | bits);
223
224 spi_unlock(&mc13783_spi);
225
226 return data;
227}
228
229uint32_t mc13783_clear(unsigned address, uint32_t bits)
230{
231 spi_lock(&mc13783_spi);
232
233 uint32_t data = mc13783_read(address);
234
235 if (data != MC13783_DATA_ERROR)
236 mc13783_write(address, data & ~bits);
237
238 spi_unlock(&mc13783_spi);
239
240 return data;
241}
242
243int mc13783_write(unsigned address, uint32_t data)
244{
245 struct spi_transfer xfer;
246 uint32_t packet;
247
248 if (address >= MC13783_NUM_REGS)
249 return -1;
250
251 packet = (1 << 31) | (address << 25) | (data & 0xffffff);
252 xfer.txbuf = &packet;
253 xfer.rxbuf = &packet;
254 xfer.count = 1;
255
256 if (!spi_transfer(&mc13783_spi, &xfer))
257 return -1;
258
259 return 1 - xfer.count;
260}
261
262uint32_t mc13783_write_masked(unsigned address, uint32_t data, uint32_t mask)
263{
264 uint32_t old;
265
266 spi_lock(&mc13783_spi);
267
268 old = mc13783_read(address);
269
270 if (old != MC13783_DATA_ERROR)
271 {
272 data = (old & ~mask) | (data & mask);
273
274 if (mc13783_write(address, data) != 1)
275 old = MC13783_DATA_ERROR;
276 }
277
278 spi_unlock(&mc13783_spi);
279
280 return old;
281}
282
283int mc13783_write_regset(const unsigned char *regs, const uint32_t *data,
284 int count)
285{
286 int i;
287 struct spi_transfer xfer;
288 uint32_t packets[MC13783_NUM_REGS];
289
290 if ((unsigned)count > MC13783_NUM_REGS)
291 return -1;
292
293 for (i = 0; i < count; i++)
294 {
295 uint32_t reg = regs[i];
296
297 if (reg >= MC13783_NUM_REGS)
298 return -1;
299
300 packets[i] = (1 << 31) | (reg << 25) | (data[i] & 0xffffff);
301 }
302
303 xfer.txbuf = packets;
304 xfer.rxbuf = packets;
305 xfer.count = count;
306
307 if (!spi_transfer(&mc13783_spi, &xfer))
308 return -1;
309
310 return count - xfer.count;
311}
312
313uint32_t mc13783_read(unsigned address)
314{
315 uint32_t packet;
316 struct spi_transfer xfer;
317
318 if (address >= MC13783_NUM_REGS)
319 return MC13783_DATA_ERROR;
320
321 packet = address << 25;
322
323 xfer.txbuf = &packet;
324 xfer.rxbuf = &packet;
325 xfer.count = 1;
326
327 if (!spi_transfer(&mc13783_spi, &xfer))
328 return MC13783_DATA_ERROR;
329
330 return packet;
331}
332
333int mc13783_read_regset(const unsigned char *regs, uint32_t *buffer,
334 int count)
335{
336 int i;
337 struct spi_transfer xfer;
338
339 if ((unsigned)count > MC13783_NUM_REGS)
340 return -1;
341
342 for (i = 0; i < count; i++)
343 {
344 unsigned reg = regs[i];
345
346 if (reg >= MC13783_NUM_REGS)
347 return -1;
348
349 buffer[i] = reg << 25;
350 }
351
352 xfer.txbuf = buffer;
353 xfer.rxbuf = buffer;
354 xfer.count = count;
355
356 if (!spi_transfer(&mc13783_spi, &xfer))
357 return -1;
358
359 return count - xfer.count;
360}
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