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Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c')
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c32
1 files changed, 16 insertions, 16 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c b/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c
index 3c44a156b0..c2fddc40a7 100644
--- a/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c
@@ -7,7 +7,6 @@
7 7
8extern void (*tick_funcs[MAX_NUM_TICK_TASKS])(void); 8extern void (*tick_funcs[MAX_NUM_TICK_TASKS])(void);
9 9
10#ifndef BOOTLOADER
11static __attribute__((interrupt("IRQ"))) void EPIT1_HANDLER(void) 10static __attribute__((interrupt("IRQ"))) void EPIT1_HANDLER(void)
12{ 11{
13 int i; 12 int i;
@@ -23,14 +22,11 @@ static __attribute__((interrupt("IRQ"))) void EPIT1_HANDLER(void)
23 22
24 current_tick++; 23 current_tick++;
25} 24}
26#endif
27 25
28void tick_start(unsigned int interval_in_ms) 26void tick_start(unsigned int interval_in_ms)
29{ 27{
30 EPITCR1 &= ~(1 << 0); /* Disable the counter */ 28 CLKCTL_CGR0 |= (3 << 6); /* EPIT1 module clock ON - before writing regs! */
31 EPITCR1 |= (1 << 16); /* Reset */ 29 EPITCR1 &= ~((1 << 2) | (1 << 0)); /* Disable the counter */
32
33 CLKCTL_CGR0 |= (0x3 << 6); /* Clock ON */
34 CLKCTL_WIMR0 &= ~(1 << 23); /* Clear wakeup mask */ 30 CLKCTL_WIMR0 &= ~(1 << 23); /* Clear wakeup mask */
35 31
36 /* NOTE: This isn't really accurate yet but it's close enough to work 32 /* NOTE: This isn't really accurate yet but it's close enough to work
@@ -39,17 +35,21 @@ void tick_start(unsigned int interval_in_ms)
39 /* CLKSRC=32KHz, EPIT Output Disconnected, Enabled 35 /* CLKSRC=32KHz, EPIT Output Disconnected, Enabled
40 * prescale 1/32, Reload from modulus register, Compare interrupt enabled, 36 * prescale 1/32, Reload from modulus register, Compare interrupt enabled,
41 * Count from load value */ 37 * Count from load value */
42 EPITCR1 = (0x3 << 24) | (1 << 19) | (32 << 4) | 38 EPITCR1 = (3 << 24) | (1 << 19) | (32 << 4) |
43 (1 << 3) | (1 << 2) | (1 << 1); 39 (1 << 3) | (1 << 2) | (1 << 1);
44#ifndef BOOTLOADER
45 EPITLR1 = interval_in_ms;
46 EPITCMPR1 = 0; /* Event when counter reaches 0 */
47 avic_enable_int(EPIT1, IRQ, EPIT1_HANDLER);
48#else
49 (void)interval_in_ms;
50#endif
51 EPITSR1 = 1; /* Clear any pending interrupt after
52 enabling the vector */
53 40
41 EPITLR1 = interval_in_ms; /* Count down from interval */
42 EPITCMPR1 = 0; /* Event when counter reaches 0 */
43 EPITSR1 = 1; /* Clear any pending interrupt */
44 avic_enable_int(EPIT1, IRQ, 7, EPIT1_HANDLER);
54 EPITCR1 |= (1 << 0); /* Enable the counter */ 45 EPITCR1 |= (1 << 0); /* Enable the counter */
55} 46}
47
48#ifdef BOOTLOADER
49void tick_stop(void)
50{
51 avic_disable_int(EPIT1); /* Disable insterrupt */
52 EPITCR1 &= ~((1 << 2) | (1 << 0)); /* Disable counter */
53 CLKCTL_CGR0 &= ~(3 << 6); /* EPIT1 module clock OFF */
54}
55#endif