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Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c')
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c19
1 files changed, 15 insertions, 4 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c b/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c
index aaa4bde0eb..f0f578b03e 100644
--- a/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c
@@ -19,6 +19,9 @@
19#include "config.h" 19#include "config.h"
20#include "system.h" 20#include "system.h"
21#include "avic-imx31.h" 21#include "avic-imx31.h"
22#include "spi-imx31.h"
23#include "mc13783.h"
24#include "clkctl-imx31.h"
22#include "kernel.h" 25#include "kernel.h"
23#include "thread.h" 26#include "thread.h"
24 27
@@ -42,10 +45,11 @@ static __attribute__((interrupt("IRQ"))) void EPIT1_HANDLER(void)
42 45
43void tick_start(unsigned int interval_in_ms) 46void tick_start(unsigned int interval_in_ms)
44{ 47{
45 CLKCTL_CGR0 |= CGR0_EPIT1(CG_ON_ALL); /* EPIT1 module clock ON - 48 imx31_clkctl_module_clock_gating(CG_EPIT1, CGM_ON_ALL); /* EPIT1 module
46 before writing regs! */ 49 clock ON - before writing
50 regs! */
47 EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable the counter */ 51 EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable the counter */
48 CLKCTL_WIMR0 &= ~(1 << 23); /* Clear wakeup mask */ 52 CLKCTL_WIMR0 &= ~WIM_IPI_INT_EPIT1; /* Clear wakeup mask */
49 53
50 /* mcu_main_clk = 528MHz = 27MHz * 2 * ((9 + 7/9) / 1) 54 /* mcu_main_clk = 528MHz = 27MHz * 2 * ((9 + 7/9) / 1)
51 * CLKSRC = ipg_clk = 528MHz / 4 / 2 = 66MHz, 55 * CLKSRC = ipg_clk = 528MHz / 4 / 2 = 66MHz,
@@ -66,11 +70,18 @@ void tick_start(unsigned int interval_in_ms)
66 EPITCR1 |= EPITCR_EN; /* Enable the counter */ 70 EPITCR1 |= EPITCR_EN; /* Enable the counter */
67} 71}
68 72
73void kernel_device_init(void)
74{
75 spi_init();
76 mc13783_init();
77}
78
69#ifdef BOOTLOADER 79#ifdef BOOTLOADER
70void tick_stop(void) 80void tick_stop(void)
71{ 81{
72 avic_disable_int(EPIT1); /* Disable insterrupt */ 82 avic_disable_int(EPIT1); /* Disable insterrupt */
73 EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable counter */ 83 EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable counter */
74 CLKCTL_CGR0 &= ~CGR0_EPIT1(CG_MASK); /* EPIT1 module clock OFF */ 84 EPITSR1 = EPITSR_OCIF; /* Clear pending */
85 imx31_clkctl_module_clock_gating(CG_EPIT1, CGM_OFF); /* Turn off module clock */
75} 86}
76#endif 87#endif