1 files changed, 40 insertions, 0 deletions

diff --git a/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c b/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c
index a01fab07d0..2dc6e817de 100644
--- a/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c
@@ -43,3 +43,43 @@ void imx31_clkctl_module_clock_gating(enum IMX31_CG_LIST cg,
 
     restore_interrupt(oldlevel);
 }
+
+/* Get the PLL reference clock frequency in HZ */
+unsigned int imx31_clkctl_get_pll_ref_clk(void)
+{
+    if ((CLKCTL_CCMR & (3 << 1)) == (1 << 1))
+        return CONFIG_CLK32_FREQ * 1024;
+    else
+        return CONFIG_HCLK_FREQ;
+}
+
+/* Return PLL frequency in HZ */
+unsigned int imx31_clkctl_get_pll(enum IMX31_PLLS pll)
+{
+    uint32_t infreq = imx31_clkctl_get_pll_ref_clk();
+    uint32_t reg = (&CLKCTL_MPCTL)[pll];
+    uint32_t mfn = reg & 0x3ff;
+    uint32_t pd  = ((reg >> 26) & 0xf) + 1;
+    uint64_t mfd = ((reg >> 16) & 0x3ff) + 1;
+    uint32_t mfi = (reg >> 10) & 0xf;
+
+    mfi = mfi <= 5 ? 5 : mfi;
+
+    return 2*infreq*(mfi * mfd + mfn) / (mfd * pd);
+}
+
+unsigned int imx31_clkctl_get_ipg_clk(void)
+{
+    unsigned int pll = imx31_clkctl_get_pll((CLKCTL_PMCR0 & 0xC0000000) == 0 ?
+                               PLL_SERIAL : PLL_MCU);
+    uint32_t reg = CLKCTL_PDR0;
+    unsigned int max_pdf = ((reg >> 3) & 0x7) + 1;
+    unsigned int ipg_pdf = ((reg >> 6) & 0x3) + 1;
+
+    return pll / (max_pdf * ipg_pdf);
+}
+
+unsigned int imx31_clkctl_get_ata_clk(void)
+{
+    return imx31_clkctl_get_ipg_clk();
+}