diff options
Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/ata-imx31.c')
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/ata-imx31.c | 685 |
1 files changed, 0 insertions, 685 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c b/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c deleted file mode 100644 index 5ce7ad0a03..0000000000 --- a/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c +++ /dev/null | |||
@@ -1,685 +0,0 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2007 by Will Robertson | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #include "config.h" | ||
22 | #include "cpu.h" | ||
23 | #include "kernel.h" | ||
24 | #include "thread.h" | ||
25 | #include "system.h" | ||
26 | #include "power.h" | ||
27 | #include "panic.h" | ||
28 | #include "ata.h" | ||
29 | #include "ata-target.h" | ||
30 | #include "ccm-imx31.h" | ||
31 | #ifdef HAVE_ATA_DMA | ||
32 | #include "sdma-imx31.h" | ||
33 | #include "mmu-imx31.h" | ||
34 | #endif | ||
35 | |||
36 | /* PIO modes timing info */ | ||
37 | static const struct ata_pio_timings | ||
38 | { | ||
39 | uint16_t time_2w; /* t2 during write */ | ||
40 | uint16_t time_2r; /* t2 during read */ | ||
41 | uint8_t time_ax; /* tA */ | ||
42 | uint8_t time_1; /* t1 */ | ||
43 | uint8_t time_4; /* t4 */ | ||
44 | uint8_t time_9; /* t9 */ | ||
45 | } pio_timings[5] = | ||
46 | { | ||
47 | [0] = /* PIO mode 0 */ | ||
48 | { | ||
49 | .time_1 = 70, | ||
50 | .time_2w = 290, | ||
51 | .time_2r = 290, | ||
52 | .time_ax = 35, | ||
53 | .time_4 = 30, | ||
54 | .time_9 = 20 | ||
55 | }, | ||
56 | [1] = /* PIO mode 1 */ | ||
57 | { | ||
58 | .time_1 = 50, | ||
59 | .time_2w = 290, | ||
60 | .time_2r = 290, | ||
61 | .time_ax = 35, | ||
62 | .time_4 = 20, | ||
63 | .time_9 = 15 | ||
64 | }, | ||
65 | [2] = /* PIO mode 2 */ | ||
66 | { | ||
67 | .time_1 = 30, | ||
68 | .time_2w = 290, | ||
69 | .time_2r = 290, | ||
70 | .time_ax = 35, | ||
71 | .time_4 = 15, | ||
72 | .time_9 = 10 | ||
73 | }, | ||
74 | [3] = /* PIO mode 3 */ | ||
75 | { | ||
76 | .time_1 = 30, | ||
77 | .time_2w = 80, | ||
78 | .time_2r = 80, | ||
79 | .time_ax = 35, | ||
80 | .time_4 = 10, | ||
81 | .time_9 = 10 | ||
82 | }, | ||
83 | [4] = /* PIO mode 4 */ | ||
84 | { | ||
85 | .time_1 = 25, | ||
86 | .time_2w = 70, | ||
87 | .time_2r = 70, | ||
88 | .time_ax = 35, | ||
89 | .time_4 = 10, | ||
90 | .time_9 = 10 | ||
91 | } | ||
92 | }; | ||
93 | |||
94 | /* Track first init */ | ||
95 | static bool initialized = false; | ||
96 | |||
97 | #ifdef HAVE_ATA_DMA | ||
98 | /* One DMA channel for reads, the other for writes othewise one channel would | ||
99 | * have to be reinitialized every time the direction changed. (Different | ||
100 | * SDMA scripts are used for reading or writing) */ | ||
101 | #define ATA_DMA_CH_NUM_RD 3 | ||
102 | #define ATA_DMA_CH_NUM_WR 4 | ||
103 | /* Use default priority for these channels (1) - ATA isn't realtime urgent. */ | ||
104 | /* Maximum DMA size per buffer descriptor (32-byte aligned) */ | ||
105 | #define ATA_MAX_BD_SIZE (65534 & ~31) /* 65504 */ | ||
106 | |||
107 | /* Number of buffer descriptors required for a maximum sector count trasfer. | ||
108 | * NOTE: Assumes LBA28 and 512-byte sectors! */ | ||
109 | #define ATA_BASE_BD_COUNT ((256*512 + (ATA_MAX_BD_SIZE-1)) / ATA_MAX_BD_SIZE) | ||
110 | #define ATA_BD_COUNT (ATA_BASE_BD_COUNT + 2) | ||
111 | |||
112 | static const struct ata_mdma_timings | ||
113 | { | ||
114 | uint8_t time_m; /* tM */ | ||
115 | uint8_t time_jn; /* tH */ | ||
116 | uint8_t time_d; /* tD */ | ||
117 | uint8_t time_k; /* tKW */ | ||
118 | } mdma_timings[] = | ||
119 | { | ||
120 | [0] = /* MDMA mode 0 */ | ||
121 | { | ||
122 | .time_m = 50, | ||
123 | .time_jn = 20, | ||
124 | .time_d = 215, | ||
125 | .time_k = 215 | ||
126 | }, | ||
127 | [1] = /* MDMA mode 1 */ | ||
128 | { | ||
129 | .time_m = 30, | ||
130 | .time_jn = 15, | ||
131 | .time_d = 80, | ||
132 | .time_k = 50 | ||
133 | }, | ||
134 | [2] = /* MDMA mode 2 */ | ||
135 | { | ||
136 | .time_m = 25, | ||
137 | .time_jn = 10, | ||
138 | .time_d = 70, | ||
139 | .time_k = 25 | ||
140 | } | ||
141 | }; | ||
142 | |||
143 | static const struct ata_udma_timings | ||
144 | { | ||
145 | uint8_t time_ack; /* tACK */ | ||
146 | uint8_t time_env; /* tENV */ | ||
147 | uint8_t time_rpx; /* tRP */ | ||
148 | uint8_t time_zah; /* tZAH */ | ||
149 | uint8_t time_mlix; /* tMLI */ | ||
150 | uint8_t time_dvh; /* tDVH */ | ||
151 | uint8_t time_dzfs; /* tDVS+tDVH? */ | ||
152 | uint8_t time_dvs; /* tDVS */ | ||
153 | uint8_t time_cvh; /* ?? */ | ||
154 | uint8_t time_ss; /* tSS */ | ||
155 | uint8_t time_cyc; /* tCYC */ | ||
156 | } udma_timings[] = | ||
157 | { | ||
158 | [0] = /* UDMA mode 0 */ | ||
159 | { | ||
160 | .time_ack = 20, | ||
161 | .time_env = 20, | ||
162 | .time_rpx = 160, | ||
163 | .time_zah = 20, | ||
164 | .time_mlix = 20, | ||
165 | .time_dvh = 6, | ||
166 | .time_dzfs = 80, | ||
167 | .time_dvs = 70, | ||
168 | .time_cvh = 6, | ||
169 | .time_ss = 50, | ||
170 | .time_cyc = 114 | ||
171 | }, | ||
172 | [1] = /* UDMA mode 1 */ | ||
173 | { | ||
174 | .time_ack = 20, | ||
175 | .time_env = 20, | ||
176 | .time_rpx = 125, | ||
177 | .time_zah = 20, | ||
178 | .time_mlix = 20, | ||
179 | .time_dvh = 6, | ||
180 | .time_dzfs = 63, | ||
181 | .time_dvs = 48, | ||
182 | .time_cvh = 6, | ||
183 | .time_ss = 50, | ||
184 | .time_cyc = 75 | ||
185 | }, | ||
186 | [2] = /* UDMA mode 2 */ | ||
187 | { | ||
188 | .time_ack = 20, | ||
189 | .time_env = 20, | ||
190 | .time_rpx = 100, | ||
191 | .time_zah = 20, | ||
192 | .time_mlix = 20, | ||
193 | .time_dvh = 6, | ||
194 | .time_dzfs = 47, | ||
195 | .time_dvs = 34, | ||
196 | .time_cvh = 6, | ||
197 | .time_ss = 50, | ||
198 | .time_cyc = 55 | ||
199 | }, | ||
200 | [3] = /* UDMA mode 3 */ | ||
201 | { | ||
202 | .time_ack = 20, | ||
203 | .time_env = 20, | ||
204 | .time_rpx = 100, | ||
205 | .time_zah = 20, | ||
206 | .time_mlix = 20, | ||
207 | .time_dvh = 6, | ||
208 | .time_dzfs = 35, | ||
209 | .time_dvs = 20, | ||
210 | .time_cvh = 6, | ||
211 | .time_ss = 50, | ||
212 | .time_cyc = 39 | ||
213 | }, | ||
214 | [4] = /* UDMA mode 4 */ | ||
215 | { | ||
216 | .time_ack = 20, | ||
217 | .time_env = 20, | ||
218 | .time_rpx = 100, | ||
219 | .time_zah = 20, | ||
220 | .time_mlix = 20, | ||
221 | .time_dvh = 6, | ||
222 | .time_dzfs = 25, | ||
223 | .time_dvs = 7, | ||
224 | .time_cvh = 6, | ||
225 | .time_ss = 50, | ||
226 | .time_cyc = 25 | ||
227 | }, | ||
228 | #if 0 | ||
229 | [5] = /* UDMA mode 5 (bus clock 80MHz or higher only) */ | ||
230 | { | ||
231 | .time_ack = 20, | ||
232 | .time_env = 20, | ||
233 | .time_rpx = 85, | ||
234 | .time_zah = 20, | ||
235 | .time_mlix = 20, | ||
236 | .time_dvh = 6, | ||
237 | .time_dzfs = 40, | ||
238 | .time_dvs = 5, | ||
239 | .time_cvh = 10, | ||
240 | .time_ss = 50, | ||
241 | .time_cyc = 17 | ||
242 | } | ||
243 | #endif | ||
244 | }; | ||
245 | |||
246 | /** Threading **/ | ||
247 | /* Signal to tell thread when DMA is done */ | ||
248 | static struct wakeup ata_dma_wakeup; | ||
249 | |||
250 | /** SDMA **/ | ||
251 | /* Array of buffer descriptors for large transfers and alignnment */ | ||
252 | static struct buffer_descriptor ata_bda[ATA_BD_COUNT] DEVBSS_ATTR; | ||
253 | /* ATA channel descriptors */ | ||
254 | static struct channel_descriptor ata_cd_rd DEVBSS_ATTR; /* read channel */ | ||
255 | static struct channel_descriptor ata_cd_wr DEVBSS_ATTR; /* write channel */ | ||
256 | /* DMA channel to be started for transfer */ | ||
257 | static unsigned int current_channel = 0; | ||
258 | |||
259 | /** Buffers **/ | ||
260 | /* Scatter buffer for first and last 32 bytes of a non cache-aligned transfer | ||
261 | * to cached RAM. */ | ||
262 | static uint32_t scatter_buffer[32/4*2] DEVBSS_ATTR; | ||
263 | /* Address of ends in destination buffer for unaligned reads - copied after | ||
264 | * DMA completes. */ | ||
265 | static void *sb_dst[2] = { NULL, NULL }; | ||
266 | |||
267 | /** Modes **/ | ||
268 | #define ATA_DMA_MWDMA 0x00000000 /* Using multiword DMA */ | ||
269 | #define ATA_DMA_UDMA ATA_DMA_ULTRA_SELECTED /* Using Ultra DMA */ | ||
270 | #define ATA_DMA_PIO 0x80000000 /* Using PIO */ | ||
271 | #define ATA_DMA_DISABLED 0x80000001 /* DMA init error - use PIO */ | ||
272 | static unsigned long ata_dma_selected = ATA_DMA_PIO; | ||
273 | #endif /* HAVE_ATA_DMA */ | ||
274 | |||
275 | static unsigned int get_T(void) | ||
276 | { | ||
277 | /* T = ATA clock period in nanoseconds */ | ||
278 | return 1000 * 1000 * 1000 / ccm_get_ata_clk(); | ||
279 | } | ||
280 | |||
281 | static void ata_wait_for_idle(void) | ||
282 | { | ||
283 | while (!(ATA_INTERRUPT_PENDING & ATA_CONTROLLER_IDLE)); | ||
284 | } | ||
285 | |||
286 | /* Route the INTRQ to either the MCU or SDMA depending upon whether there is | ||
287 | * a DMA transfer in progress. */ | ||
288 | static inline void ata_set_intrq(bool to_dma) | ||
289 | { | ||
290 | ATA_INTERRUPT_ENABLE = | ||
291 | (ATA_INTERRUPT_ENABLE & ~(ATA_INTRQ1 | ATA_INTRQ2)) | | ||
292 | (to_dma ? ATA_INTRQ1 : ATA_INTRQ2); | ||
293 | } | ||
294 | |||
295 | /* Setup the timing for PIO mode */ | ||
296 | void ata_set_pio_timings(int mode) | ||
297 | { | ||
298 | const struct ata_pio_timings * const timings = &pio_timings[mode]; | ||
299 | unsigned int T = get_T(); | ||
300 | |||
301 | ata_wait_for_idle(); | ||
302 | |||
303 | ATA_TIME_1 = (timings->time_1 + T) / T; | ||
304 | ATA_TIME_2W = (timings->time_2w + T) / T; | ||
305 | ATA_TIME_2R = (timings->time_2r + T) / T; | ||
306 | ATA_TIME_AX = (timings->time_ax + T) / T + 2; /* 1.5 + tAX */ | ||
307 | ATA_TIME_PIO_RDX = 1; | ||
308 | ATA_TIME_4 = (timings->time_4 + T) / T; | ||
309 | ATA_TIME_9 = (timings->time_9 + T) / T; | ||
310 | } | ||
311 | |||
312 | void ata_reset(void) | ||
313 | { | ||
314 | /* Be sure we're not busy */ | ||
315 | ata_wait_for_idle(); | ||
316 | |||
317 | ATA_INTF_CONTROL &= ~(ATA_ATA_RST | ATA_FIFO_RST); | ||
318 | sleep(HZ/100); | ||
319 | ATA_INTF_CONTROL = ATA_ATA_RST | ATA_FIFO_RST; | ||
320 | sleep(HZ/100); | ||
321 | |||
322 | ata_wait_for_idle(); | ||
323 | } | ||
324 | |||
325 | void ata_enable(bool on) | ||
326 | { | ||
327 | /* Unconditionally clock module before writing regs */ | ||
328 | ccm_module_clock_gating(CG_ATA, CGM_ON_RUN_WAIT); | ||
329 | ata_wait_for_idle(); | ||
330 | |||
331 | if (on) | ||
332 | { | ||
333 | ATA_INTF_CONTROL = ATA_ATA_RST | ATA_FIFO_RST; | ||
334 | sleep(HZ/100); | ||
335 | } | ||
336 | else | ||
337 | { | ||
338 | ATA_INTF_CONTROL &= ~(ATA_ATA_RST | ATA_FIFO_RST); | ||
339 | sleep(HZ/100); | ||
340 | |||
341 | /* Disable off - unclock ATA module */ | ||
342 | ccm_module_clock_gating(CG_ATA, CGM_OFF); | ||
343 | } | ||
344 | } | ||
345 | |||
346 | bool ata_is_coldstart(void) | ||
347 | { | ||
348 | return true; | ||
349 | } | ||
350 | |||
351 | #ifdef HAVE_ATA_DMA | ||
352 | static void ata_set_mdma_timings(unsigned int mode) | ||
353 | { | ||
354 | const struct ata_mdma_timings * const timings = &mdma_timings[mode]; | ||
355 | unsigned int T = get_T(); | ||
356 | |||
357 | ATA_TIME_M = (timings->time_m + T) / T; | ||
358 | ATA_TIME_JN = (timings->time_jn + T) / T; | ||
359 | ATA_TIME_D = (timings->time_d + T) / T; | ||
360 | ATA_TIME_K = (timings->time_k + T) / T; | ||
361 | } | ||
362 | |||
363 | static void ata_set_udma_timings(unsigned int mode) | ||
364 | { | ||
365 | const struct ata_udma_timings * const timings = &udma_timings[mode]; | ||
366 | unsigned int T = get_T(); | ||
367 | |||
368 | ATA_TIME_ACK = (timings->time_ack + T) / T; | ||
369 | ATA_TIME_ENV = (timings->time_env + T) / T; | ||
370 | ATA_TIME_RPX = (timings->time_rpx + T) / T; | ||
371 | ATA_TIME_ZAH = (timings->time_zah + T) / T; | ||
372 | ATA_TIME_MLIX = (timings->time_mlix + T) / T; | ||
373 | ATA_TIME_DVH = (timings->time_dvh + T) / T + 1; | ||
374 | ATA_TIME_DZFS = (timings->time_dzfs + T) / T; | ||
375 | ATA_TIME_DVS = (timings->time_dvs + T) / T; | ||
376 | ATA_TIME_CVH = (timings->time_cvh + T) / T; | ||
377 | ATA_TIME_SS = (timings->time_ss + T) / T; | ||
378 | ATA_TIME_CYC = (timings->time_cyc + T) / T; | ||
379 | } | ||
380 | |||
381 | void ata_dma_set_mode(unsigned char mode) | ||
382 | { | ||
383 | unsigned int modeidx = mode & 0x07; | ||
384 | unsigned int dmamode = mode & 0xf8; | ||
385 | |||
386 | ata_wait_for_idle(); | ||
387 | |||
388 | if (ata_dma_selected == ATA_DMA_DISABLED) | ||
389 | { | ||
390 | /* Configuration error - no DMA */ | ||
391 | } | ||
392 | else if (dmamode == 0x40 && modeidx <= ATA_MAX_UDMA) | ||
393 | { | ||
394 | /* Using Ultra DMA */ | ||
395 | ata_set_udma_timings(dmamode); | ||
396 | ata_dma_selected = ATA_DMA_UDMA; | ||
397 | } | ||
398 | else if (dmamode == 0x20 && modeidx <= ATA_MAX_MWDMA) | ||
399 | { | ||
400 | /* Using Multiword DMA */ | ||
401 | ata_set_mdma_timings(dmamode); | ||
402 | ata_dma_selected = ATA_DMA_MWDMA; | ||
403 | } | ||
404 | else | ||
405 | { | ||
406 | /* Don't understand this - force PIO. */ | ||
407 | ata_dma_selected = ATA_DMA_PIO; | ||
408 | } | ||
409 | } | ||
410 | |||
411 | /* Called by SDMA when transfer is complete */ | ||
412 | static void ata_dma_callback(void) | ||
413 | { | ||
414 | /* Clear FIFO if not empty - shouldn't happen */ | ||
415 | while (ATA_FIFO_FILL != 0) | ||
416 | ATA_FIFO_DATA_32; | ||
417 | |||
418 | /* Clear FIFO interrupts (the only ones that can be) */ | ||
419 | ATA_INTERRUPT_CLEAR = ATA_INTERRUPT_PENDING; | ||
420 | |||
421 | ata_set_intrq(false); /* Return INTRQ to MCU */ | ||
422 | wakeup_signal(&ata_dma_wakeup); /* Signal waiting thread */ | ||
423 | } | ||
424 | |||
425 | bool ata_dma_setup(void *addr, unsigned long bytes, bool write) | ||
426 | { | ||
427 | struct buffer_descriptor *bd_p; | ||
428 | unsigned char *buf; | ||
429 | |||
430 | if (UNLIKELY(bytes > ATA_BASE_BD_COUNT*ATA_MAX_BD_SIZE || | ||
431 | (ata_dma_selected & ATA_DMA_PIO))) | ||
432 | { | ||
433 | /* Too much? Implies BD count should be reevaluated since this | ||
434 | * shouldn't be reached based upon size. Otherwise we simply didn't | ||
435 | * understand the DMA mode setup. Force PIO in both cases. */ | ||
436 | ATA_INTF_CONTROL = ATA_FIFO_RST | ATA_ATA_RST; | ||
437 | return false; | ||
438 | } | ||
439 | |||
440 | bd_p = &ata_bda[0]; | ||
441 | buf = (unsigned char *)addr_virt_to_phys((unsigned long)addr); | ||
442 | sb_dst[0] = NULL; /* Assume not needed */ | ||
443 | |||
444 | if (write) | ||
445 | { | ||
446 | /* No cache alignment concerns */ | ||
447 | current_channel = ATA_DMA_CH_NUM_WR; | ||
448 | |||
449 | if (LIKELY(buf != addr)) | ||
450 | { | ||
451 | /* addr is virtual */ | ||
452 | clean_dcache_range(addr, bytes); | ||
453 | } | ||
454 | |||
455 | /* Setup ATA controller for DMA transmit */ | ||
456 | ATA_INTF_CONTROL = ATA_FIFO_RST | ATA_ATA_RST | ATA_FIFO_TX_EN | | ||
457 | ATA_DMA_PENDING | ata_dma_selected | ATA_DMA_WRITE; | ||
458 | ATA_FIFO_ALARM = SDMA_ATA_WML / 2; | ||
459 | } | ||
460 | else | ||
461 | { | ||
462 | current_channel = ATA_DMA_CH_NUM_RD; | ||
463 | |||
464 | /* Setup ATA controller for DMA receive */ | ||
465 | ATA_INTF_CONTROL = ATA_FIFO_RST | ATA_ATA_RST | ATA_FIFO_RCV_EN | | ||
466 | ATA_DMA_PENDING | ata_dma_selected; | ||
467 | ATA_FIFO_ALARM = SDMA_ATA_WML / 2; | ||
468 | |||
469 | if (LIKELY(buf != addr)) | ||
470 | { | ||
471 | /* addr is virtual */ | ||
472 | dump_dcache_range(addr, bytes); | ||
473 | |||
474 | if ((unsigned long)addr & 31) | ||
475 | { | ||
476 | /* Not cache aligned, must use scatter buffers for first and | ||
477 | * last 32 bytes. */ | ||
478 | unsigned char *bufstart = buf; | ||
479 | |||
480 | sb_dst[0] = addr; | ||
481 | bd_p->buf_addr = scatter_buffer; | ||
482 | bd_p->mode.count = 32; | ||
483 | bd_p->mode.status = BD_DONE | BD_CONT; | ||
484 | |||
485 | buf += 32; | ||
486 | bytes -= 32; | ||
487 | bd_p++; | ||
488 | |||
489 | while (bytes > ATA_MAX_BD_SIZE) | ||
490 | { | ||
491 | bd_p->buf_addr = buf; | ||
492 | bd_p->mode.count = ATA_MAX_BD_SIZE; | ||
493 | bd_p->mode.status = BD_DONE | BD_CONT; | ||
494 | buf += ATA_MAX_BD_SIZE; | ||
495 | bytes -= ATA_MAX_BD_SIZE; | ||
496 | bd_p++; | ||
497 | } | ||
498 | |||
499 | if (bytes > 32) | ||
500 | { | ||
501 | unsigned long size = bytes - 32; | ||
502 | bd_p->buf_addr = buf; | ||
503 | bd_p->mode.count = size; | ||
504 | bd_p->mode.status = BD_DONE | BD_CONT; | ||
505 | buf += size; | ||
506 | bd_p++; | ||
507 | } | ||
508 | |||
509 | /* There will be exactly 32 bytes left */ | ||
510 | |||
511 | /* Final buffer - wrap to base bd, interrupt */ | ||
512 | sb_dst[1] = addr + (buf - bufstart); | ||
513 | bd_p->buf_addr = &scatter_buffer[32/4]; | ||
514 | bd_p->mode.count = 32; | ||
515 | bd_p->mode.status = BD_DONE | BD_WRAP | BD_INTR; | ||
516 | |||
517 | return true; | ||
518 | } | ||
519 | } | ||
520 | } | ||
521 | |||
522 | /* Setup buffer descriptors for both cache-aligned reads and all write | ||
523 | * operations. */ | ||
524 | while (bytes > ATA_MAX_BD_SIZE) | ||
525 | { | ||
526 | bd_p->buf_addr = buf; | ||
527 | bd_p->mode.count = ATA_MAX_BD_SIZE; | ||
528 | bd_p->mode.status = BD_DONE | BD_CONT; | ||
529 | buf += ATA_MAX_BD_SIZE; | ||
530 | bytes -= ATA_MAX_BD_SIZE; | ||
531 | bd_p++; | ||
532 | } | ||
533 | |||
534 | /* Final buffer - wrap to base bd, interrupt */ | ||
535 | bd_p->buf_addr = buf; | ||
536 | bd_p->mode.count = bytes; | ||
537 | bd_p->mode.status = BD_DONE | BD_WRAP | BD_INTR; | ||
538 | |||
539 | return true; | ||
540 | } | ||
541 | |||
542 | bool ata_dma_finish(void) | ||
543 | { | ||
544 | unsigned int channel = current_channel; | ||
545 | long timeout = current_tick + HZ*10; | ||
546 | |||
547 | current_channel = 0; | ||
548 | |||
549 | ata_set_intrq(true); /* Give INTRQ to DMA */ | ||
550 | sdma_channel_run(channel); /* Kick the channel to wait for events */ | ||
551 | |||
552 | while (1) | ||
553 | { | ||
554 | int oldirq; | ||
555 | |||
556 | if (LIKELY(wakeup_wait(&ata_dma_wakeup, HZ/2) == OBJ_WAIT_SUCCEEDED)) | ||
557 | break; | ||
558 | |||
559 | ata_keep_active(); | ||
560 | |||
561 | if (TIME_BEFORE(current_tick, timeout)) | ||
562 | continue; | ||
563 | |||
564 | /* Epic fail - timed out - maybe. */ | ||
565 | oldirq = disable_irq_save(); | ||
566 | ata_set_intrq(false); /* Strip INTRQ from DMA */ | ||
567 | sdma_channel_stop(channel); /* Stop DMA */ | ||
568 | restore_irq(oldirq); | ||
569 | |||
570 | if (wakeup_wait(&ata_dma_wakeup, TIMEOUT_NOBLOCK) == OBJ_WAIT_SUCCEEDED) | ||
571 | break; /* DMA really did finish after timeout */ | ||
572 | |||
573 | sdma_channel_reset(channel); /* Reset everything + clear error */ | ||
574 | return false; | ||
575 | } | ||
576 | |||
577 | if (sdma_channel_is_error(channel)) | ||
578 | { | ||
579 | /* Channel error in one or more descriptors */ | ||
580 | sdma_channel_reset(channel); /* Reset everything + clear error */ | ||
581 | return false; | ||
582 | } | ||
583 | |||
584 | if (sb_dst[0] != NULL) | ||
585 | { | ||
586 | /* NOTE: This requires that unaligned access support be enabled! */ | ||
587 | register void *sbs = scatter_buffer; | ||
588 | register void *sbd0 = sb_dst[0]; | ||
589 | register void *sbd1 = sb_dst[1]; | ||
590 | asm volatile( | ||
591 | "add r0, %1, #32 \n" /* Prefetch at DMA-direct boundaries */ | ||
592 | "mcrr p15, 2, r0, r0, c12 \n" | ||
593 | "mcrr p15, 2, %2, %2, c12 \n" | ||
594 | "ldmia %0!, { r0-r3 } \n" /* Copy the 32-bytes to destination */ | ||
595 | "str r0, [%1], #4 \n" /* stmia doesn't work unaligned */ | ||
596 | "str r1, [%1], #4 \n" | ||
597 | "str r2, [%1], #4 \n" | ||
598 | "str r3, [%1], #4 \n" | ||
599 | "ldmia %0!, { r0-r3 } \n" | ||
600 | "str r0, [%1], #4 \n" | ||
601 | "str r1, [%1], #4 \n" | ||
602 | "str r2, [%1], #4 \n" | ||
603 | "str r3, [%1] \n" | ||
604 | "ldmia %0!, { r0-r3 } \n" /* Copy the 32-bytes to destination */ | ||
605 | "str r0, [%2], #4 \n" /* stmia doesn't work unaligned */ | ||
606 | "str r1, [%2], #4 \n" | ||
607 | "str r2, [%2], #4 \n" | ||
608 | "str r3, [%2], #4 \n" | ||
609 | "ldmia %0!, { r0-r3 } \n" | ||
610 | "str r0, [%2], #4 \n" | ||
611 | "str r1, [%2], #4 \n" | ||
612 | "str r2, [%2], #4 \n" | ||
613 | "str r3, [%2] \n" | ||
614 | : "+r"(sbs), "+r"(sbd0), "+r"(sbd1) | ||
615 | : | ||
616 | : "r0", "r1", "r2", "r3"); | ||
617 | } | ||
618 | |||
619 | return true; | ||
620 | } | ||
621 | #endif /* HAVE_ATA_DMA */ | ||
622 | |||
623 | void ata_device_init(void) | ||
624 | { | ||
625 | /* Make sure we're not in reset mode */ | ||
626 | ata_enable(true); | ||
627 | |||
628 | if (!initialized) | ||
629 | { | ||
630 | ATA_INTERRUPT_ENABLE = 0; | ||
631 | ATA_INTERRUPT_CLEAR = ATA_INTERRUPT_PENDING; | ||
632 | } | ||
633 | |||
634 | ata_set_intrq(false); | ||
635 | |||
636 | if (initialized) | ||
637 | return; | ||
638 | |||
639 | /* All modes use same tOFF/tON */ | ||
640 | ATA_TIME_OFF = 3; | ||
641 | ATA_TIME_ON = 3; | ||
642 | |||
643 | /* Setup mode 0 for all by default | ||
644 | * Mode may be switched later once identify info is ready in which | ||
645 | * case the main driver calls back */ | ||
646 | ata_set_pio_timings(0); | ||
647 | |||
648 | #ifdef HAVE_ATA_DMA | ||
649 | ata_set_mdma_timings(0); | ||
650 | ata_set_udma_timings(0); | ||
651 | |||
652 | ata_dma_selected = ATA_DMA_PIO; | ||
653 | |||
654 | /* Called for first time at startup */ | ||
655 | wakeup_init(&ata_dma_wakeup); | ||
656 | |||
657 | /* Read/write channels share buffer descriptors */ | ||
658 | ata_cd_rd.bd_count = ATA_BD_COUNT; | ||
659 | ata_cd_rd.callback = ata_dma_callback; | ||
660 | ata_cd_rd.shp_addr = SDMA_PER_ADDR_ATA_RX; | ||
661 | ata_cd_rd.wml = SDMA_ATA_WML; | ||
662 | ata_cd_rd.per_type = SDMA_PER_ATA; | ||
663 | ata_cd_rd.tran_type = SDMA_TRAN_PER_2_EMI; | ||
664 | ata_cd_rd.event_id1 = SDMA_REQ_ATA_TXFER_END; | ||
665 | ata_cd_rd.event_id2 = SDMA_REQ_ATA_RX; | ||
666 | |||
667 | ata_cd_wr.bd_count = ATA_BD_COUNT; | ||
668 | ata_cd_wr.callback = ata_dma_callback; | ||
669 | ata_cd_wr.shp_addr = SDMA_PER_ADDR_ATA_TX; | ||
670 | ata_cd_wr.wml = SDMA_ATA_WML; | ||
671 | ata_cd_wr.per_type = SDMA_PER_ATA; | ||
672 | ata_cd_wr.tran_type = SDMA_TRAN_EMI_2_PER; | ||
673 | ata_cd_wr.event_id1 = SDMA_REQ_ATA_TXFER_END; | ||
674 | ata_cd_wr.event_id2 = SDMA_REQ_ATA_TX; | ||
675 | |||
676 | if (!sdma_channel_init(ATA_DMA_CH_NUM_RD, &ata_cd_rd, ata_bda) || | ||
677 | !sdma_channel_init(ATA_DMA_CH_NUM_WR, &ata_cd_wr, ata_bda)) | ||
678 | { | ||
679 | /* Channel init error - disable DMA forever */ | ||
680 | ata_dma_selected = ATA_DMA_DISABLED; | ||
681 | } | ||
682 | #endif /* HAVE_ATA_DMA */ | ||
683 | |||
684 | initialized = true; | ||
685 | } | ||