1 files changed, 125 insertions, 111 deletions

diff --git a/firmware/target/arm/imx31/crt0.S b/firmware/target/arm/imx31/crt0.S
index 9d50888536..4e79cd1352 100644
--- a/firmware/target/arm/imx31/crt0.S
+++ b/firmware/target/arm/imx31/crt0.S
@@ -23,9 +23,16 @@
 
     .global    start
 start:
-    b          newstart
-    .space 4*12 /* Space for low vectors */
-
+    /* Exception vectors */
+    b       newstart
+    b       undef_instr_handler
+    b       software_int_handler
+    b       prefetch_abort_handler
+    b       data_abort_handler
+    b       reserved_handler
+    b       irq_handler
+    b       fiq_handler
+    .balign 0x40, 0x6B
 
 /* Arm bootloader and startup code based on startup.s from the iPodLinux loader
  *
@@ -34,28 +41,41 @@ start:
  *
  */
 
+/* Initially this code is running at VA 0x8a000000 (PA 0x82000000).
+ * The mapping stub is copied to IRAM (0x1fffc000) and jumps to the final
+ * VA remapping starting at 0x01f00000 because the 1MB section containing
+ * the framebuffer at PA 0x81000000 is skipped in the remapping giving 63MB
+ * of contiguous RAM for the firmware. The TTB is placed at the end of said
+ * section.
+ *
+ * For now this will be done in bootloader, especially if usb will be needed
+ * within the bootloader to load the main firmware file. Interrupts will be
+ * needed for this (whether they be swi or irq).
+ */
 newstart:
     msr     cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
 
 #ifdef BOOTLOADER
-    ldr     r2, =remap_start
-    ldr     r3, =remap_end
+    adr     r2, remap_start    /* Load PC-relative labels */
+    adr     r3, remap_end
     ldr     r5, =TTB_BASE_ADDR /* TTB pointer */
     ldr     r6, =IRAM_BASE_ADDR
     mov     r1, r6
 
-1:    
+1:  /* Copy remapping stub to IRAM */
     cmp     r3, r2
     ldrhi   r4, [r2], #4
     strhi   r4, [r1], #4
     bhi     1b
 
     mov     pc, r6
-    
+
+    /* Remapping stub. No absolute addresses may be used until after the
+     * remapping is complete. */
 remap_start:
     mrc     p15, 0, r3, c1, c0, 0  /* perform writeback if D cache is enabled */
-    tst     r3, #(1 <<  2)
-    tsteq   r3, #(1 << 12)
+    tst     r3, #(1 <<  2)         /* dcache? */
+    tsteq   r3, #(1 << 12)         /* or icache? */
     mcrne   p15, 0, r0, c7, c10, 0 /* clean dcache */
     mov     r0, #0
     mcrne   p15, 0, r0, c7, c7, 0  /* invalidate I cache and D cache */
@@ -77,9 +97,9 @@ remap_start:
     str     r1, [r0, #L2_CACHE_CTL_REG]
 
     /* Disble L1 caches and memory manager */
-    bic     r3, r3, #(1 <<  1)
-    bic     r3, r3, #(1 <<  2)
-    bic     r3, r3, #(1 << 12)
+    bic     r3, r3, #(1 << 12)    /* L1 I-cache disabled */
+    bic     r3, r3, #((1 << 2) |  /* L1 D-cache disabled */ \
+                      (1 << 0))   /* MMU disabled */
     mcr     p15, 0, r3, c1, c0, 0
     
     /*
@@ -96,92 +116,97 @@ remap_start:
     /* Invalidate L2 */
     mov     r1, #0x000000FF
     str     r1, [r0, #L2_CACHE_INV_WAY_REG]
-L2_loop:
+1:
     /* Poll Invalidate By Way register */
-    ldr     r2, [r0, #L2_CACHE_INV_WAY_REG]
-    cmp     r2, #0
-    bne     L2_loop
+    ldr     r1, [r0, #L2_CACHE_INV_WAY_REG]
+    cmp     r1, #0
+    bne     1b
 
     /*** End of L2 operations ***/
 
-    /*remap memory as well as exception vectors*/
-    /*for now this will be done in bootloader, especially
-      if usb will be needed within the bootloader to load the 
-      main firmware file. Interrupts will be needed for this
-      (whether they be swi or irq)*/
-
     /* TTB Initialisation */
-    mov     r3, r5
-    add     r2, r3, #TTB_SIZE
+    mov     r2, r5
+    add     r3, r5, #TTB_SIZE
     mov     r1, #0
-ttbloop:
-    str     r1, [r3], #4
-    cmp     r3, r2
-    bne     ttbloop
+1:
+    str     r1, [r2], #4
+    cmp     r2, r3
+    blo     1b
 
     /* Set TTB base address */
-    mov     r3, r5
-    mcr     p15, 0, r3, c2, c0, 0
+    mcr     p15, 0, r5, c2, c0, 0
+
     /* Set all domains to manager status */
-    mvn     r3, #0
-    mcr     p15, 0, r3, c3, c0, 0
+    mvn     r0, #0
+    mcr     p15, 0, r0, c3, c0, 0
 
     /* Set page tables */
 
     /* Map each memory loc to itself, no cache */
-    mov     r1, #0 /* Physical address */
-    mov     r3, r5
-    add     r4, r3, #TTB_SIZE                       /* End position */
-maploop1:
-    mov     r2, r1
-    orr     r2, r2, #(1<<10)    /* superuser - r/w, user - no access */
-    //orr   r2, r2, #(0<<5)     /* domain 0th */
-    orr     r2, r2, #(1<<4)     /* should be "1" */
-    orr     r2, r2, #(1<<1)     /* Section signature */
-    str     r2, [r3], #4
-    add     r1, r1, #(1<<20)
-    cmp     r3, r4
-    bne     maploop1
+                                   /* Physical address = 0x0 */
+    mov     r1,      #(1 << 10)    /* superuser - r/w, user - no access */
+    orr     r1, r1, #((0 <<  5)  | /* domain 0th */ \
+                      (1 <<  4)  | /* should be "1" */ \
+                      (1 <<  1))   /* Section signature */
+    mov     r2, r5
+    add     r3, r5, #TTB_SIZE   /* End position */
+1:
+    str     r1, [r2], #4
+    add     r1, r1, #(1 << 20)  /* Next MB */
+    cmp     r2, r3
+    blo     1b
+    sub     r1, r1, #TTB_SIZE/4*(1 << 20) /* Back up */
 
     /* Map 0x80000000 -> 0x0, cached */
-    mov     r1, #0x80000000 /* Physical address */
-    mov     r3, r5          /* TTB pointer */
-    add     r4, r3, #64*4   /* End position */
-maploop2:
-    mov     r2, r1
-    orr     r2, r2, #(1<<10)    /* superuser - r/w, user - no access */
-    //orr   r2, r2, #(0<<5)     /* domain 0th */
-    orr     r2, r2, #(1<<4)     /* should be "1" */
-    orr     r2, r2, #(1<<3)     /* cache flags */
-    orr     r2, r2, #(1<<2)     /* more cache stuff */
-    orr     r2, r2, #(1<<1)     /* Section signature */
-    str     r2, [r3], #4
-    add     r1, r1, #(1<<20)
-    bic     r6, r1, #0xf0000000
-    cmp     r6, #0x00100000     /* Skip framebuffer */
-    addeq   r1, r1, #(1<<20)
-    cmp     r3, r4
-    bne     maploop2
+    mov     r2, r5               /* TTB pointer */
+    add     r3, r5, #63*4        /* End position */
+    orr     r1, r1, #0x80000000  /* Physical address */
+    orr     r1, r1, #((1 << 3) | /* cache flag */ \
+                      (1 << 2))  /* buffer flag */
+1:
+    str     r1, [r2], #4
+    add     r1, r1, #(1 << 20)
+    and     r4, r1, #0x0ff00000
+    cmp     r4, #0x00100000      /* Skip framebuffer */
+    addeq   r1, r1, #(1 << 20)
+    cmp     r2, r3
+    blo     1b
 
     /* Enable MMU */
 
     mov     r0, #0
     mcr     p15, 0, r0, c8, c7, 0 /* Invalidate TLB */
     mcr     p15, 0, r0, c7, c7, 0 /* Invalidate icache and dcache */
-#if 1
+    
+    /* Auxilliary control register */
     mrc     p15, 0, r0, c1, c0, 1
-    bic     r0, r0, #0x70
-    bic     r0, r0, #0x07    
+    bic     r0, r0, #((1 << 6) | /* Restrict cache size OFF */ \
+                      (1 << 5) | /* Enable block tranfer cache operations */ \
+                      (1 << 4) | /* Clean+Invalidate cache operation ON */ \
+                      (1 << 3))  /* Round-robin micro TLB replacement */
+    orr     r0, r0, #((1 << 2) | /* Static branch prediction ON */ \
+                      (1 << 1) | /* Dynamic branch prediction ON */ \
+                      (1 << 0))  /* Return stack enabled */
     mcr     p15, 0, r0, c1, c0, 1
-#endif
+
+    /* Control register */
     mrc     p15, 0, r0, c1, c0, 0
-    orr     r0, r0, #(1 <<  0)    /* enable mmu bit */
-    orr     r0, r0, #(1 <<  2)    /* enable dcache */
-    bic     r0, r0, #(1 << 11)    /* no program flow prediction */
-    orr     r0, r0, #(1 << 12)    /* enable icache */
-    bic     r0, r0, #(1 << 13)    /* low vectors */
-    orr     r0, r0, #(1 << 14)    /* Round-robin */
-    bic     r0, r0, #(1 << 21)    /* No low latency interrupt */
+    bic     r0, r0, #((1 << 29) | /* AF by AP disabled */ \
+                      (1 << 28) | /* TEX remap disabled */ \
+                      (1 << 24) | /* Vectored interrupt OFF */ \
+                      (1 << 23) | /* Sub AP bits enabled (compatible) */ \
+                      (1 << 22))  /* Unaligned access support disabled */
+    bic     r0, r0, #((1 << 21) | /* All performance features enabled */ \
+                      (1 << 15))  /* Loads to PC set T bit */
+    bic     r0, r0, #((1 << 13) | /* Low vectors */ \
+                      (1 << 11))  /* Program flow prediction disabled (for now) */
+    orr     r0, r0, #((1 << 14) | /* Round-robin replacement for I/D caches */ \
+                      (1 << 12) | /* L1 I-cache enabled */ \
+                      (1 <<  9) | /* ROM protection enabled */ \
+                      (1 <<  8))  /* MMU protection enabled */
+    orr     r0, r0, #((1 <<  2) | /* L1 D-cache enabled */ \
+                      (1 <<  1) | /* Strict alignment enabled */ \
+                      (1 <<  0))  /* MMU enabled */
     mcr     p15, 0, r0, c1, c0, 0
     nop
     nop
@@ -194,8 +219,8 @@ remap_end:
 
 #endif /* BOOTLOADER */
 
-#ifndef BOOTLOADER
-    /* Copy exception handler code to address 0 */
+#ifdef BOOTLOADER
+    /* Copy bootloader exception handler code to address 0 */
     ldr     r2, =_vectorsstart
     ldr     r3, =_vectorsend
     ldr     r4, =_vectorscopy
@@ -204,7 +229,7 @@ remap_end:
     ldrhi   r5, [r4], #4
     strhi   r5, [r2], #4
     bhi     1b
-
+#else
     /* Zero out IBSS */
     ldr     r2, =_iedata
     ldr     r3, =_iend
@@ -261,47 +286,41 @@ remap_end:
     msr     cpsr_c, #0xd3
     bl      main
 
-/* Exception handlers. Will be copied to address 0 after memory remapping */
-_vectorstart:
+#ifdef BOOTLOADER
+    /* Exception vectors with absolute jumps for bootloader */
     .section .vectors,"aw"
-    ldr    pc, [pc, #24]
-    ldr    pc, [pc, #24]
-    ldr    pc, [pc, #24]
-    ldr    pc, [pc, #24]
-    ldr    pc, [pc, #24]
-    ldr    pc, [pc, #24]
-    ldr    pc, [pc, #24]
-    ldr    pc, [pc, #24]
-
-    /* Exception vectors */
-    .global vectors
-vectors:
-    .word  start 
-    .word  undef_instr_handler
-    .word  software_int_handler
-    .word  prefetch_abort_handler
-    .word  data_abort_handler
-    .word  reserved_handler
-    .word  irq_handler
-    .word  fiq_handler
+    ldr     pc, [pc, #24]
+    ldr     pc, [pc, #24]
+    ldr     pc, [pc, #24]
+    ldr     pc, [pc, #24]
+    ldr     pc, [pc, #24]
+    ldr     pc, [pc, #24]
+    ldr     pc, [pc, #24]
+    ldr     pc, [pc, #24]
+    .word   newstart
+    .word   undef_instr_handler
+    .word   software_int_handler
+    .word   prefetch_abort_handler
+    .word   data_abort_handler
+    .word   reserved_handler
+    .word   irq_handler
+    .word   fiq_handler
+#endif /* BOOTLOADER */
 
     .text
-
     .global UIE
 
 /* All illegal exceptions call into UIE with exception address as first
-   parameter. This is calculated differently depending on which exception
-   we're in. Second parameter is exception number, used for a string lookup
-   in UIE.
- */
+ * parameter. This is calculated differently depending on which exception
+ * we're in. Second parameter is exception number, used for a string lookup
+ * in UIE. */
 undef_instr_handler:
     mov    r0, lr
     mov    r1, #0
     b      UIE
 
 /* We run supervisor mode most of the time, and should never see a software
-   exception being thrown. Perhaps make it illegal and call UIE?
- */
+ * exception being thrown. Perhaps make it illegal and call UIE? */
 software_int_handler:
 reserved_handler:
     movs   pc, lr
@@ -316,11 +335,6 @@ data_abort_handler:
     mov    r1, #2
     b      UIE
 
-#ifdef BOOTLOADER
-UIE:
-    b      UIE
-#endif    
-
 /* 256 words of IRQ stack */
     .space 256*4
 irq_stack: