diff options
Diffstat (limited to 'firmware/target/arm/imx31/crt0.S')
-rw-r--r-- | firmware/target/arm/imx31/crt0.S | 35 |
1 files changed, 18 insertions, 17 deletions
diff --git a/firmware/target/arm/imx31/crt0.S b/firmware/target/arm/imx31/crt0.S index 69577e4d3d..b6a49266ef 100644 --- a/firmware/target/arm/imx31/crt0.S +++ b/firmware/target/arm/imx31/crt0.S | |||
@@ -32,8 +32,9 @@ start: | |||
32 | b prefetch_abort_handler | 32 | b prefetch_abort_handler |
33 | b data_abort_handler | 33 | b data_abort_handler |
34 | b reserved_handler | 34 | b reserved_handler |
35 | /* These vectors are unused */ | ||
35 | subs pc, lr, #4 @ b irq_handler | 36 | subs pc, lr, #4 @ b irq_handler |
36 | b fiq_handler | 37 | subs pc, lr, #4 @ b fiq_handler |
37 | .balign 0x40, 0x6B | 38 | .balign 0x40, 0x6B |
38 | 39 | ||
39 | /* Arm bootloader and startup code based on startup.s from the iPodLinux loader | 40 | /* Arm bootloader and startup code based on startup.s from the iPodLinux loader |
@@ -80,7 +81,7 @@ remap_start: | |||
80 | mcrne p15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ | 81 | mcrne p15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ |
81 | mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ | 82 | mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ |
82 | mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */ | 83 | mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */ |
83 | 84 | ||
84 | mcr p15, 0, r0, c13, c0, 0 | 85 | mcr p15, 0, r0, c13, c0, 0 |
85 | mcr p15, 0, r0, c13, c0, 1 | 86 | mcr p15, 0, r0, c13, c0, 1 |
86 | 87 | ||
@@ -100,7 +101,7 @@ remap_start: | |||
100 | bic r3, r3, #((1 << 2) | /* L1 D-cache disabled */ \ | 101 | bic r3, r3, #((1 << 2) | /* L1 D-cache disabled */ \ |
101 | (1 << 0)) /* MMU disabled */ | 102 | (1 << 0)) /* MMU disabled */ |
102 | mcr p15, 0, r3, c1, c0, 0 | 103 | mcr p15, 0, r3, c1, c0, 0 |
103 | 104 | ||
104 | /* | 105 | /* |
105 | * Configure L2 Cache: | 106 | * Configure L2 Cache: |
106 | * - 128k size(16k way) | 107 | * - 128k size(16k way) |
@@ -175,7 +176,7 @@ remap_start: | |||
175 | mov r0, #0 | 176 | mov r0, #0 |
176 | mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLB */ | 177 | mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLB */ |
177 | mcr p15, 0, r0, c7, c7, 0 /* Invalidate icache and dcache */ | 178 | mcr p15, 0, r0, c7, c7, 0 /* Invalidate icache and dcache */ |
178 | 179 | ||
179 | /* Auxilliary control register */ | 180 | /* Auxilliary control register */ |
180 | mrc p15, 0, r0, c1, c0, 1 | 181 | mrc p15, 0, r0, c1, c0, 1 |
181 | bic r0, r0, #((1 << 6) | /* Restrict cache size OFF */ \ | 182 | bic r0, r0, #((1 << 6) | /* Restrict cache size OFF */ \ |
@@ -252,18 +253,18 @@ remap_end: | |||
252 | cmp r3, r2 | 253 | cmp r3, r2 |
253 | strhi r4, [r2], #4 | 254 | strhi r4, [r2], #4 |
254 | bhi 1b | 255 | bhi 1b |
255 | 256 | ||
256 | /* Set up stack for IRQ mode */ | 257 | /* Set up stack for IRQ mode */ |
257 | msr cpsr_c, #0xd2 | 258 | msr cpsr_c, #0xd2 |
258 | ldr sp, =irq_stack | 259 | ldr sp, =irq_stack |
259 | 260 | ||
260 | /* Set up stack for FIQ mode */ | 261 | /* FIQ mode is unused, thus sp_FIQ is irrelevant for it */ |
261 | msr cpsr_c, #0xd1 | ||
262 | ldr sp, =fiq_stack | ||
263 | 262 | ||
264 | /* Let svc, abort and undefined modes use irq stack */ | 263 | /* Set up stack for SVC mode */ |
265 | msr cpsr_c, #0xd3 | 264 | msr cpsr_c, #0xd3 |
266 | ldr sp, =irq_stack | 265 | ldr sp, =svc_stack |
266 | |||
267 | /* Let abort and undefined modes use irq stack */ | ||
267 | msr cpsr_c, #0xd7 | 268 | msr cpsr_c, #0xd7 |
268 | ldr sp, =irq_stack | 269 | ldr sp, =irq_stack |
269 | msr cpsr_c, #0xdb | 270 | msr cpsr_c, #0xdb |
@@ -286,7 +287,7 @@ remap_end: | |||
286 | mrc p15, 0, r3, c1, c0, 2 | 287 | mrc p15, 0, r3, c1, c0, 2 |
287 | orr r3, r3, #0xf00000 | 288 | orr r3, r3, #0xf00000 |
288 | mcr p15, 0, r3, c1, c0, 2 | 289 | mcr p15, 0, r3, c1, c0, 2 |
289 | 290 | ||
290 | /* Enable VFP */ | 291 | /* Enable VFP */ |
291 | mrc p10, 7, r3, c8, c0, 0 | 292 | mrc p10, 7, r3, c8, c0, 0 |
292 | orr r3, r3, #1<<30 | 293 | orr r3, r3, #1<<30 |
@@ -314,7 +315,7 @@ remap_end: | |||
314 | ldr pc, [pc, #24] | 315 | ldr pc, [pc, #24] |
315 | ldr pc, [pc, #24] | 316 | ldr pc, [pc, #24] |
316 | subs pc, lr, #4 @ ldr pc, [pc, #24] | 317 | subs pc, lr, #4 @ ldr pc, [pc, #24] |
317 | ldr pc, [pc, #24] | 318 | subs pc, lr, #4 @ ldr pc, [pc, #24] |
318 | .word newstart | 319 | .word newstart |
319 | .word undef_instr_handler | 320 | .word undef_instr_handler |
320 | .word software_int_handler | 321 | .word software_int_handler |
@@ -322,7 +323,7 @@ remap_end: | |||
322 | .word data_abort_handler | 323 | .word data_abort_handler |
323 | .word reserved_handler | 324 | .word reserved_handler |
324 | .word 0 @ irq_handler | 325 | .word 0 @ irq_handler |
325 | .word fiq_handler | 326 | .word 0 @ fiq_handler |
326 | #endif /* BOOTLOADER */ | 327 | #endif /* BOOTLOADER */ |
327 | 328 | ||
328 | .text | 329 | .text |
@@ -350,7 +351,7 @@ prefetch_abort_handler: | |||
350 | b UIE | 351 | b UIE |
351 | 352 | ||
352 | data_abort_handler: | 353 | data_abort_handler: |
353 | sub r0, lr, #8 | 354 | sub r0, lr, #8 |
354 | mov r1, #2 | 355 | mov r1, #2 |
355 | b UIE | 356 | b UIE |
356 | 357 | ||
@@ -360,8 +361,8 @@ data_abort_handler: | |||
360 | .space 256*4 | 361 | .space 256*4 |
361 | irq_stack: | 362 | irq_stack: |
362 | 363 | ||
363 | /* 256 words of FIQ stack */ | 364 | /* 256 words of SVC stack */ |
364 | .section .bss | 365 | .section .bss |
365 | .balign 32 | 366 | .balign 32 |
366 | .space 256*4 | 367 | .space 256*4 |
367 | fiq_stack: | 368 | svc_stack: |