diff options
Diffstat (limited to 'firmware/target/arm/imx233/regs/stmp3700/regs-digctl.h')
-rw-r--r-- | firmware/target/arm/imx233/regs/stmp3700/regs-digctl.h | 759 |
1 files changed, 759 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-digctl.h b/firmware/target/arm/imx233/regs/stmp3700/regs-digctl.h new file mode 100644 index 0000000000..69d4e7128f --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-digctl.h | |||
@@ -0,0 +1,759 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__DIGCTL__H__ | ||
24 | #define __HEADERGEN__STMP3700__DIGCTL__H__ | ||
25 | |||
26 | #define REGS_DIGCTL_BASE (0x8001c000) | ||
27 | |||
28 | #define REGS_DIGCTL_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_DIGCTL_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_DIGCTL_CTRL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x0)) | ||
36 | #define HW_DIGCTL_CTRL_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x4)) | ||
37 | #define HW_DIGCTL_CTRL_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x8)) | ||
38 | #define HW_DIGCTL_CTRL_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0xc)) | ||
39 | #define BP_DIGCTL_CTRL_TRAP_IRQ 29 | ||
40 | #define BM_DIGCTL_CTRL_TRAP_IRQ 0x20000000 | ||
41 | #define BF_DIGCTL_CTRL_TRAP_IRQ(v) (((v) << 29) & 0x20000000) | ||
42 | #define BP_DIGCTL_CTRL_DCP_BIST_CLKEN 23 | ||
43 | #define BM_DIGCTL_CTRL_DCP_BIST_CLKEN 0x800000 | ||
44 | #define BF_DIGCTL_CTRL_DCP_BIST_CLKEN(v) (((v) << 23) & 0x800000) | ||
45 | #define BP_DIGCTL_CTRL_DCP_BIST_START 22 | ||
46 | #define BM_DIGCTL_CTRL_DCP_BIST_START 0x400000 | ||
47 | #define BF_DIGCTL_CTRL_DCP_BIST_START(v) (((v) << 22) & 0x400000) | ||
48 | #define BP_DIGCTL_CTRL_ARM_BIST_CLKEN 21 | ||
49 | #define BM_DIGCTL_CTRL_ARM_BIST_CLKEN 0x200000 | ||
50 | #define BF_DIGCTL_CTRL_ARM_BIST_CLKEN(v) (((v) << 21) & 0x200000) | ||
51 | #define BP_DIGCTL_CTRL_USB_TESTMODE 20 | ||
52 | #define BM_DIGCTL_CTRL_USB_TESTMODE 0x100000 | ||
53 | #define BF_DIGCTL_CTRL_USB_TESTMODE(v) (((v) << 20) & 0x100000) | ||
54 | #define BP_DIGCTL_CTRL_ANALOG_TESTMODE 19 | ||
55 | #define BM_DIGCTL_CTRL_ANALOG_TESTMODE 0x80000 | ||
56 | #define BF_DIGCTL_CTRL_ANALOG_TESTMODE(v) (((v) << 19) & 0x80000) | ||
57 | #define BP_DIGCTL_CTRL_DIGITAL_TESTMODE 18 | ||
58 | #define BM_DIGCTL_CTRL_DIGITAL_TESTMODE 0x40000 | ||
59 | #define BF_DIGCTL_CTRL_DIGITAL_TESTMODE(v) (((v) << 18) & 0x40000) | ||
60 | #define BP_DIGCTL_CTRL_ARM_BIST_START 17 | ||
61 | #define BM_DIGCTL_CTRL_ARM_BIST_START 0x20000 | ||
62 | #define BF_DIGCTL_CTRL_ARM_BIST_START(v) (((v) << 17) & 0x20000) | ||
63 | #define BP_DIGCTL_CTRL_UART_LOOPBACK 16 | ||
64 | #define BM_DIGCTL_CTRL_UART_LOOPBACK 0x10000 | ||
65 | #define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL 0x0 | ||
66 | #define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT 0x1 | ||
67 | #define BF_DIGCTL_CTRL_UART_LOOPBACK(v) (((v) << 16) & 0x10000) | ||
68 | #define BF_DIGCTL_CTRL_UART_LOOPBACK_V(v) ((BV_DIGCTL_CTRL_UART_LOOPBACK__##v << 16) & 0x10000) | ||
69 | #define BP_DIGCTL_CTRL_SAIF_LOOPBACK 15 | ||
70 | #define BM_DIGCTL_CTRL_SAIF_LOOPBACK 0x8000 | ||
71 | #define BV_DIGCTL_CTRL_SAIF_LOOPBACK__NORMAL 0x0 | ||
72 | #define BV_DIGCTL_CTRL_SAIF_LOOPBACK__LOOPIT 0x1 | ||
73 | #define BF_DIGCTL_CTRL_SAIF_LOOPBACK(v) (((v) << 15) & 0x8000) | ||
74 | #define BF_DIGCTL_CTRL_SAIF_LOOPBACK_V(v) ((BV_DIGCTL_CTRL_SAIF_LOOPBACK__##v << 15) & 0x8000) | ||
75 | #define BP_DIGCTL_CTRL_SAIF_CLKMUX_SEL 13 | ||
76 | #define BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL 0x6000 | ||
77 | #define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__MBL_CLK_OUT 0x0 | ||
78 | #define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_OUT 0x1 | ||
79 | #define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__M_CLK_OUT_BL_CLK_IN 0x2 | ||
80 | #define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_IN 0x3 | ||
81 | #define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(v) (((v) << 13) & 0x6000) | ||
82 | #define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL_V(v) ((BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__##v << 13) & 0x6000) | ||
83 | #define BP_DIGCTL_CTRL_SAIF_CLKMST_SEL 12 | ||
84 | #define BM_DIGCTL_CTRL_SAIF_CLKMST_SEL 0x1000 | ||
85 | #define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF1_MST 0x0 | ||
86 | #define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF2_MST 0x1 | ||
87 | #define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL(v) (((v) << 12) & 0x1000) | ||
88 | #define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL_V(v) ((BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__##v << 12) & 0x1000) | ||
89 | #define BP_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL 11 | ||
90 | #define BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL 0x800 | ||
91 | #define BF_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL(v) (((v) << 11) & 0x800) | ||
92 | #define BP_DIGCTL_CTRL_USE_SERIAL_JTAG 6 | ||
93 | #define BM_DIGCTL_CTRL_USE_SERIAL_JTAG 0x40 | ||
94 | #define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__OLD_JTAG 0x0 | ||
95 | #define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__SERIAL_JTAG 0x1 | ||
96 | #define BF_DIGCTL_CTRL_USE_SERIAL_JTAG(v) (((v) << 6) & 0x40) | ||
97 | #define BF_DIGCTL_CTRL_USE_SERIAL_JTAG_V(v) ((BV_DIGCTL_CTRL_USE_SERIAL_JTAG__##v << 6) & 0x40) | ||
98 | #define BP_DIGCTL_CTRL_TRAP_IN_RANGE 5 | ||
99 | #define BM_DIGCTL_CTRL_TRAP_IN_RANGE 0x20 | ||
100 | #define BF_DIGCTL_CTRL_TRAP_IN_RANGE(v) (((v) << 5) & 0x20) | ||
101 | #define BP_DIGCTL_CTRL_TRAP_ENABLE 4 | ||
102 | #define BM_DIGCTL_CTRL_TRAP_ENABLE 0x10 | ||
103 | #define BF_DIGCTL_CTRL_TRAP_ENABLE(v) (((v) << 4) & 0x10) | ||
104 | #define BP_DIGCTL_CTRL_DEBUG_DISABLE 3 | ||
105 | #define BM_DIGCTL_CTRL_DEBUG_DISABLE 0x8 | ||
106 | #define BF_DIGCTL_CTRL_DEBUG_DISABLE(v) (((v) << 3) & 0x8) | ||
107 | #define BP_DIGCTL_CTRL_USB_CLKGATE 2 | ||
108 | #define BM_DIGCTL_CTRL_USB_CLKGATE 0x4 | ||
109 | #define BV_DIGCTL_CTRL_USB_CLKGATE__RUN 0x0 | ||
110 | #define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS 0x1 | ||
111 | #define BF_DIGCTL_CTRL_USB_CLKGATE(v) (((v) << 2) & 0x4) | ||
112 | #define BF_DIGCTL_CTRL_USB_CLKGATE_V(v) ((BV_DIGCTL_CTRL_USB_CLKGATE__##v << 2) & 0x4) | ||
113 | #define BP_DIGCTL_CTRL_JTAG_SHIELD 1 | ||
114 | #define BM_DIGCTL_CTRL_JTAG_SHIELD 0x2 | ||
115 | #define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL 0x0 | ||
116 | #define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP 0x1 | ||
117 | #define BF_DIGCTL_CTRL_JTAG_SHIELD(v) (((v) << 1) & 0x2) | ||
118 | #define BF_DIGCTL_CTRL_JTAG_SHIELD_V(v) ((BV_DIGCTL_CTRL_JTAG_SHIELD__##v << 1) & 0x2) | ||
119 | #define BP_DIGCTL_CTRL_LATCH_ENTROPY 0 | ||
120 | #define BM_DIGCTL_CTRL_LATCH_ENTROPY 0x1 | ||
121 | #define BF_DIGCTL_CTRL_LATCH_ENTROPY(v) (((v) << 0) & 0x1) | ||
122 | |||
123 | /** | ||
124 | * Register: HW_DIGCTL_STATUS | ||
125 | * Address: 0x10 | ||
126 | * SCT: no | ||
127 | */ | ||
128 | #define HW_DIGCTL_STATUS (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x10)) | ||
129 | #define BP_DIGCTL_STATUS_USB_HS_PRESENT 31 | ||
130 | #define BM_DIGCTL_STATUS_USB_HS_PRESENT 0x80000000 | ||
131 | #define BF_DIGCTL_STATUS_USB_HS_PRESENT(v) (((v) << 31) & 0x80000000) | ||
132 | #define BP_DIGCTL_STATUS_USB_OTG_PRESENT 30 | ||
133 | #define BM_DIGCTL_STATUS_USB_OTG_PRESENT 0x40000000 | ||
134 | #define BF_DIGCTL_STATUS_USB_OTG_PRESENT(v) (((v) << 30) & 0x40000000) | ||
135 | #define BP_DIGCTL_STATUS_USB_HOST_PRESENT 29 | ||
136 | #define BM_DIGCTL_STATUS_USB_HOST_PRESENT 0x20000000 | ||
137 | #define BF_DIGCTL_STATUS_USB_HOST_PRESENT(v) (((v) << 29) & 0x20000000) | ||
138 | #define BP_DIGCTL_STATUS_USB_DEVICE_PRESENT 28 | ||
139 | #define BM_DIGCTL_STATUS_USB_DEVICE_PRESENT 0x10000000 | ||
140 | #define BF_DIGCTL_STATUS_USB_DEVICE_PRESENT(v) (((v) << 28) & 0x10000000) | ||
141 | #define BP_DIGCTL_STATUS_DCP_BIST_FAIL 10 | ||
142 | #define BM_DIGCTL_STATUS_DCP_BIST_FAIL 0x400 | ||
143 | #define BF_DIGCTL_STATUS_DCP_BIST_FAIL(v) (((v) << 10) & 0x400) | ||
144 | #define BP_DIGCTL_STATUS_DCP_BIST_PASS 9 | ||
145 | #define BM_DIGCTL_STATUS_DCP_BIST_PASS 0x200 | ||
146 | #define BF_DIGCTL_STATUS_DCP_BIST_PASS(v) (((v) << 9) & 0x200) | ||
147 | #define BP_DIGCTL_STATUS_DCP_BIST_DONE 8 | ||
148 | #define BM_DIGCTL_STATUS_DCP_BIST_DONE 0x100 | ||
149 | #define BF_DIGCTL_STATUS_DCP_BIST_DONE(v) (((v) << 8) & 0x100) | ||
150 | #define BP_DIGCTL_STATUS_JTAG_IN_USE 4 | ||
151 | #define BM_DIGCTL_STATUS_JTAG_IN_USE 0x10 | ||
152 | #define BF_DIGCTL_STATUS_JTAG_IN_USE(v) (((v) << 4) & 0x10) | ||
153 | #define BP_DIGCTL_STATUS_PACKAGE_TYPE 1 | ||
154 | #define BM_DIGCTL_STATUS_PACKAGE_TYPE 0xe | ||
155 | #define BF_DIGCTL_STATUS_PACKAGE_TYPE(v) (((v) << 1) & 0xe) | ||
156 | #define BP_DIGCTL_STATUS_WRITTEN 0 | ||
157 | #define BM_DIGCTL_STATUS_WRITTEN 0x1 | ||
158 | #define BF_DIGCTL_STATUS_WRITTEN(v) (((v) << 0) & 0x1) | ||
159 | |||
160 | /** | ||
161 | * Register: HW_DIGCTL_HCLKCOUNT | ||
162 | * Address: 0x20 | ||
163 | * SCT: no | ||
164 | */ | ||
165 | #define HW_DIGCTL_HCLKCOUNT (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x20)) | ||
166 | #define BP_DIGCTL_HCLKCOUNT_COUNT 0 | ||
167 | #define BM_DIGCTL_HCLKCOUNT_COUNT 0xffffffff | ||
168 | #define BF_DIGCTL_HCLKCOUNT_COUNT(v) (((v) << 0) & 0xffffffff) | ||
169 | |||
170 | /** | ||
171 | * Register: HW_DIGCTL_RAMCTRL | ||
172 | * Address: 0x30 | ||
173 | * SCT: yes | ||
174 | */ | ||
175 | #define HW_DIGCTL_RAMCTRL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x0)) | ||
176 | #define HW_DIGCTL_RAMCTRL_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x4)) | ||
177 | #define HW_DIGCTL_RAMCTRL_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x8)) | ||
178 | #define HW_DIGCTL_RAMCTRL_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0xc)) | ||
179 | #define BP_DIGCTL_RAMCTRL_SPEED_SELECT 8 | ||
180 | #define BM_DIGCTL_RAMCTRL_SPEED_SELECT 0xf00 | ||
181 | #define BF_DIGCTL_RAMCTRL_SPEED_SELECT(v) (((v) << 8) & 0xf00) | ||
182 | #define BP_DIGCTL_RAMCTRL_RAM_REPAIR_EN 0 | ||
183 | #define BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN 0x1 | ||
184 | #define BF_DIGCTL_RAMCTRL_RAM_REPAIR_EN(v) (((v) << 0) & 0x1) | ||
185 | |||
186 | /** | ||
187 | * Register: HW_DIGCTL_RAMREPAIR | ||
188 | * Address: 0x40 | ||
189 | * SCT: yes | ||
190 | */ | ||
191 | #define HW_DIGCTL_RAMREPAIR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x0)) | ||
192 | #define HW_DIGCTL_RAMREPAIR_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x4)) | ||
193 | #define HW_DIGCTL_RAMREPAIR_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x8)) | ||
194 | #define HW_DIGCTL_RAMREPAIR_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0xc)) | ||
195 | #define BP_DIGCTL_RAMREPAIR_ADDR 0 | ||
196 | #define BM_DIGCTL_RAMREPAIR_ADDR 0xffff | ||
197 | #define BF_DIGCTL_RAMREPAIR_ADDR(v) (((v) << 0) & 0xffff) | ||
198 | |||
199 | /** | ||
200 | * Register: HW_DIGCTL_ROMCTRL | ||
201 | * Address: 0x50 | ||
202 | * SCT: yes | ||
203 | */ | ||
204 | #define HW_DIGCTL_ROMCTRL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x0)) | ||
205 | #define HW_DIGCTL_ROMCTRL_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x4)) | ||
206 | #define HW_DIGCTL_ROMCTRL_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x8)) | ||
207 | #define HW_DIGCTL_ROMCTRL_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0xc)) | ||
208 | #define BP_DIGCTL_ROMCTRL_RD_MARGIN 0 | ||
209 | #define BM_DIGCTL_ROMCTRL_RD_MARGIN 0xf | ||
210 | #define BF_DIGCTL_ROMCTRL_RD_MARGIN(v) (((v) << 0) & 0xf) | ||
211 | |||
212 | /** | ||
213 | * Register: HW_DIGCTL_WRITEONCE | ||
214 | * Address: 0x60 | ||
215 | * SCT: no | ||
216 | */ | ||
217 | #define HW_DIGCTL_WRITEONCE (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x60)) | ||
218 | #define BP_DIGCTL_WRITEONCE_BITS 0 | ||
219 | #define BM_DIGCTL_WRITEONCE_BITS 0xffffffff | ||
220 | #define BF_DIGCTL_WRITEONCE_BITS(v) (((v) << 0) & 0xffffffff) | ||
221 | |||
222 | /** | ||
223 | * Register: HW_DIGCTL_ENTROPY | ||
224 | * Address: 0x90 | ||
225 | * SCT: no | ||
226 | */ | ||
227 | #define HW_DIGCTL_ENTROPY (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x90)) | ||
228 | #define BP_DIGCTL_ENTROPY_VALUE 0 | ||
229 | #define BM_DIGCTL_ENTROPY_VALUE 0xffffffff | ||
230 | #define BF_DIGCTL_ENTROPY_VALUE(v) (((v) << 0) & 0xffffffff) | ||
231 | |||
232 | /** | ||
233 | * Register: HW_DIGCTL_ENTROPY_LATCHED | ||
234 | * Address: 0xa0 | ||
235 | * SCT: no | ||
236 | */ | ||
237 | #define HW_DIGCTL_ENTROPY_LATCHED (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xa0)) | ||
238 | #define BP_DIGCTL_ENTROPY_LATCHED_VALUE 0 | ||
239 | #define BM_DIGCTL_ENTROPY_LATCHED_VALUE 0xffffffff | ||
240 | #define BF_DIGCTL_ENTROPY_LATCHED_VALUE(v) (((v) << 0) & 0xffffffff) | ||
241 | |||
242 | /** | ||
243 | * Register: HW_DIGCTL_SJTAGDBG | ||
244 | * Address: 0xb0 | ||
245 | * SCT: yes | ||
246 | */ | ||
247 | #define HW_DIGCTL_SJTAGDBG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x0)) | ||
248 | #define HW_DIGCTL_SJTAGDBG_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x4)) | ||
249 | #define HW_DIGCTL_SJTAGDBG_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x8)) | ||
250 | #define HW_DIGCTL_SJTAGDBG_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0xc)) | ||
251 | #define BP_DIGCTL_SJTAGDBG_SJTAG_STATE 16 | ||
252 | #define BM_DIGCTL_SJTAGDBG_SJTAG_STATE 0x7ff0000 | ||
253 | #define BF_DIGCTL_SJTAGDBG_SJTAG_STATE(v) (((v) << 16) & 0x7ff0000) | ||
254 | #define BP_DIGCTL_SJTAGDBG_SJTAG_TDO 10 | ||
255 | #define BM_DIGCTL_SJTAGDBG_SJTAG_TDO 0x400 | ||
256 | #define BF_DIGCTL_SJTAGDBG_SJTAG_TDO(v) (((v) << 10) & 0x400) | ||
257 | #define BP_DIGCTL_SJTAGDBG_SJTAG_TDI 9 | ||
258 | #define BM_DIGCTL_SJTAGDBG_SJTAG_TDI 0x200 | ||
259 | #define BF_DIGCTL_SJTAGDBG_SJTAG_TDI(v) (((v) << 9) & 0x200) | ||
260 | #define BP_DIGCTL_SJTAGDBG_SJTAG_MODE 8 | ||
261 | #define BM_DIGCTL_SJTAGDBG_SJTAG_MODE 0x100 | ||
262 | #define BF_DIGCTL_SJTAGDBG_SJTAG_MODE(v) (((v) << 8) & 0x100) | ||
263 | #define BP_DIGCTL_SJTAGDBG_DELAYED_ACTIVE 4 | ||
264 | #define BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE 0xf0 | ||
265 | #define BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(v) (((v) << 4) & 0xf0) | ||
266 | #define BP_DIGCTL_SJTAGDBG_ACTIVE 3 | ||
267 | #define BM_DIGCTL_SJTAGDBG_ACTIVE 0x8 | ||
268 | #define BF_DIGCTL_SJTAGDBG_ACTIVE(v) (((v) << 3) & 0x8) | ||
269 | #define BP_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE 2 | ||
270 | #define BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE 0x4 | ||
271 | #define BF_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE(v) (((v) << 2) & 0x4) | ||
272 | #define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA 1 | ||
273 | #define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA 0x2 | ||
274 | #define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA(v) (((v) << 1) & 0x2) | ||
275 | #define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE 0 | ||
276 | #define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE 0x1 | ||
277 | #define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE(v) (((v) << 0) & 0x1) | ||
278 | |||
279 | /** | ||
280 | * Register: HW_DIGCTL_MICROSECONDS | ||
281 | * Address: 0xc0 | ||
282 | * SCT: yes | ||
283 | */ | ||
284 | #define HW_DIGCTL_MICROSECONDS (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x0)) | ||
285 | #define HW_DIGCTL_MICROSECONDS_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x4)) | ||
286 | #define HW_DIGCTL_MICROSECONDS_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x8)) | ||
287 | #define HW_DIGCTL_MICROSECONDS_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0xc)) | ||
288 | #define BP_DIGCTL_MICROSECONDS_VALUE 0 | ||
289 | #define BM_DIGCTL_MICROSECONDS_VALUE 0xffffffff | ||
290 | #define BF_DIGCTL_MICROSECONDS_VALUE(v) (((v) << 0) & 0xffffffff) | ||
291 | |||
292 | /** | ||
293 | * Register: HW_DIGCTL_DBGRD | ||
294 | * Address: 0xd0 | ||
295 | * SCT: no | ||
296 | */ | ||
297 | #define HW_DIGCTL_DBGRD (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xd0)) | ||
298 | #define BP_DIGCTL_DBGRD_COMPLEMENT 0 | ||
299 | #define BM_DIGCTL_DBGRD_COMPLEMENT 0xffffffff | ||
300 | #define BF_DIGCTL_DBGRD_COMPLEMENT(v) (((v) << 0) & 0xffffffff) | ||
301 | |||
302 | /** | ||
303 | * Register: HW_DIGCTL_DBG | ||
304 | * Address: 0xe0 | ||
305 | * SCT: no | ||
306 | */ | ||
307 | #define HW_DIGCTL_DBG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0)) | ||
308 | #define BP_DIGCTL_DBG_VALUE 0 | ||
309 | #define BM_DIGCTL_DBG_VALUE 0xffffffff | ||
310 | #define BF_DIGCTL_DBG_VALUE(v) (((v) << 0) & 0xffffffff) | ||
311 | |||
312 | /** | ||
313 | * Register: HW_DIGCTL_OCRAM_BIST_CSR | ||
314 | * Address: 0xf0 | ||
315 | * SCT: yes | ||
316 | */ | ||
317 | #define HW_DIGCTL_OCRAM_BIST_CSR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x0)) | ||
318 | #define HW_DIGCTL_OCRAM_BIST_CSR_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x4)) | ||
319 | #define HW_DIGCTL_OCRAM_BIST_CSR_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x8)) | ||
320 | #define HW_DIGCTL_OCRAM_BIST_CSR_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0xc)) | ||
321 | #define BP_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE 9 | ||
322 | #define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE 0x200 | ||
323 | #define BF_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE(v) (((v) << 9) & 0x200) | ||
324 | #define BP_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN 8 | ||
325 | #define BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN 0x100 | ||
326 | #define BF_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN(v) (((v) << 8) & 0x100) | ||
327 | #define BP_DIGCTL_OCRAM_BIST_CSR_FAIL 3 | ||
328 | #define BM_DIGCTL_OCRAM_BIST_CSR_FAIL 0x8 | ||
329 | #define BF_DIGCTL_OCRAM_BIST_CSR_FAIL(v) (((v) << 3) & 0x8) | ||
330 | #define BP_DIGCTL_OCRAM_BIST_CSR_PASS 2 | ||
331 | #define BM_DIGCTL_OCRAM_BIST_CSR_PASS 0x4 | ||
332 | #define BF_DIGCTL_OCRAM_BIST_CSR_PASS(v) (((v) << 2) & 0x4) | ||
333 | #define BP_DIGCTL_OCRAM_BIST_CSR_DONE 1 | ||
334 | #define BM_DIGCTL_OCRAM_BIST_CSR_DONE 0x2 | ||
335 | #define BF_DIGCTL_OCRAM_BIST_CSR_DONE(v) (((v) << 1) & 0x2) | ||
336 | #define BP_DIGCTL_OCRAM_BIST_CSR_START 0 | ||
337 | #define BM_DIGCTL_OCRAM_BIST_CSR_START 0x1 | ||
338 | #define BF_DIGCTL_OCRAM_BIST_CSR_START(v) (((v) << 0) & 0x1) | ||
339 | |||
340 | /** | ||
341 | * Register: HW_DIGCTL_OCRAM_STATUS0 | ||
342 | * Address: 0x110 | ||
343 | * SCT: no | ||
344 | */ | ||
345 | #define HW_DIGCTL_OCRAM_STATUS0 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x110)) | ||
346 | #define BP_DIGCTL_OCRAM_STATUS0_FAILDATA00 0 | ||
347 | #define BM_DIGCTL_OCRAM_STATUS0_FAILDATA00 0xffffffff | ||
348 | #define BF_DIGCTL_OCRAM_STATUS0_FAILDATA00(v) (((v) << 0) & 0xffffffff) | ||
349 | |||
350 | /** | ||
351 | * Register: HW_DIGCTL_OCRAM_STATUS1 | ||
352 | * Address: 0x120 | ||
353 | * SCT: no | ||
354 | */ | ||
355 | #define HW_DIGCTL_OCRAM_STATUS1 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x120)) | ||
356 | #define BP_DIGCTL_OCRAM_STATUS1_FAILDATA01 0 | ||
357 | #define BM_DIGCTL_OCRAM_STATUS1_FAILDATA01 0xffffffff | ||
358 | #define BF_DIGCTL_OCRAM_STATUS1_FAILDATA01(v) (((v) << 0) & 0xffffffff) | ||
359 | |||
360 | /** | ||
361 | * Register: HW_DIGCTL_OCRAM_STATUS2 | ||
362 | * Address: 0x130 | ||
363 | * SCT: no | ||
364 | */ | ||
365 | #define HW_DIGCTL_OCRAM_STATUS2 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x130)) | ||
366 | #define BP_DIGCTL_OCRAM_STATUS2_FAILDATA10 0 | ||
367 | #define BM_DIGCTL_OCRAM_STATUS2_FAILDATA10 0xffffffff | ||
368 | #define BF_DIGCTL_OCRAM_STATUS2_FAILDATA10(v) (((v) << 0) & 0xffffffff) | ||
369 | |||
370 | /** | ||
371 | * Register: HW_DIGCTL_OCRAM_STATUS3 | ||
372 | * Address: 0x140 | ||
373 | * SCT: no | ||
374 | */ | ||
375 | #define HW_DIGCTL_OCRAM_STATUS3 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x140)) | ||
376 | #define BP_DIGCTL_OCRAM_STATUS3_FAILDATA11 0 | ||
377 | #define BM_DIGCTL_OCRAM_STATUS3_FAILDATA11 0xffffffff | ||
378 | #define BF_DIGCTL_OCRAM_STATUS3_FAILDATA11(v) (((v) << 0) & 0xffffffff) | ||
379 | |||
380 | /** | ||
381 | * Register: HW_DIGCTL_OCRAM_STATUS4 | ||
382 | * Address: 0x150 | ||
383 | * SCT: no | ||
384 | */ | ||
385 | #define HW_DIGCTL_OCRAM_STATUS4 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x150)) | ||
386 | #define BP_DIGCTL_OCRAM_STATUS4_FAILDATA20 0 | ||
387 | #define BM_DIGCTL_OCRAM_STATUS4_FAILDATA20 0xffffffff | ||
388 | #define BF_DIGCTL_OCRAM_STATUS4_FAILDATA20(v) (((v) << 0) & 0xffffffff) | ||
389 | |||
390 | /** | ||
391 | * Register: HW_DIGCTL_OCRAM_STATUS5 | ||
392 | * Address: 0x160 | ||
393 | * SCT: no | ||
394 | */ | ||
395 | #define HW_DIGCTL_OCRAM_STATUS5 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x160)) | ||
396 | #define BP_DIGCTL_OCRAM_STATUS5_FAILDATA21 0 | ||
397 | #define BM_DIGCTL_OCRAM_STATUS5_FAILDATA21 0xffffffff | ||
398 | #define BF_DIGCTL_OCRAM_STATUS5_FAILDATA21(v) (((v) << 0) & 0xffffffff) | ||
399 | |||
400 | /** | ||
401 | * Register: HW_DIGCTL_OCRAM_STATUS6 | ||
402 | * Address: 0x170 | ||
403 | * SCT: no | ||
404 | */ | ||
405 | #define HW_DIGCTL_OCRAM_STATUS6 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x170)) | ||
406 | #define BP_DIGCTL_OCRAM_STATUS6_FAILDATA30 0 | ||
407 | #define BM_DIGCTL_OCRAM_STATUS6_FAILDATA30 0xffffffff | ||
408 | #define BF_DIGCTL_OCRAM_STATUS6_FAILDATA30(v) (((v) << 0) & 0xffffffff) | ||
409 | |||
410 | /** | ||
411 | * Register: HW_DIGCTL_OCRAM_STATUS7 | ||
412 | * Address: 0x180 | ||
413 | * SCT: no | ||
414 | */ | ||
415 | #define HW_DIGCTL_OCRAM_STATUS7 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x180)) | ||
416 | #define BP_DIGCTL_OCRAM_STATUS7_FAILDATA31 0 | ||
417 | #define BM_DIGCTL_OCRAM_STATUS7_FAILDATA31 0xffffffff | ||
418 | #define BF_DIGCTL_OCRAM_STATUS7_FAILDATA31(v) (((v) << 0) & 0xffffffff) | ||
419 | |||
420 | /** | ||
421 | * Register: HW_DIGCTL_OCRAM_STATUS8 | ||
422 | * Address: 0x190 | ||
423 | * SCT: no | ||
424 | */ | ||
425 | #define HW_DIGCTL_OCRAM_STATUS8 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x190)) | ||
426 | #define BP_DIGCTL_OCRAM_STATUS8_FAILADDR01 16 | ||
427 | #define BM_DIGCTL_OCRAM_STATUS8_FAILADDR01 0xffff0000 | ||
428 | #define BF_DIGCTL_OCRAM_STATUS8_FAILADDR01(v) (((v) << 16) & 0xffff0000) | ||
429 | #define BP_DIGCTL_OCRAM_STATUS8_FAILADDR00 0 | ||
430 | #define BM_DIGCTL_OCRAM_STATUS8_FAILADDR00 0xffff | ||
431 | #define BF_DIGCTL_OCRAM_STATUS8_FAILADDR00(v) (((v) << 0) & 0xffff) | ||
432 | |||
433 | /** | ||
434 | * Register: HW_DIGCTL_OCRAM_STATUS9 | ||
435 | * Address: 0x1a0 | ||
436 | * SCT: no | ||
437 | */ | ||
438 | #define HW_DIGCTL_OCRAM_STATUS9 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1a0)) | ||
439 | #define BP_DIGCTL_OCRAM_STATUS9_FAILADDR11 16 | ||
440 | #define BM_DIGCTL_OCRAM_STATUS9_FAILADDR11 0xffff0000 | ||
441 | #define BF_DIGCTL_OCRAM_STATUS9_FAILADDR11(v) (((v) << 16) & 0xffff0000) | ||
442 | #define BP_DIGCTL_OCRAM_STATUS9_FAILADDR10 0 | ||
443 | #define BM_DIGCTL_OCRAM_STATUS9_FAILADDR10 0xffff | ||
444 | #define BF_DIGCTL_OCRAM_STATUS9_FAILADDR10(v) (((v) << 0) & 0xffff) | ||
445 | |||
446 | /** | ||
447 | * Register: HW_DIGCTL_OCRAM_STATUS10 | ||
448 | * Address: 0x1b0 | ||
449 | * SCT: no | ||
450 | */ | ||
451 | #define HW_DIGCTL_OCRAM_STATUS10 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1b0)) | ||
452 | #define BP_DIGCTL_OCRAM_STATUS10_FAILADDR21 16 | ||
453 | #define BM_DIGCTL_OCRAM_STATUS10_FAILADDR21 0xffff0000 | ||
454 | #define BF_DIGCTL_OCRAM_STATUS10_FAILADDR21(v) (((v) << 16) & 0xffff0000) | ||
455 | #define BP_DIGCTL_OCRAM_STATUS10_FAILADDR20 0 | ||
456 | #define BM_DIGCTL_OCRAM_STATUS10_FAILADDR20 0xffff | ||
457 | #define BF_DIGCTL_OCRAM_STATUS10_FAILADDR20(v) (((v) << 0) & 0xffff) | ||
458 | |||
459 | /** | ||
460 | * Register: HW_DIGCTL_OCRAM_STATUS11 | ||
461 | * Address: 0x1c0 | ||
462 | * SCT: no | ||
463 | */ | ||
464 | #define HW_DIGCTL_OCRAM_STATUS11 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1c0)) | ||
465 | #define BP_DIGCTL_OCRAM_STATUS11_FAILADDR31 16 | ||
466 | #define BM_DIGCTL_OCRAM_STATUS11_FAILADDR31 0xffff0000 | ||
467 | #define BF_DIGCTL_OCRAM_STATUS11_FAILADDR31(v) (((v) << 16) & 0xffff0000) | ||
468 | #define BP_DIGCTL_OCRAM_STATUS11_FAILADDR30 0 | ||
469 | #define BM_DIGCTL_OCRAM_STATUS11_FAILADDR30 0xffff | ||
470 | #define BF_DIGCTL_OCRAM_STATUS11_FAILADDR30(v) (((v) << 0) & 0xffff) | ||
471 | |||
472 | /** | ||
473 | * Register: HW_DIGCTL_OCRAM_STATUS12 | ||
474 | * Address: 0x1d0 | ||
475 | * SCT: no | ||
476 | */ | ||
477 | #define HW_DIGCTL_OCRAM_STATUS12 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1d0)) | ||
478 | #define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE11 24 | ||
479 | #define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11 0x1f000000 | ||
480 | #define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11(v) (((v) << 24) & 0x1f000000) | ||
481 | #define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE10 16 | ||
482 | #define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10 0x1f0000 | ||
483 | #define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10(v) (((v) << 16) & 0x1f0000) | ||
484 | #define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE01 8 | ||
485 | #define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01 0x1f00 | ||
486 | #define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01(v) (((v) << 8) & 0x1f00) | ||
487 | #define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE00 0 | ||
488 | #define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00 0x1f | ||
489 | #define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00(v) (((v) << 0) & 0x1f) | ||
490 | |||
491 | /** | ||
492 | * Register: HW_DIGCTL_OCRAM_STATUS13 | ||
493 | * Address: 0x1e0 | ||
494 | * SCT: no | ||
495 | */ | ||
496 | #define HW_DIGCTL_OCRAM_STATUS13 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1e0)) | ||
497 | #define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE31 24 | ||
498 | #define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31 0x1f000000 | ||
499 | #define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31(v) (((v) << 24) & 0x1f000000) | ||
500 | #define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE30 16 | ||
501 | #define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30 0x1f0000 | ||
502 | #define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30(v) (((v) << 16) & 0x1f0000) | ||
503 | #define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE21 8 | ||
504 | #define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21 0x1f00 | ||
505 | #define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21(v) (((v) << 8) & 0x1f00) | ||
506 | #define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE20 0 | ||
507 | #define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20 0x1f | ||
508 | #define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20(v) (((v) << 0) & 0x1f) | ||
509 | |||
510 | /** | ||
511 | * Register: HW_DIGCTL_SCRATCH0 | ||
512 | * Address: 0x290 | ||
513 | * SCT: no | ||
514 | */ | ||
515 | #define HW_DIGCTL_SCRATCH0 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x290)) | ||
516 | #define BP_DIGCTL_SCRATCH0_PTR 0 | ||
517 | #define BM_DIGCTL_SCRATCH0_PTR 0xffffffff | ||
518 | #define BF_DIGCTL_SCRATCH0_PTR(v) (((v) << 0) & 0xffffffff) | ||
519 | |||
520 | /** | ||
521 | * Register: HW_DIGCTL_SCRATCH1 | ||
522 | * Address: 0x2a0 | ||
523 | * SCT: no | ||
524 | */ | ||
525 | #define HW_DIGCTL_SCRATCH1 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2a0)) | ||
526 | #define BP_DIGCTL_SCRATCH1_PTR 0 | ||
527 | #define BM_DIGCTL_SCRATCH1_PTR 0xffffffff | ||
528 | #define BF_DIGCTL_SCRATCH1_PTR(v) (((v) << 0) & 0xffffffff) | ||
529 | |||
530 | /** | ||
531 | * Register: HW_DIGCTL_ARMCACHE | ||
532 | * Address: 0x2b0 | ||
533 | * SCT: no | ||
534 | */ | ||
535 | #define HW_DIGCTL_ARMCACHE (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2b0)) | ||
536 | #define BP_DIGCTL_ARMCACHE_CACHE_SS 8 | ||
537 | #define BM_DIGCTL_ARMCACHE_CACHE_SS 0x300 | ||
538 | #define BF_DIGCTL_ARMCACHE_CACHE_SS(v) (((v) << 8) & 0x300) | ||
539 | #define BP_DIGCTL_ARMCACHE_DTAG_SS 4 | ||
540 | #define BM_DIGCTL_ARMCACHE_DTAG_SS 0x30 | ||
541 | #define BF_DIGCTL_ARMCACHE_DTAG_SS(v) (((v) << 4) & 0x30) | ||
542 | #define BP_DIGCTL_ARMCACHE_ITAG_SS 0 | ||
543 | #define BM_DIGCTL_ARMCACHE_ITAG_SS 0x3 | ||
544 | #define BF_DIGCTL_ARMCACHE_ITAG_SS(v) (((v) << 0) & 0x3) | ||
545 | |||
546 | /** | ||
547 | * Register: HW_DIGCTL_DEBUG_TRAP_ADDR_LOW | ||
548 | * Address: 0x2c0 | ||
549 | * SCT: no | ||
550 | */ | ||
551 | #define HW_DIGCTL_DEBUG_TRAP_ADDR_LOW (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2c0)) | ||
552 | #define BP_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR 0 | ||
553 | #define BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR 0xffffffff | ||
554 | #define BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(v) (((v) << 0) & 0xffffffff) | ||
555 | |||
556 | /** | ||
557 | * Register: HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH | ||
558 | * Address: 0x2d0 | ||
559 | * SCT: no | ||
560 | */ | ||
561 | #define HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2d0)) | ||
562 | #define BP_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR 0 | ||
563 | #define BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR 0xffffffff | ||
564 | #define BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(v) (((v) << 0) & 0xffffffff) | ||
565 | |||
566 | /** | ||
567 | * Register: HW_DIGCTL_SGTL | ||
568 | * Address: 0x300 | ||
569 | * SCT: no | ||
570 | */ | ||
571 | #define HW_DIGCTL_SGTL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x300)) | ||
572 | #define BP_DIGCTL_SGTL_COPYRIGHT 0 | ||
573 | #define BM_DIGCTL_SGTL_COPYRIGHT 0xffffffff | ||
574 | #define BF_DIGCTL_SGTL_COPYRIGHT(v) (((v) << 0) & 0xffffffff) | ||
575 | |||
576 | /** | ||
577 | * Register: HW_DIGCTL_CHIPID | ||
578 | * Address: 0x310 | ||
579 | * SCT: no | ||
580 | */ | ||
581 | #define HW_DIGCTL_CHIPID (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x310)) | ||
582 | #define BP_DIGCTL_CHIPID_PRODUCT_CODE 16 | ||
583 | #define BM_DIGCTL_CHIPID_PRODUCT_CODE 0xffff0000 | ||
584 | #define BF_DIGCTL_CHIPID_PRODUCT_CODE(v) (((v) << 16) & 0xffff0000) | ||
585 | #define BP_DIGCTL_CHIPID_REVISION 0 | ||
586 | #define BM_DIGCTL_CHIPID_REVISION 0xff | ||
587 | #define BF_DIGCTL_CHIPID_REVISION(v) (((v) << 0) & 0xff) | ||
588 | |||
589 | /** | ||
590 | * Register: HW_DIGCTL_AHB_STATS_SELECT | ||
591 | * Address: 0x330 | ||
592 | * SCT: no | ||
593 | */ | ||
594 | #define HW_DIGCTL_AHB_STATS_SELECT (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x330)) | ||
595 | #define BP_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT 24 | ||
596 | #define BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT 0xf000000 | ||
597 | #define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBH 0x1 | ||
598 | #define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBX 0x2 | ||
599 | #define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__USB 0x4 | ||
600 | #define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(v) (((v) << 24) & 0xf000000) | ||
601 | #define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT_V(v) ((BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__##v << 24) & 0xf000000) | ||
602 | #define BP_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT 16 | ||
603 | #define BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT 0xf0000 | ||
604 | #define BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__ARM_D 0x1 | ||
605 | #define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(v) (((v) << 16) & 0xf0000) | ||
606 | #define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT_V(v) ((BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__##v << 16) & 0xf0000) | ||
607 | #define BP_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT 8 | ||
608 | #define BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT 0xf00 | ||
609 | #define BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__ARM_I 0x1 | ||
610 | #define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(v) (((v) << 8) & 0xf00) | ||
611 | #define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT_V(v) ((BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__##v << 8) & 0xf00) | ||
612 | #define BP_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT 0 | ||
613 | #define BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT 0xf | ||
614 | #define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__ECC8 0x1 | ||
615 | #define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__CRYPTO 0x2 | ||
616 | #define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(v) (((v) << 0) & 0xf) | ||
617 | #define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT_V(v) ((BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__##v << 0) & 0xf) | ||
618 | |||
619 | /** | ||
620 | * Register: HW_DIGCTL_L0_AHB_ACTIVE_CYCLES | ||
621 | * Address: 0x340 | ||
622 | * SCT: no | ||
623 | */ | ||
624 | #define HW_DIGCTL_L0_AHB_ACTIVE_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x340)) | ||
625 | #define BP_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT 0 | ||
626 | #define BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT 0xffffffff | ||
627 | #define BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
628 | |||
629 | /** | ||
630 | * Register: HW_DIGCTL_L0_AHB_DATA_STALLED | ||
631 | * Address: 0x350 | ||
632 | * SCT: no | ||
633 | */ | ||
634 | #define HW_DIGCTL_L0_AHB_DATA_STALLED (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x350)) | ||
635 | #define BP_DIGCTL_L0_AHB_DATA_STALLED_COUNT 0 | ||
636 | #define BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT 0xffffffff | ||
637 | #define BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT(v) (((v) << 0) & 0xffffffff) | ||
638 | |||
639 | /** | ||
640 | * Register: HW_DIGCTL_L0_AHB_DATA_CYCLES | ||
641 | * Address: 0x360 | ||
642 | * SCT: no | ||
643 | */ | ||
644 | #define HW_DIGCTL_L0_AHB_DATA_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x360)) | ||
645 | #define BP_DIGCTL_L0_AHB_DATA_CYCLES_COUNT 0 | ||
646 | #define BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT 0xffffffff | ||
647 | #define BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
648 | |||
649 | /** | ||
650 | * Register: HW_DIGCTL_L1_AHB_ACTIVE_CYCLES | ||
651 | * Address: 0x370 | ||
652 | * SCT: no | ||
653 | */ | ||
654 | #define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x370)) | ||
655 | #define BP_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT 0 | ||
656 | #define BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT 0xffffffff | ||
657 | #define BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
658 | |||
659 | /** | ||
660 | * Register: HW_DIGCTL_L1_AHB_DATA_STALLED | ||
661 | * Address: 0x380 | ||
662 | * SCT: no | ||
663 | */ | ||
664 | #define HW_DIGCTL_L1_AHB_DATA_STALLED (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x380)) | ||
665 | #define BP_DIGCTL_L1_AHB_DATA_STALLED_COUNT 0 | ||
666 | #define BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT 0xffffffff | ||
667 | #define BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT(v) (((v) << 0) & 0xffffffff) | ||
668 | |||
669 | /** | ||
670 | * Register: HW_DIGCTL_L1_AHB_DATA_CYCLES | ||
671 | * Address: 0x390 | ||
672 | * SCT: no | ||
673 | */ | ||
674 | #define HW_DIGCTL_L1_AHB_DATA_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x390)) | ||
675 | #define BP_DIGCTL_L1_AHB_DATA_CYCLES_COUNT 0 | ||
676 | #define BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT 0xffffffff | ||
677 | #define BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
678 | |||
679 | /** | ||
680 | * Register: HW_DIGCTL_L2_AHB_ACTIVE_CYCLES | ||
681 | * Address: 0x3a0 | ||
682 | * SCT: no | ||
683 | */ | ||
684 | #define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3a0)) | ||
685 | #define BP_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT 0 | ||
686 | #define BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT 0xffffffff | ||
687 | #define BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
688 | |||
689 | /** | ||
690 | * Register: HW_DIGCTL_L2_AHB_DATA_STALLED | ||
691 | * Address: 0x3b0 | ||
692 | * SCT: no | ||
693 | */ | ||
694 | #define HW_DIGCTL_L2_AHB_DATA_STALLED (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3b0)) | ||
695 | #define BP_DIGCTL_L2_AHB_DATA_STALLED_COUNT 0 | ||
696 | #define BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT 0xffffffff | ||
697 | #define BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT(v) (((v) << 0) & 0xffffffff) | ||
698 | |||
699 | /** | ||
700 | * Register: HW_DIGCTL_L2_AHB_DATA_CYCLES | ||
701 | * Address: 0x3c0 | ||
702 | * SCT: no | ||
703 | */ | ||
704 | #define HW_DIGCTL_L2_AHB_DATA_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3c0)) | ||
705 | #define BP_DIGCTL_L2_AHB_DATA_CYCLES_COUNT 0 | ||
706 | #define BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT 0xffffffff | ||
707 | #define BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
708 | |||
709 | /** | ||
710 | * Register: HW_DIGCTL_L3_AHB_ACTIVE_CYCLES | ||
711 | * Address: 0x3d0 | ||
712 | * SCT: no | ||
713 | */ | ||
714 | #define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3d0)) | ||
715 | #define BP_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT 0 | ||
716 | #define BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT 0xffffffff | ||
717 | #define BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
718 | |||
719 | /** | ||
720 | * Register: HW_DIGCTL_L3_AHB_DATA_STALLED | ||
721 | * Address: 0x3e0 | ||
722 | * SCT: no | ||
723 | */ | ||
724 | #define HW_DIGCTL_L3_AHB_DATA_STALLED (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3e0)) | ||
725 | #define BP_DIGCTL_L3_AHB_DATA_STALLED_COUNT 0 | ||
726 | #define BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT 0xffffffff | ||
727 | #define BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT(v) (((v) << 0) & 0xffffffff) | ||
728 | |||
729 | /** | ||
730 | * Register: HW_DIGCTL_L3_AHB_DATA_CYCLES | ||
731 | * Address: 0x3f0 | ||
732 | * SCT: no | ||
733 | */ | ||
734 | #define HW_DIGCTL_L3_AHB_DATA_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3f0)) | ||
735 | #define BP_DIGCTL_L3_AHB_DATA_CYCLES_COUNT 0 | ||
736 | #define BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT 0xffffffff | ||
737 | #define BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
738 | |||
739 | /** | ||
740 | * Register: HW_DIGCTL_MPTEn_LOC | ||
741 | * Address: 0x400+n*0x10 | ||
742 | * SCT: no | ||
743 | */ | ||
744 | #define HW_DIGCTL_MPTEn_LOC(n) (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x400+(n)*0x10)) | ||
745 | #define BP_DIGCTL_MPTEn_LOC_LOC 0 | ||
746 | #define BM_DIGCTL_MPTEn_LOC_LOC 0xfff | ||
747 | #define BF_DIGCTL_MPTEn_LOC_LOC(v) (((v) << 0) & 0xfff) | ||
748 | |||
749 | /** | ||
750 | * Register: HW_DIGCTL_EMICLK_DELAY | ||
751 | * Address: 0x480 | ||
752 | * SCT: no | ||
753 | */ | ||
754 | #define HW_DIGCTL_EMICLK_DELAY (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x480)) | ||
755 | #define BP_DIGCTL_EMICLK_DELAY_NUM_TAPS 0 | ||
756 | #define BM_DIGCTL_EMICLK_DELAY_NUM_TAPS 0x1f | ||
757 | #define BF_DIGCTL_EMICLK_DELAY_NUM_TAPS(v) (((v) << 0) & 0x1f) | ||
758 | |||
759 | #endif /* __HEADERGEN__STMP3700__DIGCTL__H__ */ | ||