diff options
Diffstat (limited to 'firmware/target/arm/imx233/regs/stmp3600/regs-memcpy.h')
-rw-r--r-- | firmware/target/arm/imx233/regs/stmp3600/regs-memcpy.h | 105 |
1 files changed, 105 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-memcpy.h b/firmware/target/arm/imx233/regs/stmp3600/regs-memcpy.h new file mode 100644 index 0000000000..3ba723eab3 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-memcpy.h | |||
@@ -0,0 +1,105 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__MEMCPY__H__ | ||
24 | #define __HEADERGEN__STMP3600__MEMCPY__H__ | ||
25 | |||
26 | #define REGS_MEMCPY_BASE (0x80014000) | ||
27 | |||
28 | #define REGS_MEMCPY_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_MEMCPY_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_MEMCPY_CTRL (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0x0)) | ||
36 | #define HW_MEMCPY_CTRL_SET (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0x4)) | ||
37 | #define HW_MEMCPY_CTRL_CLR (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0x8)) | ||
38 | #define HW_MEMCPY_CTRL_TOG (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0xc)) | ||
39 | #define BP_MEMCPY_CTRL_SFTRST 31 | ||
40 | #define BM_MEMCPY_CTRL_SFTRST 0x80000000 | ||
41 | #define BV_MEMCPY_CTRL_SFTRST__RUN 0x0 | ||
42 | #define BV_MEMCPY_CTRL_SFTRST__RESET 0x1 | ||
43 | #define BF_MEMCPY_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
44 | #define BF_MEMCPY_CTRL_SFTRST_V(v) ((BV_MEMCPY_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
45 | #define BP_MEMCPY_CTRL_CLKGATE 30 | ||
46 | #define BM_MEMCPY_CTRL_CLKGATE 0x40000000 | ||
47 | #define BV_MEMCPY_CTRL_CLKGATE__RUN 0x0 | ||
48 | #define BV_MEMCPY_CTRL_CLKGATE__NO_CLKS 0x1 | ||
49 | #define BF_MEMCPY_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
50 | #define BF_MEMCPY_CTRL_CLKGATE_V(v) ((BV_MEMCPY_CTRL_CLKGATE__##v << 30) & 0x40000000) | ||
51 | #define BP_MEMCPY_CTRL_PRESENT 29 | ||
52 | #define BM_MEMCPY_CTRL_PRESENT 0x20000000 | ||
53 | #define BV_MEMCPY_CTRL_PRESENT__UNAVAILABLE 0x0 | ||
54 | #define BV_MEMCPY_CTRL_PRESENT__AVAILABLE 0x1 | ||
55 | #define BF_MEMCPY_CTRL_PRESENT(v) (((v) << 29) & 0x20000000) | ||
56 | #define BF_MEMCPY_CTRL_PRESENT_V(v) ((BV_MEMCPY_CTRL_PRESENT__##v << 29) & 0x20000000) | ||
57 | #define BP_MEMCPY_CTRL_BURST 16 | ||
58 | #define BM_MEMCPY_CTRL_BURST 0x10000 | ||
59 | #define BF_MEMCPY_CTRL_BURST(v) (((v) << 16) & 0x10000) | ||
60 | #define BP_MEMCPY_CTRL_XFER_SIZE 0 | ||
61 | #define BM_MEMCPY_CTRL_XFER_SIZE 0xffff | ||
62 | #define BF_MEMCPY_CTRL_XFER_SIZE(v) (((v) << 0) & 0xffff) | ||
63 | |||
64 | /** | ||
65 | * Register: HW_MEMCPY_DATA | ||
66 | * Address: 0x10 | ||
67 | * SCT: yes | ||
68 | */ | ||
69 | #define HW_MEMCPY_DATA (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0x0)) | ||
70 | #define HW_MEMCPY_DATA_SET (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0x4)) | ||
71 | #define HW_MEMCPY_DATA_CLR (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0x8)) | ||
72 | #define HW_MEMCPY_DATA_TOG (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0xc)) | ||
73 | #define BP_MEMCPY_DATA_DATA 0 | ||
74 | #define BM_MEMCPY_DATA_DATA 0xffffffff | ||
75 | #define BF_MEMCPY_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
76 | |||
77 | /** | ||
78 | * Register: HW_MEMCPY_DEBUG | ||
79 | * Address: 0x20 | ||
80 | * SCT: no | ||
81 | */ | ||
82 | #define HW_MEMCPY_DEBUG (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x20)) | ||
83 | #define BP_MEMCPY_DEBUG_DST_END_CMD 30 | ||
84 | #define BM_MEMCPY_DEBUG_DST_END_CMD 0x40000000 | ||
85 | #define BF_MEMCPY_DEBUG_DST_END_CMD(v) (((v) << 30) & 0x40000000) | ||
86 | #define BP_MEMCPY_DEBUG_DST_KICK 29 | ||
87 | #define BM_MEMCPY_DEBUG_DST_KICK 0x20000000 | ||
88 | #define BF_MEMCPY_DEBUG_DST_KICK(v) (((v) << 29) & 0x20000000) | ||
89 | #define BP_MEMCPY_DEBUG_DST_DMA_REQ 28 | ||
90 | #define BM_MEMCPY_DEBUG_DST_DMA_REQ 0x10000000 | ||
91 | #define BF_MEMCPY_DEBUG_DST_DMA_REQ(v) (((v) << 28) & 0x10000000) | ||
92 | #define BP_MEMCPY_DEBUG_SRC_KICK 25 | ||
93 | #define BM_MEMCPY_DEBUG_SRC_KICK 0x2000000 | ||
94 | #define BF_MEMCPY_DEBUG_SRC_KICK(v) (((v) << 25) & 0x2000000) | ||
95 | #define BP_MEMCPY_DEBUG_SRC_DMA_REQ 24 | ||
96 | #define BM_MEMCPY_DEBUG_SRC_DMA_REQ 0x1000000 | ||
97 | #define BF_MEMCPY_DEBUG_SRC_DMA_REQ(v) (((v) << 24) & 0x1000000) | ||
98 | #define BP_MEMCPY_DEBUG_WRITE_STATE 2 | ||
99 | #define BM_MEMCPY_DEBUG_WRITE_STATE 0xc | ||
100 | #define BF_MEMCPY_DEBUG_WRITE_STATE(v) (((v) << 2) & 0xc) | ||
101 | #define BP_MEMCPY_DEBUG_READ_STATE 0 | ||
102 | #define BM_MEMCPY_DEBUG_READ_STATE 0x3 | ||
103 | #define BF_MEMCPY_DEBUG_READ_STATE(v) (((v) << 0) & 0x3) | ||
104 | |||
105 | #endif /* __HEADERGEN__STMP3600__MEMCPY__H__ */ | ||