diff options
Diffstat (limited to 'firmware/target/arm/imx233/crt0.S')
-rw-r--r-- | firmware/target/arm/imx233/crt0.S | 34 |
1 files changed, 26 insertions, 8 deletions
diff --git a/firmware/target/arm/imx233/crt0.S b/firmware/target/arm/imx233/crt0.S index b8b63e5f26..a0f9ec270b 100644 --- a/firmware/target/arm/imx233/crt0.S +++ b/firmware/target/arm/imx233/crt0.S | |||
@@ -39,6 +39,13 @@ start: | |||
39 | /* Save r0 */ | 39 | /* Save r0 */ |
40 | mov r6, r0 | 40 | mov r6, r0 |
41 | msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */ | 41 | msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */ |
42 | /* Disable MMU, disable caching and buffering; | ||
43 | * use low exception range address (the core uses high range by default) */ | ||
44 | mrc p15, 0, r0, c1, c0, 0 | ||
45 | ldr r1, =0x3005 | ||
46 | bic r0, r1 | ||
47 | mcr p15, 0, r0, c1, c0, 0 | ||
48 | |||
42 | /* Zero out IBSS */ | 49 | /* Zero out IBSS */ |
43 | ldr r2, =_iedata | 50 | ldr r2, =_iedata |
44 | ldr r3, =_iend | 51 | ldr r3, =_iend |
@@ -59,6 +66,22 @@ start: | |||
59 | strhi r5, [r3], #4 | 66 | strhi r5, [r3], #4 |
60 | bhi 1b | 67 | bhi 1b |
61 | 68 | ||
69 | #ifdef HAVE_INIT_ATTR | ||
70 | /* copy init data to codec buffer */ | ||
71 | /* must be done before bss is zeroed */ | ||
72 | ldr r2, =_initcopy | ||
73 | ldr r3, =_initstart | ||
74 | ldr r4, =_initend | ||
75 | 1: | ||
76 | cmp r4, r3 | ||
77 | ldrhi r5, [r2], #4 | ||
78 | strhi r5, [r3], #4 | ||
79 | bhi 1b | ||
80 | |||
81 | mov r2, #0 | ||
82 | mcr p15, 0, r2, c7, c5, 0 @ Invalidate ICache | ||
83 | #endif | ||
84 | |||
62 | /* Initialise bss section to zero */ | 85 | /* Initialise bss section to zero */ |
63 | ldr r2, =_edata | 86 | ldr r2, =_edata |
64 | ldr r3, =_end | 87 | ldr r3, =_end |
@@ -68,7 +91,6 @@ start: | |||
68 | strhi r4, [r2], #4 | 91 | strhi r4, [r2], #4 |
69 | bhi 1b | 92 | bhi 1b |
70 | 93 | ||
71 | |||
72 | /* Set up some stack and munge it with 0xdeadbeef */ | 94 | /* Set up some stack and munge it with 0xdeadbeef */ |
73 | ldr sp, =stackend | 95 | ldr sp, =stackend |
74 | ldr r2, =stackbegin | 96 | ldr r2, =stackbegin |
@@ -92,16 +114,12 @@ start: | |||
92 | msr cpsr_c, #0xdb | 114 | msr cpsr_c, #0xdb |
93 | ldr sp, =irq_stack | 115 | ldr sp, =irq_stack |
94 | 116 | ||
117 | /* Enable MMU */ | ||
118 | bl memory_init | ||
119 | |||
95 | /* Switch back to supervisor mode */ | 120 | /* Switch back to supervisor mode */ |
96 | msr cpsr_c, #0xd3 | 121 | msr cpsr_c, #0xd3 |
97 | 122 | ||
98 | /* Disable MMU, disable caching and buffering; | ||
99 | * use low exception range address (the core uses high range by default) */ | ||
100 | mrc p15, 0, r0, c1, c0, 0 | ||
101 | ldr r1, =0x3005 | ||
102 | bic r0, r1 | ||
103 | mcr p15, 0, r0, c1, c0, 0 | ||
104 | |||
105 | /* Jump to main */ | 123 | /* Jump to main */ |
106 | mov r0, r6 | 124 | mov r0, r6 |
107 | bl main | 125 | bl main |