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Diffstat (limited to 'firmware/target/arm/imx233/crt0.S')
-rw-r--r--firmware/target/arm/imx233/crt0.S13
1 files changed, 10 insertions, 3 deletions
diff --git a/firmware/target/arm/imx233/crt0.S b/firmware/target/arm/imx233/crt0.S
index a0f9ec270b..ab0250f6b6 100644
--- a/firmware/target/arm/imx233/crt0.S
+++ b/firmware/target/arm/imx233/crt0.S
@@ -33,6 +33,9 @@
33 ldr pc, =irq_handler 33 ldr pc, =irq_handler
34 ldr pc, =fiq_handler 34 ldr pc, =fiq_handler
35 35
36/* When starting, we are running at 0x40000000 but the code
37 * assumes DRAM is somewhere else (for caching) so we first need to
38 * setup the MMU and then jump to the right location */
36.text 39.text
37.global start 40.global start
38start: 41start:
@@ -46,6 +49,13 @@ start:
46 bic r0, r1 49 bic r0, r1
47 mcr p15, 0, r0, c1, c0, 0 50 mcr p15, 0, r0, c1, c0, 0
48 51
52 /* Enable MMU */
53 bl memory_init
54
55 /* Jump to real location */
56 ldr pc, =remap
57remap:
58
49 /* Zero out IBSS */ 59 /* Zero out IBSS */
50 ldr r2, =_iedata 60 ldr r2, =_iedata
51 ldr r3, =_iend 61 ldr r3, =_iend
@@ -114,9 +124,6 @@ start:
114 msr cpsr_c, #0xdb 124 msr cpsr_c, #0xdb
115 ldr sp, =irq_stack 125 ldr sp, =irq_stack
116 126
117 /* Enable MMU */
118 bl memory_init
119
120 /* Switch back to supervisor mode */ 127 /* Switch back to supervisor mode */
121 msr cpsr_c, #0xd3 128 msr cpsr_c, #0xd3
122 129