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author | Amaury Pouly <pamaury@rockbox.org> | 2011-09-05 11:29:32 +0000 |
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committer | Amaury Pouly <pamaury@rockbox.org> | 2011-09-05 11:29:32 +0000 |
commit | 7d4fed53cc1e8b0e5aa250ebea3a1b53fc3a50b2 (patch) | |
tree | 236a72d742675715fd599daaa98af8f4eeb45ad8 /firmware/target/arm/imx233/crt0.S | |
parent | 11e1f71612f6c1ef8c17f8ceea17f69fd4bc7b02 (diff) | |
download | rockbox-7d4fed53cc1e8b0e5aa250ebea3a1b53fc3a50b2.tar.gz rockbox-7d4fed53cc1e8b0e5aa250ebea3a1b53fc3a50b2.zip |
imx233:fuze+: major memory and usb rework
- now identity map dram uncached and have a cached and buffered virtual alias
- rework dma to handle virtual to physical pointers conversion
- fix lcd frame pointer
- implement usb detection properly
- implement bootloader usb properly
- allow the bootloader to disable MMC windowing (useful for recovery)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30432 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/imx233/crt0.S')
-rw-r--r-- | firmware/target/arm/imx233/crt0.S | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/firmware/target/arm/imx233/crt0.S b/firmware/target/arm/imx233/crt0.S index a0f9ec270b..ab0250f6b6 100644 --- a/firmware/target/arm/imx233/crt0.S +++ b/firmware/target/arm/imx233/crt0.S | |||
@@ -33,6 +33,9 @@ | |||
33 | ldr pc, =irq_handler | 33 | ldr pc, =irq_handler |
34 | ldr pc, =fiq_handler | 34 | ldr pc, =fiq_handler |
35 | 35 | ||
36 | /* When starting, we are running at 0x40000000 but the code | ||
37 | * assumes DRAM is somewhere else (for caching) so we first need to | ||
38 | * setup the MMU and then jump to the right location */ | ||
36 | .text | 39 | .text |
37 | .global start | 40 | .global start |
38 | start: | 41 | start: |
@@ -46,6 +49,13 @@ start: | |||
46 | bic r0, r1 | 49 | bic r0, r1 |
47 | mcr p15, 0, r0, c1, c0, 0 | 50 | mcr p15, 0, r0, c1, c0, 0 |
48 | 51 | ||
52 | /* Enable MMU */ | ||
53 | bl memory_init | ||
54 | |||
55 | /* Jump to real location */ | ||
56 | ldr pc, =remap | ||
57 | remap: | ||
58 | |||
49 | /* Zero out IBSS */ | 59 | /* Zero out IBSS */ |
50 | ldr r2, =_iedata | 60 | ldr r2, =_iedata |
51 | ldr r3, =_iend | 61 | ldr r3, =_iend |
@@ -114,9 +124,6 @@ start: | |||
114 | msr cpsr_c, #0xdb | 124 | msr cpsr_c, #0xdb |
115 | ldr sp, =irq_stack | 125 | ldr sp, =irq_stack |
116 | 126 | ||
117 | /* Enable MMU */ | ||
118 | bl memory_init | ||
119 | |||
120 | /* Switch back to supervisor mode */ | 127 | /* Switch back to supervisor mode */ |
121 | msr cpsr_c, #0xd3 | 128 | msr cpsr_c, #0xd3 |
122 | 129 | ||