diff options
Diffstat (limited to 'firmware/target/arm/crt0-pp.S')
-rw-r--r-- | firmware/target/arm/crt0-pp.S | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/firmware/target/arm/crt0-pp.S b/firmware/target/arm/crt0-pp.S index f698783017..210b560560 100644 --- a/firmware/target/arm/crt0-pp.S +++ b/firmware/target/arm/crt0-pp.S | |||
@@ -41,7 +41,6 @@ start: | |||
41 | .equ COP_CTRL, 0xcf004058 | 41 | .equ COP_CTRL, 0xcf004058 |
42 | .equ CPU_STATUS, 0xcf004050 | 42 | .equ CPU_STATUS, 0xcf004050 |
43 | .equ COP_STATUS, 0xcf004050 | 43 | .equ COP_STATUS, 0xcf004050 |
44 | .equ IIS_CONFIG, 0xc0002500 | ||
45 | .equ SLEEP, 0x000000ca | 44 | .equ SLEEP, 0x000000ca |
46 | .equ WAKE, 0x000000ce | 45 | .equ WAKE, 0x000000ce |
47 | .equ CPUSLEEPING, 0x00008000 | 46 | .equ CPUSLEEPING, 0x00008000 |
@@ -63,7 +62,6 @@ start: | |||
63 | .equ COP_ICLR, 0x60004038 | 62 | .equ COP_ICLR, 0x60004038 |
64 | .equ COP_CTRL, 0x60007004 | 63 | .equ COP_CTRL, 0x60007004 |
65 | .equ COP_STATUS, 0x60007004 | 64 | .equ COP_STATUS, 0x60007004 |
66 | .equ IIS_CONFIG, 0x70002800 | ||
67 | .equ SLEEP, 0x80000000 | 65 | .equ SLEEP, 0x80000000 |
68 | .equ WAKE, 0x00000000 | 66 | .equ WAKE, 0x00000000 |
69 | .equ CPUSLEEPING, 0x80000000 | 67 | .equ CPUSLEEPING, 0x80000000 |
@@ -186,6 +184,9 @@ cpu_init: | |||
186 | ldr r3, [r4] | 184 | ldr r3, [r4] |
187 | tst r3, #COPSLEEPING | 185 | tst r3, #COPSLEEPING |
188 | beq 1b | 186 | beq 1b |
187 | |||
188 | /* Vectors and IRAM copy is done first since they are reclaimed for | ||
189 | * other uninitialized sections */ | ||
189 | 190 | ||
190 | /* Copy exception handler code to address 0 */ | 191 | /* Copy exception handler code to address 0 */ |
191 | ldr r2, =_vectorsstart | 192 | ldr r2, =_vectorsstart |
@@ -196,16 +197,7 @@ cpu_init: | |||
196 | ldrhi r5, [r4], #4 | 197 | ldrhi r5, [r4], #4 |
197 | strhi r5, [r2], #4 | 198 | strhi r5, [r2], #4 |
198 | bhi 1b | 199 | bhi 1b |
199 | 200 | ||
200 | /* Zero out IBSS */ | ||
201 | ldr r2, =_iedata | ||
202 | ldr r3, =_iend | ||
203 | mov r4, #0 | ||
204 | 1: | ||
205 | cmp r3, r2 | ||
206 | strhi r4, [r2], #4 | ||
207 | bhi 1b | ||
208 | |||
209 | /* Copy the IRAM */ | 201 | /* Copy the IRAM */ |
210 | ldr r2, =_iramcopy | 202 | ldr r2, =_iramcopy |
211 | ldr r3, =_iramstart | 203 | ldr r3, =_iramstart |
@@ -216,6 +208,15 @@ cpu_init: | |||
216 | strhi r5, [r3], #4 | 208 | strhi r5, [r3], #4 |
217 | bhi 1b | 209 | bhi 1b |
218 | 210 | ||
211 | /* Zero out IBSS */ | ||
212 | ldr r2, =_iedata | ||
213 | ldr r3, =_iend | ||
214 | mov r4, #0 | ||
215 | 1: | ||
216 | cmp r3, r2 | ||
217 | strhi r4, [r2], #4 | ||
218 | bhi 1b | ||
219 | |||
219 | /* Initialise bss section to zero */ | 220 | /* Initialise bss section to zero */ |
220 | ldr r2, =_edata | 221 | ldr r2, =_edata |
221 | ldr r3, =_end | 222 | ldr r3, =_end |