diff options
Diffstat (limited to 'firmware/target/arm/crt0-pp.S')
| -rw-r--r-- | firmware/target/arm/crt0-pp.S | 84 |
1 files changed, 46 insertions, 38 deletions
diff --git a/firmware/target/arm/crt0-pp.S b/firmware/target/arm/crt0-pp.S index 8fd1e31f09..dac666ca1c 100644 --- a/firmware/target/arm/crt0-pp.S +++ b/firmware/target/arm/crt0-pp.S | |||
| @@ -32,45 +32,49 @@ start: | |||
| 32 | * | 32 | * |
| 33 | */ | 33 | */ |
| 34 | #if CONFIG_CPU == PP5002 | 34 | #if CONFIG_CPU == PP5002 |
| 35 | .equ PROC_ID, 0xc4000000 | 35 | .equ PROC_ID, 0xc4000000 |
| 36 | .equ CPU_ICLR, 0xcf001028 | 36 | .equ CPU_ICLR, 0xcf001028 |
| 37 | .equ CPU_CTRL, 0xcf004054 | 37 | .equ CPU_CTRL, 0xcf004054 |
| 38 | .equ COP_ICLR, 0xcf001038 | 38 | .equ COP_ICLR, 0xcf001038 |
| 39 | .equ COP_CTRL, 0xcf004058 | 39 | .equ COP_CTRL, 0xcf004058 |
| 40 | .equ COP_STATUS, 0xcf004050 | 40 | .equ CPU_STATUS, 0xcf004050 |
| 41 | .equ IIS_CONFIG, 0xc0002500 | 41 | .equ COP_STATUS, 0xcf004050 |
| 42 | .equ SLEEP, 0x000000ca | 42 | .equ IIS_CONFIG, 0xc0002500 |
| 43 | .equ WAKE, 0x000000ce | 43 | .equ SLEEP, 0x000000ca |
| 44 | .equ SLEEPING, 0x00004000 | 44 | .equ WAKE, 0x000000ce |
| 45 | .equ MMAP_LOG, 0xf000f010 /* MMAP2 */ | 45 | .equ CPUSLEEPING, 0x00008000 |
| 46 | .equ MMAP_PHYS, 0xf000f014 | 46 | .equ COPSLEEPING, 0x00004000 |
| 47 | .equ CACHE_CTRL, 0xcf004024 | ||
| 48 | .equ MMAP_LOG, 0xf000f000 /* MMAP0 */ | ||
| 49 | .equ MMAP_PHYS, 0xf000f004 | ||
| 47 | #if MEM > 32 | 50 | #if MEM > 32 |
| 48 | .equ MMAP_MASK, 0x00007400 | 51 | .equ MMAP_MASK, 0x00003c00 |
| 49 | #else | 52 | #else |
| 50 | .equ MMAP_MASK, 0x00003a00 | 53 | .equ MMAP_MASK, 0x00003e00 |
| 51 | #endif | 54 | #endif |
| 52 | .equ MMAP_FLAGS, 0x00003f84 | 55 | .equ MMAP_FLAGS, 0x00003f84 |
| 53 | #else | 56 | #else |
| 54 | .equ PROC_ID, 0x60000000 | 57 | .equ PROC_ID, 0x60000000 |
| 55 | .equ CPU_ICLR, 0x60004028 | 58 | .equ CPU_ICLR, 0x60004028 |
| 56 | .equ CPU_CTRL, 0x60007000 | 59 | .equ CPU_CTRL, 0x60007000 |
| 57 | .equ CPU_STATUS, 0x60007000 | 60 | .equ CPU_STATUS, 0x60007000 |
| 58 | .equ COP_ICLR, 0x60004038 | 61 | .equ COP_ICLR, 0x60004038 |
| 59 | .equ COP_CTRL, 0x60007004 | 62 | .equ COP_CTRL, 0x60007004 |
| 60 | .equ COP_STATUS, 0x60007004 | 63 | .equ COP_STATUS, 0x60007004 |
| 61 | .equ IIS_CONFIG, 0x70002800 | 64 | .equ IIS_CONFIG, 0x70002800 |
| 62 | .equ SLEEP, 0x80000000 | 65 | .equ SLEEP, 0x80000000 |
| 63 | .equ WAKE, 0x00000000 | 66 | .equ WAKE, 0x00000000 |
| 64 | .equ SLEEPING, 0x80000000 | 67 | .equ CPUSLEEPING, 0x80000000 |
| 65 | .equ CACHE_CTRL, 0x6000c000 | 68 | .equ COPSLEEPING, 0x80000000 |
| 66 | .equ MMAP_LOG, 0xf000f000 /* MMAP0 */ | 69 | .equ CACHE_CTRL, 0x6000c000 |
| 67 | .equ MMAP_PHYS, 0xf000f004 | 70 | .equ MMAP_LOG, 0xf000f000 /* MMAP0 */ |
| 71 | .equ MMAP_PHYS, 0xf000f004 | ||
| 68 | #if MEM > 32 | 72 | #if MEM > 32 |
| 69 | .equ MMAP_MASK, 0x00003c00 | 73 | .equ MMAP_MASK, 0x00003c00 |
| 70 | #else | 74 | #else |
| 71 | .equ MMAP_MASK, 0x00003e00 | 75 | .equ MMAP_MASK, 0x00003e00 |
| 72 | #endif | 76 | #endif |
| 73 | .equ MMAP_FLAGS, 0x00000f84 | 77 | .equ MMAP_FLAGS, 0x00000f84 |
| 74 | #endif | 78 | #endif |
| 75 | 79 | ||
| 76 | msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */ | 80 | msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */ |
| @@ -111,21 +115,22 @@ pad_skip: | |||
| 111 | ldrne r2, =COP_CTRL | 115 | ldrne r2, =COP_CTRL |
| 112 | movne r1, #SLEEP | 116 | movne r1, #SLEEP |
| 113 | strne r1, [r2] | 117 | strne r1, [r2] |
| 118 | nop | ||
| 119 | nop | ||
| 120 | nop | ||
| 114 | 121 | ||
| 115 | /* wait for co-processor to sleep then CPU can begin its remapping */ | 122 | /* wait for co-processor to sleep then CPU can begin its remapping */ |
| 116 | ldreq r2, =COP_STATUS | 123 | ldreq r2, =COP_STATUS |
| 117 | 1: | 124 | 1: |
| 118 | ldreq r1, [r2] | 125 | ldreq r1, [r2] |
| 119 | tsteq r1, #SLEEPING | 126 | tsteq r1, #COPSLEEPING |
| 120 | beq 1b | 127 | beq 1b |
| 121 | 128 | ||
| 122 | #ifdef CPU_PP502x | ||
| 123 | /* disable cache and local interrupt vectors - it is really not desireable | 129 | /* disable cache and local interrupt vectors - it is really not desireable |
| 124 | to have them enabled here */ | 130 | to have them enabled here */ |
| 125 | ldr r2, =CACHE_CTRL | 131 | ldr r2, =CACHE_CTRL |
| 126 | mov r1, #0 | 132 | mov r1, #0 |
| 127 | str r1, [r2] | 133 | str r1, [r2] |
| 128 | #endif | ||
| 129 | 134 | ||
| 130 | mov r2, #0x40000000 | 135 | mov r2, #0x40000000 |
| 131 | ldr r3, =remap_start | 136 | ldr r3, =remap_start |
| @@ -165,6 +170,9 @@ remap_end: | |||
| 165 | /* Sleep us (co-processor) and wait for CPU to do kernel initialization */ | 170 | /* Sleep us (co-processor) and wait for CPU to do kernel initialization */ |
| 166 | movne r3, #SLEEP | 171 | movne r3, #SLEEP |
| 167 | str r3, [r4] | 172 | str r3, [r4] |
| 173 | nop | ||
| 174 | nop | ||
| 175 | nop | ||
| 168 | 176 | ||
| 169 | /* Jump to co-processor init */ | 177 | /* Jump to co-processor init */ |
| 170 | ldrne pc, =cop_init | 178 | ldrne pc, =cop_init |
| @@ -174,7 +182,7 @@ cpu_init: | |||
| 174 | ldr r4, =COP_STATUS | 182 | ldr r4, =COP_STATUS |
| 175 | 1: | 183 | 1: |
| 176 | ldr r3, [r4] | 184 | ldr r3, [r4] |
| 177 | tst r3, #SLEEPING | 185 | tst r3, #COPSLEEPING |
| 178 | beq 1b | 186 | beq 1b |
| 179 | 187 | ||
| 180 | /* Copy exception handler code to address 0 */ | 188 | /* Copy exception handler code to address 0 */ |
| @@ -275,7 +283,7 @@ cop_init: | |||
| 275 | ldr r4, =CPU_STATUS | 283 | ldr r4, =CPU_STATUS |
| 276 | 1: | 284 | 1: |
| 277 | ldr r3, [r4] | 285 | ldr r3, [r4] |
| 278 | tst r3, #SLEEPING | 286 | tst r3, #CPUSLEEPING |
| 279 | beq 1b | 287 | beq 1b |
| 280 | #endif | 288 | #endif |
| 281 | 289 | ||
| @@ -377,7 +385,7 @@ UIE: | |||
| 377 | #endif | 385 | #endif |
| 378 | 386 | ||
| 379 | /* Align stacks to cache line boundary */ | 387 | /* Align stacks to cache line boundary */ |
| 380 | .balign 16 | 388 | .balign 32 |
| 381 | 389 | ||
| 382 | /* 256 words of IRQ stack */ | 390 | /* 256 words of IRQ stack */ |
| 383 | .space 256*4 | 391 | .space 256*4 |