diff options
Diffstat (limited to 'firmware/target/arm/crt0-pp-bl.S')
-rw-r--r-- | firmware/target/arm/crt0-pp-bl.S | 113 |
1 files changed, 59 insertions, 54 deletions
diff --git a/firmware/target/arm/crt0-pp-bl.S b/firmware/target/arm/crt0-pp-bl.S index 7ac6295305..9ab33a78d3 100644 --- a/firmware/target/arm/crt0-pp-bl.S +++ b/firmware/target/arm/crt0-pp-bl.S | |||
@@ -48,33 +48,34 @@ start: | |||
48 | .equ WAKE, 0x0 | 48 | .equ WAKE, 0x0 |
49 | .equ SLEEPING, 0x80000000 | 49 | .equ SLEEPING, 0x80000000 |
50 | .equ CACHE_CTRL, 0x6000c000 | 50 | .equ CACHE_CTRL, 0x6000c000 |
51 | .equ CACHE_ENAB, 0x1 | ||
51 | #endif | 52 | #endif |
52 | 53 | ||
53 | msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ */ | 54 | msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ */ |
54 | #ifndef E200R_INSTALLER | 55 | #ifndef E200R_INSTALLER |
55 | /* 1 - Copy the bootloader to IRAM */ | 56 | /* 1 - Copy the bootloader to IRAM */ |
56 | /* get the high part of our execute address */ | 57 | /* get the high part of our execute address */ |
57 | ldr r7, =0xffffff00 | 58 | bic r0, pc, #0xff /* r4 = pc & 0xffffff00 */ |
58 | and r4, pc, r7 | ||
59 | 59 | ||
60 | /* Copy bootloader to safe area - 0x40000000 (IRAM) */ | 60 | /* Copy bootloader to safe area - 0x40000000 (IRAM) */ |
61 | mov r5, #0x40000000 | 61 | mov r1, #0x40000000 |
62 | ldr r6, = _dataend | 62 | ldr r2, =_dataend |
63 | 1: | 63 | 1: |
64 | cmp r5, r6 | 64 | cmp r2, r1 |
65 | ldrcc r2, [r4], #4 | 65 | ldrhi r3, [r0], #4 |
66 | strcc r2, [r5], #4 | 66 | strhi r3, [r1], #4 |
67 | bcc 1b | 67 | bhi 1b |
68 | 68 | ||
69 | #ifndef IPOD_ARCH | 69 | #ifndef IPOD_ARCH |
70 | /* For builds on targets with mi4 firmware, scramble writes data to | 70 | /* For builds on targets with mi4 firmware, scramble writes data to |
71 | 0xe0-0xeb, so jump past that.*/ | 71 | 0xe0-0xeb, so jump past that. pad_skip must then exist at an |
72 | address >= 0xec */ | ||
72 | b pad_skip | 73 | b pad_skip |
73 | 74 | ||
74 | .space 60*4 | 75 | .space 60*4 |
75 | 76 | ||
76 | pad_skip: | 77 | pad_skip: |
77 | #endif | 78 | #endif /* IPOD_ARCH */ |
78 | 79 | ||
79 | 80 | ||
80 | /* 2 - Jump both CPU and COP there */ | 81 | /* 2 - Jump both CPU and COP there */ |
@@ -82,89 +83,92 @@ pad_skip: | |||
82 | #endif /* E200R_INSTALLER */ | 83 | #endif /* E200R_INSTALLER */ |
83 | 84 | ||
84 | start_loc: | 85 | start_loc: |
85 | |||
86 | /* Find out which processor we are */ | 86 | /* Find out which processor we are */ |
87 | ldr r0, =PROC_ID | 87 | ldr r0, =PROC_ID |
88 | ldr r0, [r0] | 88 | ldrb r0, [r0] |
89 | and r0, r0, #0xff | ||
90 | cmp r0, #0x55 | 89 | cmp r0, #0x55 |
91 | beq cpu | 90 | beq cpu |
92 | 91 | ||
92 | cop: | ||
93 | /* put us (co-processor) to sleep */ | 93 | /* put us (co-processor) to sleep */ |
94 | ldr r4, =COP_CTRL | 94 | ldr r0, =COP_CTRL |
95 | mov r3, #SLEEP | 95 | mov r1, #SLEEP |
96 | str r3, [r4] | 96 | str r1, [r0] |
97 | ldr pc, =cop_wake_start | 97 | |
98 | 98 | #ifdef CPU_PP502x | |
99 | cop_wake_start: | 99 | /* COP: Invalidate cache if enabled */ |
100 | #if CONFIG_CPU != PP5002 | 100 | ldr r2, =CACHE_CTRL |
101 | /* COP: Invalidate cache */ | 101 | ldr r1, [r2] |
102 | tst r1, #CACHE_ENAB | ||
103 | beq 2f | ||
102 | ldr r0, =0xf000f044 | 104 | ldr r0, =0xf000f044 |
103 | ldr r1, [r0] | 105 | ldr r1, [r0] |
104 | orr r1, r1, #0x6 | 106 | orr r1, r1, #0x6 |
105 | str r1, [r0] | 107 | str r1, [r0] |
106 | |||
107 | ldr r0, =CACHE_CTRL | ||
108 | 1: | 108 | 1: |
109 | ldr r1, [r0] | 109 | ldr r1, [r2] |
110 | tst r1, #0x8000 | 110 | tst r1, #0x8000 |
111 | bne 1b | 111 | bne 1b |
112 | #endif | 112 | 2: |
113 | #endif /* CPU_PP502x */ | ||
113 | 114 | ||
114 | ldr r0, =startup_loc | 115 | ldr r0, =startup_loc |
115 | ldr pc, [r0] | 116 | ldr pc, [r0] |
116 | 117 | ||
117 | cpu: | 118 | cpu: |
118 | /* Wait for COP to be sleeping */ | 119 | /* Wait for COP to be sleeping */ |
119 | ldr r4, =COP_STATUS | 120 | ldr r0, =COP_STATUS |
120 | 1: | 121 | 1: |
121 | ldr r3, [r4] | 122 | ldr r1, [r0] |
122 | ands r3, r3, #SLEEPING | 123 | tst r1, #SLEEPING |
123 | beq 1b | 124 | beq 1b |
124 | 125 | ||
125 | /* Initialise bss section to zero */ | 126 | /* Initialise bss section to zero */ |
126 | ldr r2, =_edata | 127 | ldr r0, =_edata |
127 | ldr r3, =_end | 128 | ldr r1, =_end |
128 | mov r4, #0 | 129 | mov r2, #0 |
129 | 1: | 130 | 1: |
130 | cmp r3, r2 | 131 | cmp r1, r0 |
131 | strhi r4, [r2], #4 | 132 | strhi r2, [r0], #4 |
132 | bhi 1b | 133 | bhi 1b |
133 | 134 | ||
134 | /* Set up some stack and munge it with 0xdeadbeef */ | 135 | /* Set up some stack and munge it with 0xdeadbeef */ |
135 | ldr sp, =stackend | 136 | ldr sp, =stackend |
136 | mov r3, sp | 137 | ldr r0, =stackbegin |
137 | ldr r2, =stackbegin | 138 | ldr r1, =0xdeadbeef |
138 | ldr r4, =0xdeadbeef | ||
139 | 1: | 139 | 1: |
140 | cmp r3, r2 | 140 | cmp sp, r0 |
141 | strhi r4, [r2], #4 | 141 | strhi r1, [r0], #4 |
142 | bhi 1b | 142 | bhi 1b |
143 | 143 | ||
144 | /* execute the loader - this will load an image to 0x10000000 */ | 144 | /* execute the loader - this will load an image to 0x10000000 */ |
145 | bl main | 145 | bl main |
146 | 146 | ||
147 | /* store actual startup location returned by main() */ | ||
147 | ldr r1, =startup_loc | 148 | ldr r1, =startup_loc |
148 | str r0, [r1] | 149 | str r0, [r1] |
149 | 150 | ||
150 | #if CONFIG_CPU != PP5002 | 151 | #ifdef CPU_PP502x |
151 | /* Flush cache */ | 152 | /* Flush cache if enabled */ |
152 | ldr r3, =0xf000f044 | 153 | ldr r2, =CACHE_CTRL |
153 | ldr r4, [r3] | 154 | ldr r1, [r2] |
154 | orr r4, r4, #0x2 | 155 | tst r1, #CACHE_ENAB |
155 | str r4, [r3] | 156 | beq 2f |
156 | 157 | ldr r0, =0xf000f044 | |
157 | ldr r3, =CACHE_CTRL | 158 | ldr r1, [r0] |
159 | orr r1, r1, #0x2 | ||
160 | str r1, [r0] | ||
158 | 1: | 161 | 1: |
159 | ldr r4, [r3] | 162 | ldr r1, [r2] |
160 | tst r4, #0x8000 | 163 | tst r1, #0x8000 |
161 | bne 1b | 164 | bne 1b |
162 | #endif | 165 | 2: |
166 | #endif /* CPU_PP502x */ | ||
163 | 167 | ||
164 | /* Wake up the coprocessor before executing the firmware */ | 168 | /* Wake up the coprocessor before executing the firmware */ |
165 | ldr r4, =COP_CTRL | 169 | ldr r0, =COP_CTRL |
166 | mov r3, #WAKE | 170 | mov r1, #WAKE |
167 | str r3, [r4] | 171 | str r1, [r0] |
168 | 172 | ||
169 | #ifdef SANSA_C200 | 173 | #ifdef SANSA_C200 |
170 | /* Magic for loading the c200 OF */ | 174 | /* Magic for loading the c200 OF */ |
@@ -184,6 +188,7 @@ startup_loc: | |||
184 | .align 8 /* starts at 0x100 */ | 188 | .align 8 /* starts at 0x100 */ |
185 | .global boot_table | 189 | .global boot_table |
186 | boot_table: | 190 | boot_table: |
187 | /* here comes the boot table, don't move its offset */ | 191 | /* here comes the boot table, don't move its offset - preceding |
192 | code+data must stay <= 256 bytes */ | ||
188 | .space 400 | 193 | .space 400 |
189 | #endif | 194 | #endif |