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Diffstat (limited to 'firmware/target/arm/as3525/system-as3525.c')
-rw-r--r--firmware/target/arm/as3525/system-as3525.c30
1 files changed, 27 insertions, 3 deletions
diff --git a/firmware/target/arm/as3525/system-as3525.c b/firmware/target/arm/as3525/system-as3525.c
index 2f320e91ab..60fe7032e6 100644
--- a/firmware/target/arm/as3525/system-as3525.c
+++ b/firmware/target/arm/as3525/system-as3525.c
@@ -28,6 +28,9 @@
28#include "clock-target.h" 28#include "clock-target.h"
29#include "fmradio_i2c.h" 29#include "fmradio_i2c.h"
30#include "button-target.h" 30#include "button-target.h"
31#ifndef BOOTLOADER
32#include "mmu-arm.h"
33#endif
31 34
32#define default_interrupt(name) \ 35#define default_interrupt(name) \
33 extern __attribute__((weak,alias("UIRQ"))) void name (void) 36 extern __attribute__((weak,alias("UIRQ"))) void name (void)
@@ -214,6 +217,26 @@ static void sdram_init(void)
214 217
215 MPMC_DYNAMIC_CONFIG_0 |= (1<<19); /* buffer enable */ 218 MPMC_DYNAMIC_CONFIG_0 |= (1<<19); /* buffer enable */
216} 219}
220#else
221void memory_init(void)
222{
223 ttb_init();
224 /* map every region to itself, uncached */
225 map_section(0, 0, 4096, CACHE_NONE);
226
227 /* IRAM */
228 map_section(0, IRAM_ORIG, 1, CACHE_ALL);
229 map_section(0, UNCACHED_ADDR(IRAM_ORIG), 1, CACHE_NONE);
230
231 /* DRAM */
232 map_section(0x30000000, DRAM_ORIG, MEMORYSIZE, CACHE_ALL);
233 map_section(0x30000000, UNCACHED_ADDR(DRAM_ORIG), MEMORYSIZE, CACHE_NONE);
234
235 /* map 1st mbyte of DRAM at 0x0 to have exception vectors available */
236 map_section(0x30000000, 0, 1, CACHE_ALL);
237
238 enable_mmu();
239}
217#endif 240#endif
218 241
219void system_init(void) 242void system_init(void)
@@ -226,6 +249,9 @@ void system_init(void)
226 CCU_SRL = CCU_SRL_MAGIC_NUMBER; 249 CCU_SRL = CCU_SRL_MAGIC_NUMBER;
227 CCU_SRC = CCU_SRL = 0; 250 CCU_SRC = CCU_SRL = 0;
228 251
252 CCU_SCON = 1; /* AHB master's priority configuration :
253 TIC (Test Interface Controller) > DMA > USB > IDE > ARM */
254
229 CGU_PROC = 0; /* fclk 24 MHz */ 255 CGU_PROC = 0; /* fclk 24 MHz */
230 CGU_PERI &= ~0x7f; /* pclk 24 MHz */ 256 CGU_PERI &= ~0x7f; /* pclk 24 MHz */
231 257
@@ -244,10 +270,8 @@ void system_init(void)
244 270
245 asm volatile( 271 asm volatile(
246 "mov r0, #0 \n" 272 "mov r0, #0 \n"
247 "mcr p15, 0, r0, c7, c7 \n" /* invalidate icache & dcache */
248 "mrc p15, 0, r0, c1, c0 \n" /* control register */ 273 "mrc p15, 0, r0, c1, c0 \n" /* control register */
249 "bic r0, r0, #3<<30 \n" /* clears bus bits & sets fastbus */ 274 "bic r0, r0, #3<<30 \n" /* clears bus bits : sets fastbus */
250 "orr r0, r0, #1<<12 \n" /* enable icache */
251 "mcr p15, 0, r0, c1, c0 \n" 275 "mcr p15, 0, r0, c1, c0 \n"
252 : : : "r0" ); 276 : : : "r0" );
253 277