diff options
Diffstat (limited to 'firmware/target/arm/as3525/memory-init.S')
-rw-r--r-- | firmware/target/arm/as3525/memory-init.S | 167 |
1 files changed, 167 insertions, 0 deletions
diff --git a/firmware/target/arm/as3525/memory-init.S b/firmware/target/arm/as3525/memory-init.S new file mode 100644 index 0000000000..fbc11e5c56 --- /dev/null +++ b/firmware/target/arm/as3525/memory-init.S | |||
@@ -0,0 +1,167 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright © 2010 by Rafaël Carré | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #include "config.h" | ||
22 | #include "cpu.h" | ||
23 | |||
24 | #define CACHE_NONE 0 | ||
25 | #define CACHE_ALL 0x0C | ||
26 | #define UNCACHED_ADDR(a) (a + 0x10000000) | ||
27 | |||
28 | #if defined(SANSA_CLIP) || defined(SANSA_M200V4) || defined(SANSA_C200V2) | ||
29 | /* 16 bits external bus, low power SDRAM, 16 Mbits = 2 Mbytes */ | ||
30 | #define MEMORY_MODEL 0x21 | ||
31 | |||
32 | #elif defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_CLIPV2) \ | ||
33 | || defined(SANSA_CLIPPLUS) || defined(SANSA_FUZEV2) | ||
34 | /* 16 bits external bus, high performance SDRAM, 64 Mbits = 8 Mbytes */ | ||
35 | #define MEMORY_MODEL 0x5 | ||
36 | |||
37 | #else | ||
38 | #error "The external memory in your player is unknown" | ||
39 | #endif | ||
40 | |||
41 | .global memory_init | ||
42 | .text | ||
43 | |||
44 | memory_init: | ||
45 | |||
46 | #ifdef BOOTLOADER | ||
47 | |||
48 | ldr r2, =0xC80F0014 @ CGU_PERI | ||
49 | ldr r1, [r2] | ||
50 | orr r1, r1, #(CGU_EXTMEM_CLOCK_ENABLE|CGU_EXTMEMIF_CLOCK_ENABLE) | ||
51 | str r1, [r2] | ||
52 | |||
53 | ldr r3, =0xC6030000 @ MPMC_BASE | ||
54 | |||
55 | mov r2, #1 @ enable MPMC | ||
56 | str r2, [r3] @ MPMC_CONTROL | ||
57 | ldr r2, =0x183 @ SDRAM NOP, all clocks high | ||
58 | str r2, [r3, #0x20] @ MPMC_DYNAMIC_CONTROL | ||
59 | ldr r2, =0x103 @ SDRAM PALL, all clocks high | ||
60 | str r2, [r3, #0x20] @ MPMC_DYNAMIC_CONTROL | ||
61 | ldr r1, =0x138 @ 0x138 * 16 HCLK ticks between SDRAM refresh cycles | ||
62 | str r1, [r3, #0x24] @ MPMC_DYNAMIC_REFRESH | ||
63 | mov r2, #0 @ little endian, HCLK:MPMCCLKOUT[3:0] ratio = 1:1 | ||
64 | str r2, [r3, #8] @ MPMC_CONFIG | ||
65 | |||
66 | ldr r2, [r3, #0xfe8] @ MPMC_PERIPH_ID2 | ||
67 | tst r2, #0xf0 | ||
68 | movne r2, #1 @ command delayed, clock out not delayed | ||
69 | strne r2, [r3, #0x28] @ MPMC_DYNAMIC_READ_CONFIG | ||
70 | |||
71 | mov r1, #2 | ||
72 | mov r0, #5 | ||
73 | mov ip, #4 | ||
74 | mov r2, #0 | ||
75 | str r1, [r3, #0x30] @ tRP | ||
76 | str ip, [r3, #0x34] @ tRAS | ||
77 | str r0, [r3, #0x38] @ tSREX | ||
78 | str r2, [r3, #0x3c] @ tAPR | ||
79 | str ip, [r3, #0x40] @ tDAL | ||
80 | str r1, [r3, #0x44] @ tWR | ||
81 | str r0, [r3, #0x48] @ tRC | ||
82 | str r0, [r3, #0x4c] @ tRFC | ||
83 | str r0, [r3, #0x50] @ tXSR | ||
84 | str r1, [r3, #0x54] @ tRRD | ||
85 | str r1, [r3, #0x58] @ tMRD | ||
86 | mov ip, #(MEMORY_MODEL << 7) | ||
87 | str ip, [r3, #0x100] @ MPMC_DYNAMIC_CONFIG_CONFIG_0 | ||
88 | orr r1, r1, #(2<<8) @ CAS & RAS latency = 2 clock cycle | ||
89 | str r1, [r3, #0x104] @ MPMC_DYNAMIC_CONFIG_RASCAS_0 | ||
90 | |||
91 | str r2, [r3, #0x120] @ MPMC_DYNAMIC_CONFIG_CONFIG_1 | ||
92 | str r2, [r3, #0x124] @ MPMC_DYNAMIC_CONFIG_RASCAS_1 | ||
93 | str r2, [r3, #0x140] @ MPMC_DYNAMIC_CONFIG_CONFIG_2 | ||
94 | str r2, [r3, #0x144] @ MPMC_DYNAMIC_CONFIG_RASCAS_2 | ||
95 | str r2, [r3, #0x160] @ MPMC_DYNAMIC_CONFIG_CONFIG_3 | ||
96 | str r2, [r3, #0x164] @ MPMC_DYNAMIC_CONFIG_RASCAS_3 | ||
97 | |||
98 | mov r1, #0x82 @ SDRAM MODE, MPMCCLKOUT runs continuously | ||
99 | str r1, [r3, #0x20] @ MPMC_DYNAMIC_CONTROL | ||
100 | |||
101 | ldr r1, =DRAM_ORIG+(0x2300*MEM) | ||
102 | ldr r1, [r1] | ||
103 | |||
104 | str r2, [r3, #0x20] @ MPMC_DYNAMIC_CONTROL= SDRAM NORMAL, | ||
105 | @ MPMCCLKOUT stopped when SDRAM is idle | ||
106 | |||
107 | ldr r2, [r3, #0x100] @ MPMC_DYNAMIC_CONFIG_0 | ||
108 | orr r2, r2, #(1<<19) @ buffer enable | ||
109 | str r2, [r3, #0x100] | ||
110 | |||
111 | #endif /* BOOTLOADER */ | ||
112 | |||
113 | @ XXX: to avoid using the stack, we rely on the fact that: | ||
114 | @ - ttb_init | ||
115 | @ - map_section | ||
116 | @ - enable_mmu | ||
117 | @ do not modify ip (r12) | ||
118 | mov ip, lr | ||
119 | |||
120 | /* Setup MMU */ | ||
121 | |||
122 | bl ttb_init | ||
123 | |||
124 | mov r0, #0 @ physical address | ||
125 | mov r1, #0 @ virtual address | ||
126 | mov r2, #0x1000 @ size (all memory) | ||
127 | mov r3, #CACHE_NONE | ||
128 | bl map_section | ||
129 | |||
130 | mov r0, #0 @ physical address | ||
131 | ldr r1, =IRAM_ORIG @ virtual address | ||
132 | mov r2, #1 @ size : 1MB | ||
133 | mov r3, #CACHE_ALL | ||
134 | bl map_section | ||
135 | |||
136 | mov r0, #0 @ physical address | ||
137 | ldr r1, =UNCACHED_ADDR(IRAM_ORIG) @ virtual address | ||
138 | mov r2, #1 @ size : 1MB | ||
139 | mov r3, #CACHE_NONE | ||
140 | bl map_section | ||
141 | |||
142 | mov r0, #0x30000000 @ physical address | ||
143 | mov r1, #DRAM_ORIG @ virtual address | ||
144 | mov r2, #MEMORYSIZE @ size | ||
145 | mov r3, #CACHE_ALL | ||
146 | bl map_section | ||
147 | |||
148 | mov r0, #0x30000000 @ physical address | ||
149 | mov r1, #UNCACHED_ADDR(DRAM_ORIG) @ virtual address | ||
150 | mov r2, #MEMORYSIZE @ size | ||
151 | mov r3, #CACHE_NONE | ||
152 | bl map_section | ||
153 | |||
154 | /* map 1st mbyte of RAM at 0x0 to have exception vectors available */ | ||
155 | #ifdef BOOTLOADER | ||
156 | mov r0, #0x81000000 @ physical address | ||
157 | #else | ||
158 | mov r0, #0x30000000 @ physical address | ||
159 | #endif | ||
160 | mov r1, #0 @ virtual address | ||
161 | mov r2, #1 @ size | ||
162 | mov r3, #CACHE_ALL | ||
163 | bl map_section | ||
164 | |||
165 | bl enable_mmu | ||
166 | |||
167 | bx ip | ||