diff options
Diffstat (limited to 'firmware/target/arm/as3525/clock-target.h')
-rw-r--r-- | firmware/target/arm/as3525/clock-target.h | 22 |
1 files changed, 9 insertions, 13 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index 7c388ad6c9..97d6edb3d1 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h | |||
@@ -139,7 +139,6 @@ | |||
139 | #define AS3525_FCLK_POSTDIV (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), AS3525_FCLK_FREQ) - 1) /*div=1/(n+1)*/ | 139 | #define AS3525_FCLK_POSTDIV (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), AS3525_FCLK_FREQ) - 1) /*div=1/(n+1)*/ |
140 | 140 | ||
141 | #if CONFIG_CPU == AS3525v2 | 141 | #if CONFIG_CPU == AS3525v2 |
142 | /* On as3525v2 we change fclk by writing to CGU_PROC */ | ||
143 | #define AS3525_FCLK_POSTDIV_UNBOOSTED (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), CPUFREQ_NORMAL) - 1) /*div=1/(n+1) */ | 142 | #define AS3525_FCLK_POSTDIV_UNBOOSTED (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), CPUFREQ_NORMAL) - 1) /*div=1/(n+1) */ |
144 | /* Since pclk is based on fclk, we need to change CGU_PERI as well */ | 143 | /* Since pclk is based on fclk, we need to change CGU_PERI as well */ |
145 | #define AS3525_PCLK_DIV0_UNBOOSTED (CLK_DIV(CPUFREQ_NORMAL, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/ | 144 | #define AS3525_PCLK_DIV0_UNBOOSTED (CLK_DIV(CPUFREQ_NORMAL, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/ |
@@ -164,21 +163,18 @@ | |||
164 | 163 | ||
165 | /* PCLK */ | 164 | /* PCLK */ |
166 | 165 | ||
167 | /* Figure out if we need to use asynchronous bus */ | 166 | #if CONFIG_CPU == AS3525 |
168 | #if ((CONFIG_CPU == AS3525) && (AS3525_FCLK_FREQ % AS3525_PCLK_FREQ)) | ||
169 | #define ASYNCHRONOUS_BUS /* Boosted mode asynchronous */ | ||
170 | #endif | ||
171 | |||
172 | #ifdef ASYNCHRONOUS_BUS | ||
173 | #define AS3525_PCLK_SEL AS3525_CLK_PLLA /* PLLA input for asynchronous */ | ||
174 | #define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_PLLA_FREQ, AS3525_DRAM_FREQ) - 1)/*div=1/(n+1)*/ | ||
175 | #else /* ASYNCHRONOUS_BUS */ | ||
176 | #define AS3525_PCLK_SEL AS3525_CLK_FCLK /* Fclk input for synchronous */ | ||
177 | #define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_FCLK_FREQ, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/ | ||
178 | #endif /* ASYNCHRONOUS_BUS */ | ||
179 | 167 | ||
168 | #define AS3525_PCLK_SEL AS3525_CLK_PLLA | ||
180 | /*unable to use AS3525_PCLK_DIV1 != 0 successfuly so far*/ | 169 | /*unable to use AS3525_PCLK_DIV1 != 0 successfuly so far*/ |
181 | #define AS3525_PCLK_DIV1 (CLK_DIV(AS3525_DRAM_FREQ, AS3525_PCLK_FREQ) - 1)/* div = 1/(n+1)*/ | 170 | #define AS3525_PCLK_DIV1 (CLK_DIV(AS3525_DRAM_FREQ, AS3525_PCLK_FREQ) - 1)/* div = 1/(n+1)*/ |
171 | #define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_PLLA_FREQ, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/ | ||
172 | #else | ||
173 | |||
174 | #define AS3525_PCLK_SEL AS3525_CLK_FCLK | ||
175 | #define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_FCLK_FREQ, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/ | ||
176 | |||
177 | #endif /* CONFIG_CPU */ | ||
182 | 178 | ||
183 | /* PCLK as Source */ | 179 | /* PCLK as Source */ |
184 | #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/ | 180 | #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/ |