FS#11597 : decrease FCLK frequency when unboosted

FCLK is unused because we use fastbus clocking: CPU clock = PCLK
Base PCLK off PLLA and use the lowest frqeuency for FCLK (24MHz source,
maximum divider)
Save a bit of power, adjust Clipv1/e200v2/Fuzev1 current usage accordingly

Note: the power saving (in mA) is a bit less on e200v2/Fuzev1 than on Clipv1

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28000 a1c6a512-1295-4272-9138-f99709370657

1 files changed, 9 insertions, 13 deletions

diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h
index 7c388ad6c9..97d6edb3d1 100644
--- a/firmware/target/arm/as3525/clock-target.h
+++ b/firmware/target/arm/as3525/clock-target.h
@@ -139,7 +139,6 @@
 #define AS3525_FCLK_POSTDIV      (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), AS3525_FCLK_FREQ) - 1) /*div=1/(n+1)*/
 
 #if CONFIG_CPU == AS3525v2
-/* On as3525v2 we change fclk by writing to CGU_PROC */
 #define AS3525_FCLK_POSTDIV_UNBOOSTED      (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), CPUFREQ_NORMAL) - 1) /*div=1/(n+1) */
 /* Since pclk is based on fclk, we need to change CGU_PERI as well */
 #define AS3525_PCLK_DIV0_UNBOOSTED (CLK_DIV(CPUFREQ_NORMAL, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/
@@ -164,21 +163,18 @@
 
 /* PCLK */
 
-/* Figure out if we need to use asynchronous bus */
-#if ((CONFIG_CPU == AS3525) && (AS3525_FCLK_FREQ % AS3525_PCLK_FREQ))
-#define ASYNCHRONOUS_BUS                          /* Boosted mode asynchronous */
-#endif
-
-#ifdef ASYNCHRONOUS_BUS
-#define AS3525_PCLK_SEL          AS3525_CLK_PLLA    /* PLLA input for asynchronous */
-#define AS3525_PCLK_DIV0         (CLK_DIV(AS3525_PLLA_FREQ, AS3525_DRAM_FREQ) - 1)/*div=1/(n+1)*/
-#else /* ASYNCHRONOUS_BUS */
-#define AS3525_PCLK_SEL          AS3525_CLK_FCLK    /* Fclk input for synchronous */
-#define AS3525_PCLK_DIV0         (CLK_DIV(AS3525_FCLK_FREQ, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/
-#endif /* ASYNCHRONOUS_BUS */
+#if CONFIG_CPU == AS3525
 
+#define AS3525_PCLK_SEL          AS3525_CLK_PLLA
          /*unable to use AS3525_PCLK_DIV1 != 0 successfuly so far*/
 #define AS3525_PCLK_DIV1         (CLK_DIV(AS3525_DRAM_FREQ, AS3525_PCLK_FREQ) - 1)/* div = 1/(n+1)*/ 
+#define AS3525_PCLK_DIV0         (CLK_DIV(AS3525_PLLA_FREQ, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/
+#else
+
+#define AS3525_PCLK_SEL          AS3525_CLK_FCLK
+#define AS3525_PCLK_DIV0         (CLK_DIV(AS3525_FCLK_FREQ, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/
+
+#endif /* CONFIG_CPU */
 
    /* PCLK as Source */
   #define AS3525_DBOP_DIV        (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/