diff options
Diffstat (limited to 'firmware/target/arm/as3525/as3525-codec.c')
-rw-r--r-- | firmware/target/arm/as3525/as3525-codec.c | 130 |
1 files changed, 65 insertions, 65 deletions
diff --git a/firmware/target/arm/as3525/as3525-codec.c b/firmware/target/arm/as3525/as3525-codec.c index 1de2f49e1a..0bd49464fa 100644 --- a/firmware/target/arm/as3525/as3525-codec.c +++ b/firmware/target/arm/as3525/as3525-codec.c | |||
@@ -5,7 +5,7 @@ | |||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id: $ | 8 | * $Id$ |
9 | * | 9 | * |
10 | * Copyright (C) 2008 by Bertrik Sikken | 10 | * Copyright (C) 2008 by Bertrik Sikken |
11 | * | 11 | * |
@@ -40,93 +40,93 @@ | |||
40 | #include "as3525-codec.h" | 40 | #include "as3525-codec.h" |
41 | #include "as3525.h" | 41 | #include "as3525.h" |
42 | 42 | ||
43 | #define AUDIO_I2C_ADDR 0x46 | 43 | #define AUDIO_I2C_ADDR 0x46 |
44 | 44 | ||
45 | #define I2C2_DATA *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x00)) | 45 | #define I2C2_DATA *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x00)) |
46 | #define I2C2_SLAD0 *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x04)) | 46 | #define I2C2_SLAD0 *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x04)) |
47 | #define I2C2_CNTRL *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x0C)) | 47 | #define I2C2_CNTRL *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x0C)) |
48 | #define I2C2_DACNT *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x10)) | 48 | #define I2C2_DACNT *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x10)) |
49 | #define I2C2_CPSR0 *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x1C)) | 49 | #define I2C2_CPSR0 *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x1C)) |
50 | #define I2C2_CPSR1 *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x20)) | 50 | #define I2C2_CPSR1 *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x20)) |
51 | #define I2C2_IMR *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x24)) | 51 | #define I2C2_IMR *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x24)) |
52 | #define I2C2_RIS *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x28)) | 52 | #define I2C2_RIS *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x28)) |
53 | #define I2C2_MIS *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x2C)) | 53 | #define I2C2_MIS *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x2C)) |
54 | #define I2C2_SR *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x30)) | 54 | #define I2C2_SR *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x30)) |
55 | #define I2C2_INT_CLR *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x40)) | 55 | #define I2C2_INT_CLR *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x40)) |
56 | #define I2C2_SADDR *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x44)) | 56 | #define I2C2_SADDR *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x44)) |
57 | 57 | ||
58 | 58 | ||
59 | /* initialises the internal i2c bus and prepares for transfers to the codec */ | 59 | /* initialises the internal i2c bus and prepares for transfers to the codec */ |
60 | void as3525_codec_init(void) | 60 | void as3525_codec_init(void) |
61 | { | 61 | { |
62 | /* reset device */ | 62 | /* reset device */ |
63 | CCU_SRC = CCU_SRC_I2C_AUDIO_EN; | 63 | CCU_SRC = CCU_SRC_I2C_AUDIO_EN; |
64 | CCU_SRL = CCU_SRL_MAGIC_NUMBER; | 64 | CCU_SRL = CCU_SRL_MAGIC_NUMBER; |
65 | CCU_SRL = 0; | 65 | CCU_SRL = 0; |
66 | 66 | ||
67 | /* enable clock */ | 67 | /* enable clock */ |
68 | CGU_PERI |= CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE; | 68 | CGU_PERI |= CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE; |
69 | 69 | ||
70 | /* prescaler for i2c clock */ | 70 | /* prescaler for i2c clock */ |
71 | I2C2_CPSR0 = 60; /* 24 MHz / 400 kHz */ | 71 | I2C2_CPSR0 = 60; /* 24 MHz / 400 kHz */ |
72 | I2C2_CPSR1 = 0; /* MSB */ | 72 | I2C2_CPSR1 = 0; /* MSB */ |
73 | 73 | ||
74 | /* set i2c slave address of codec part */ | 74 | /* set i2c slave address of codec part */ |
75 | I2C2_SLAD0 = AUDIO_I2C_ADDR << 1; | 75 | I2C2_SLAD0 = AUDIO_I2C_ADDR << 1; |
76 | 76 | ||
77 | I2C2_CNTRL = 0x51; | 77 | I2C2_CNTRL = 0x51; |
78 | } | 78 | } |
79 | 79 | ||
80 | 80 | ||
81 | /* returns != 0 when busy */ | 81 | /* returns != 0 when busy */ |
82 | static int i2c_busy(void) | 82 | static int i2c_busy(void) |
83 | { | 83 | { |
84 | return (I2C2_SR & 1); | 84 | return (I2C2_SR & 1); |
85 | } | 85 | } |
86 | 86 | ||
87 | 87 | ||
88 | /* returns 0 on success, <0 otherwise */ | 88 | /* returns 0 on success, <0 otherwise */ |
89 | int as3525_codec_write(int index, int value) | 89 | int as3525_codec_write(int index, int value) |
90 | { | 90 | { |
91 | if (index == 0x21) { | 91 | if (index == 0x21) { |
92 | /* prevent setting of the LREG_CP_not bit */ | 92 | /* prevent setting of the LREG_CP_not bit */ |
93 | value &= ~(1 << 5); | 93 | value &= ~(1 << 5); |
94 | } | 94 | } |
95 | 95 | ||
96 | /* check if still busy */ | 96 | /* check if still busy */ |
97 | if (i2c_busy()) { | 97 | if (i2c_busy()) { |
98 | return -1; | 98 | return -1; |
99 | } | 99 | } |
100 | 100 | ||
101 | /* start transfer */ | 101 | /* start transfer */ |
102 | I2C2_SADDR = index; | 102 | I2C2_SADDR = index; |
103 | I2C2_CNTRL &= ~(1 << 1); | 103 | I2C2_CNTRL &= ~(1 << 1); |
104 | I2C2_DATA = value; | 104 | I2C2_DATA = value; |
105 | I2C2_DACNT = 1; | 105 | I2C2_DACNT = 1; |
106 | 106 | ||
107 | /* wait for transfer*/ | 107 | /* wait for transfer*/ |
108 | while (i2c_busy()); | 108 | while (i2c_busy()); |
109 | |||
110 | return 0; | ||
111 | } | ||
109 | 112 | ||
110 | return 0; | ||
111 | } | ||
112 | |||
113 | 113 | ||
114 | /* returns value read on success, <0 otherwise */ | 114 | /* returns value read on success, <0 otherwise */ |
115 | int as3525_codec_read(int index) | 115 | int as3525_codec_read(int index) |
116 | { | 116 | { |
117 | /* check if still busy */ | 117 | /* check if still busy */ |
118 | if (i2c_busy()) { | 118 | if (i2c_busy()) { |
119 | return -1; | 119 | return -1; |
120 | } | 120 | } |
121 | |||
122 | /* start transfer */ | ||
123 | I2C2_SADDR = index; | ||
124 | I2C2_CNTRL |= (1 << 1); | ||
125 | I2C2_DACNT = 1; | ||
121 | 126 | ||
122 | /* start transfer */ | 127 | /* wait for transfer*/ |
123 | I2C2_SADDR = index; | 128 | while (i2c_busy()); |
124 | I2C2_CNTRL |= (1 << 1); | ||
125 | I2C2_DACNT = 1; | ||
126 | 129 | ||
127 | /* wait for transfer*/ | 130 | return I2C2_DATA; |
128 | while (i2c_busy()); | 131 | } |
129 | |||
130 | return I2C2_DATA; | ||
131 | } | ||
132 | 132 | ||