diff options
Diffstat (limited to 'firmware/rolo.c')
-rw-r--r-- | firmware/rolo.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/firmware/rolo.c b/firmware/rolo.c index 1489a8e695..4ac730b7ef 100644 --- a/firmware/rolo.c +++ b/firmware/rolo.c | |||
@@ -50,10 +50,10 @@ void rolo_restart_cop(void) | |||
50 | { | 50 | { |
51 | /* Invalidate cache */ | 51 | /* Invalidate cache */ |
52 | outl(inl(0xf000f044) | 0x6, 0xf000f044); | 52 | outl(inl(0xf000f044) | 0x6, 0xf000f044); |
53 | while ((inl(0x6000c000) & 0x8000) != 0) {} | 53 | while ((CACHE_CTL & 0x8000) != 0) {} |
54 | 54 | ||
55 | /* Disable cache */ | 55 | /* Disable cache */ |
56 | outl(0x0, 0x6000C000); | 56 | CACHE_CTL = CACHE_DISABLE; |
57 | 57 | ||
58 | /* Wait while RoLo loads the image into SDRAM */ | 58 | /* Wait while RoLo loads the image into SDRAM */ |
59 | /* TODO: Accept checksum failure gracefully */ | 59 | /* TODO: Accept checksum failure gracefully */ |
@@ -115,10 +115,10 @@ void rolo_restart(const unsigned char* source, unsigned char* dest, | |||
115 | 115 | ||
116 | /* Flush cache */ | 116 | /* Flush cache */ |
117 | outl(inl(0xf000f044) | 0x2, 0xf000f044); | 117 | outl(inl(0xf000f044) | 0x2, 0xf000f044); |
118 | while ((inl(0x6000c000) & 0x8000) != 0) {} | 118 | while ((CACHE_CTL & 0x8000) != 0) {} |
119 | 119 | ||
120 | /* Disable cache */ | 120 | /* Disable cache */ |
121 | outl(0x0, 0x6000C000); | 121 | CACHE_CTL = CACHE_DISABLE; |
122 | 122 | ||
123 | /* Reset the memory mapping registers to zero */ | 123 | /* Reset the memory mapping registers to zero */ |
124 | for (i=0;i<8;i++) | 124 | for (i=0;i<8;i++) |