diff options
Diffstat (limited to 'firmware/pcm_record.c')
-rw-r--r-- | firmware/pcm_record.c | 40 |
1 files changed, 21 insertions, 19 deletions
diff --git a/firmware/pcm_record.c b/firmware/pcm_record.c index f97995df72..b1415fa235 100644 --- a/firmware/pcm_record.c +++ b/firmware/pcm_record.c | |||
@@ -80,10 +80,10 @@ static short peak_left, peak_right; | |||
80 | Total buffer size: 32 MB / 176 KB/s = 181s before writing to disk | 80 | Total buffer size: 32 MB / 176 KB/s = 181s before writing to disk |
81 | */ | 81 | */ |
82 | 82 | ||
83 | #define CHUNK_SIZE 8192 /* Multiple of 4 */ | 83 | #define CHUNK_SIZE 8192 /* Multiple of 4 */ |
84 | #define WRITE_THRESHOLD 250 /* (2 MB) Write when this many chunks (or less) until buffer full */ | 84 | #define WRITE_THRESHOLD 250 /* (2 MB) Write when this many chunks (or less) until buffer full */ |
85 | 85 | ||
86 | #define GET_CHUNK(x) (short*)(&rec_buffer[CHUNK_SIZE*(x)]) | 86 | #define GET_CHUNK(x) (short*)(&rec_buffer[CHUNK_SIZE*(x)]) |
87 | 87 | ||
88 | static unsigned int rec_buffer_offset; | 88 | static unsigned int rec_buffer_offset; |
89 | static unsigned char *rec_buffer; /* Circular recording buffer */ | 89 | static unsigned char *rec_buffer; /* Circular recording buffer */ |
@@ -305,34 +305,36 @@ void audio_set_recording_options(int frequency, int quality, | |||
305 | case 2: | 305 | case 2: |
306 | /* Int. when 6 samples in FIFO. PDIR2 source = ebu1RcvData */ | 306 | /* Int. when 6 samples in FIFO. PDIR2 source = ebu1RcvData */ |
307 | DATAINCONTROL = 0xc038; | 307 | DATAINCONTROL = 0xc038; |
308 | EBU1CONFIG = 0; /* Normal operation, source is EBU in 1 */ | 308 | EBU1CONFIG = (1 << 2); |
309 | /* We can't use the EBU clock to drive the IIS interface, so we | 309 | /* Input source is EBUin1, Feed-through to output for monitoring */ |
310 | * need to use the clock the UDA provides, which is 44.1kHz as of | 310 | uda1380_disable_recording(); |
311 | * now. This is the reason S/PDIF monitoring distorts for all other | ||
312 | * sample rates. Enable record to enable clock gen. | ||
313 | */ | ||
314 | uda1380_enable_recording(true); | ||
315 | break; | 311 | break; |
316 | #endif | 312 | #endif |
317 | } | 313 | } |
318 | 314 | ||
319 | sample_rate = frequency; | 315 | sample_rate = frequency; |
320 | 316 | ||
321 | #ifdef HAVE_SPDIF_IN | 317 | /* Monitoring: route the signals through the coldfire audio interface. */ |
322 | /* Turn on UDA based monitoring when UDA is used as input. */ | 318 | |
319 | IIS2CONFIG = 0x800; /* Reset before reprogram */ | ||
320 | #ifdef HAVE_SPDIF_IN | ||
323 | if (source == 2) { | 321 | if (source == 2) { |
324 | uda1380_set_monitor(false); | 322 | /* SCLK2 = Audioclk/4 (can't use EBUin clock), TXSRC = EBU1rcv, 64 bclk/wclk */ |
325 | IIS2CONFIG = 0x800; /* Reset before reprogram */ | 323 | IIS2CONFIG = (6 << 12) | (7 << 8) | (4 << 2); |
326 | /* SCLK follow IIS1 (UDA clock), TXSRC = EBU1rcv, 64 bclk/wclk */ | 324 | /* S/PDIF feed-through already configured */ |
327 | IIS2CONFIG = (8 << 12) | (7 << 8) | (4 << 2); | ||
328 | } | 325 | } |
329 | else | 326 | else |
330 | { | 327 | { |
331 | uda1380_set_monitor(true); | 328 | /* SCLK2 follow IIS1 (UDA clock), TXSRC = IIS1rcv, 64 bclk/wclk */ |
332 | IIS2CONFIG = 0x800; /* Stop the S/PDIF monitoring if it's active */ | 329 | IIS2CONFIG = (8 << 12) | (4 << 8) | (4 << 2); |
330 | |||
331 | EBU1CONFIG = 0x800; /* Reset before reprogram */ | ||
332 | /* SCLK2, TXSRC = IIS1recv, validity, normal operation */ | ||
333 | EBU1CONFIG = (7 << 12) | (4 << 8) | (1 << 5) | (5 << 2); | ||
333 | } | 334 | } |
334 | #else | 335 | #else |
335 | uda1380_set_monitor(true); | 336 | /* SCLK2 follow IIS1 (UDA clock), TXSRC = IIS1rcv, 64 bclk/wclk */ |
337 | IIS2CONFIG = (8 << 12) | (4 << 8) | (4 << 2); | ||
336 | #endif | 338 | #endif |
337 | } | 339 | } |
338 | 340 | ||