4 files changed, 60 insertions, 28 deletions

diff --git a/firmware/export/config-gigabeat-s.h b/firmware/export/config-gigabeat-s.h
index 09f5e18ecc..3fc226ae59 100644
--- a/firmware/export/config-gigabeat-s.h
+++ b/firmware/export/config-gigabeat-s.h
@@ -73,6 +73,8 @@
 #define HW_SAMPR_CAPS (SAMPR_CAP_88 | SAMPR_CAP_44 | SAMPR_CAP_22 | \
                        SAMPR_CAP_11)
 
+#define HAVE_HEADPHONE_DETECTION
+
 #ifndef SIMULATOR
 
 /* The LCD on a Gigabeat is 240x320 - it is portrait */
@@ -86,6 +88,9 @@
 /* Define the bitmask of serial interface modules (CSPI) used */
 #define SPI_MODULE_MASK (USE_CSPI2_MODULE)
 
+/* Define this if target has an additional number of threads specific to it */
+#define TARGET_EXTRA_THREADS 1
+
 /* Type of mobile power - check this out */
 #define BATTERY_CAPACITY_DEFAULT 2000 /* default battery capacity */
 #define BATTERY_CAPACITY_MIN 1500        /* min. capacity selectable */
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h
index 7dc2659b33..3e7abe344b 100755
--- a/firmware/export/imx31l.h
+++ b/firmware/export/imx31l.h
@@ -491,29 +491,37 @@
 #define EPITSR_OCIF                     (1 << 0)
 
 /* GPIO */
-#define GPIO1_DR                (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x00))
-#define GPIO1_GDIR              (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x04))
-#define GPIO1_PSR               (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x08))
-#define GPIO1_ICR1              (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x0C))
-#define GPIO1_ICR2              (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x10))
-#define GPIO1_IMR               (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x14))
-#define GPIO1_ISR               (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x18))
-
-#define GPIO2_DR                (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x00))
-#define GPIO2_GDIR              (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x04))
-#define GPIO2_PSR               (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x08))
-#define GPIO2_ICR1              (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x0C))
-#define GPIO2_ICR2              (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x10))
-#define GPIO2_IMR               (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x14))
-#define GPIO2_ISR               (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x18))
-
-#define GPIO3_DR                (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x00))
-#define GPIO3_GDIR              (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x04))
-#define GPIO3_PSR               (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x08))
-#define GPIO3_ICR1              (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x0C))
-#define GPIO3_ICR2              (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x10))
-#define GPIO3_IMR               (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x14))
-#define GPIO3_ISR               (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x18))
+#define GPIO_DR_I               0x00 /* Offset - 0x00 */
+#define GPIO_GDIR_I             0x01 /* Offset - 0x04 */
+#define GPIO_PSR_I              0x02 /* Offset - 0x08 */
+#define GPIO_ICR1_I             0x03 /* Offset - 0x0C */
+#define GPIO_ICR2_I             0x04 /* Offset - 0x10 */
+#define GPIO_IMR_I              0x05 /* Offset - 0x14 */
+#define GPIO_ISR_I              0x06 /* Offset - 0x18 */
+
+#define GPIO1_DR                (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_DR_I])
+#define GPIO1_GDIR              (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_GDIR_I])
+#define GPIO1_PSR               (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_PSR_I])
+#define GPIO1_ICR1              (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_ICR1_I])
+#define GPIO1_ICR2              (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_ICR2_I])
+#define GPIO1_IMR               (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_IMR_I])
+#define GPIO1_ISR               (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_ISR_I])
+
+#define GPIO2_DR                (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_DR_I])
+#define GPIO2_GDIR              (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_GDIR_I])
+#define GPIO2_PSR               (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_PSR_I])
+#define GPIO2_ICR1              (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_ICR1_I])
+#define GPIO2_ICR2              (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_ICR2_I])
+#define GPIO2_IMR               (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_IMR_I])
+#define GPIO2_ISR               (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_ISR_I])
+
+#define GPIO3_DR                (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_DR_I])
+#define GPIO3_GDIR              (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_GDIR_I])
+#define GPIO3_PSR               (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_PSR_I])
+#define GPIO3_ICR1              (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_ICR1_I])
+#define GPIO3_ICR2              (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_ICR2_I])
+#define GPIO3_IMR               (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_IMR_I])
+#define GPIO3_ISR               (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_ISR_I])
 
 /* CSPI */
 #define CSPI_RXDATA_I           0x00 /* Offset - 0x00  */
diff --git a/firmware/export/mc13783.h b/firmware/export/mc13783.h
index fe9ff74e33..264c0bac4f 100644
--- a/firmware/export/mc13783.h
+++ b/firmware/export/mc13783.h
@@ -88,12 +88,25 @@ enum mc13783_regs_enum
     MC13783_NUM_REGS,
 };
 
+/* INTERRUPT_STATUS1, INTERRUPT_MASK1, INTERRUPT_SENSE1 */
+#define MC13783_HSL         (1 << 0)
+#define MC13783_ON1B        (1 << 3)
+#define MC13783_ON2B        (1 << 4)
+
+/* POWER_CONTROL0 */
+#define MC13783_USEROFFSPI  (1 << 3)
+
+/* LED_CONTROL0 */
+#define MC13783_LEDEN       (1 << 0)
+
 void mc13783_init(void);
-void mc13783_set(unsigned address, uint32_t bits);
-void mc13783_clear(unsigned address, uint32_t bits);
+uint32_t mc13783_set(unsigned address, uint32_t bits);
+uint32_t mc13783_clear(unsigned address, uint32_t bits);
 int mc13783_write(unsigned address, uint32_t data);
 int mc13783_write_multiple(unsigned start, const uint32_t *buffer, int count);
+int mc13783_write_regset(const unsigned char *regs, const uint32_t *data, int count);
 uint32_t mc13783_read(unsigned address);
 int mc13783_read_multiple(unsigned start, uint32_t *buffer, int count);
+int mc13783_read_regset(const unsigned char *regs, uint32_t *buffer, int count);
 
 #endif /* _MC13783_H_ */
diff --git a/firmware/export/thread.h b/firmware/export/thread.h
index 8c2338715c..eea58975a1 100644
--- a/firmware/export/thread.h
+++ b/firmware/export/thread.h
@@ -62,15 +62,21 @@
 #if CONFIG_CODEC == SWCODEC
 
 #ifdef HAVE_RECORDING
-#define MAXTHREADS  18
+#define BASETHREADS  18
 #else
-#define MAXTHREADS  17
+#define BASETHREADS  17
 #endif
 
 #else
-#define MAXTHREADS  11
+#define BASETHREADS  11
 #endif /* CONFIG_CODE == * */
 
+#ifndef TARGET_EXTRA_THREADS
+#define TARGET_EXTRA_THREADS 0
+#endif
+
+#define MAXTHREADS (BASETHREADS+TARGET_EXTRA_THREADS)
+
 #define DEFAULT_STACK_SIZE 0x400 /* Bytes */
 
 #ifndef SIMULATOR