diff options
Diffstat (limited to 'firmware/export')
-rw-r--r-- | firmware/export/mas.h | 25 |
1 files changed, 19 insertions, 6 deletions
diff --git a/firmware/export/mas.h b/firmware/export/mas.h index 493ed6a63c..3cc9d3a34c 100644 --- a/firmware/export/mas.h +++ b/firmware/export/mas.h | |||
@@ -33,7 +33,8 @@ | |||
33 | #define MAS_ADR 0x3c | 33 | #define MAS_ADR 0x3c |
34 | #define MAS_DEV_WRITE (MAS_ADR | 0x00) | 34 | #define MAS_DEV_WRITE (MAS_ADR | 0x00) |
35 | #define MAS_DEV_READ (MAS_ADR | 0x01) | 35 | #define MAS_DEV_READ (MAS_ADR | 0x01) |
36 | #else | 36 | |
37 | #elif CONFIG_CODEC == MAS3507D | ||
37 | #define MAS_ADR 0x3a | 38 | #define MAS_ADR 0x3a |
38 | #define MAS_DEV_WRITE (MAS_ADR | 0x00) | 39 | #define MAS_DEV_WRITE (MAS_ADR | 0x00) |
39 | #define MAS_DEV_READ (MAS_ADR | 0x01) | 40 | #define MAS_DEV_READ (MAS_ADR | 0x01) |
@@ -48,7 +49,8 @@ | |||
48 | #define MAS_CONTROL 0x6a | 49 | #define MAS_CONTROL 0x6a |
49 | #define MAS_DCCF 0x76 | 50 | #define MAS_DCCF 0x76 |
50 | #define MAS_DCFR 0x77 | 51 | #define MAS_DCFR 0x77 |
51 | #else | 52 | |
53 | #elif CONFIG_CODEC == MAS3507D | ||
52 | #define MAS_DATA_WRITE 0x68 | 54 | #define MAS_DATA_WRITE 0x68 |
53 | #define MAS_DATA_READ 0x69 | 55 | #define MAS_DATA_READ 0x69 |
54 | #define MAS_CONTROL 0x6a | 56 | #define MAS_CONTROL 0x6a |
@@ -62,8 +64,6 @@ | |||
62 | #define MAS_REG_PIODATA 0xc8 | 64 | #define MAS_REG_PIODATA 0xc8 |
63 | #define MAS_REG_StartUpConfig 0xe6 | 65 | #define MAS_REG_StartUpConfig 0xe6 |
64 | #define MAS_REG_KPRESCALE 0xe7 | 66 | #define MAS_REG_KPRESCALE 0xe7 |
65 | #define MAS_REG_KBASS 0x6b | ||
66 | #define MAS_REG_KTREBLE 0x6f | ||
67 | #if (CONFIG_CODEC == MAS3587F) || (CONFIG_CODEC == MAS3539F) | 67 | #if (CONFIG_CODEC == MAS3587F) || (CONFIG_CODEC == MAS3539F) |
68 | #define MAS_REG_KMDB_SWITCH 0x21 | 68 | #define MAS_REG_KMDB_SWITCH 0x21 |
69 | #define MAS_REG_KMDB_STR 0x22 | 69 | #define MAS_REG_KMDB_STR 0x22 |
@@ -74,7 +74,15 @@ | |||
74 | #define MAS_REG_QPEAK_R 0x0b | 74 | #define MAS_REG_QPEAK_R 0x0b |
75 | #define MAS_REG_DQPEAK_L 0x0c | 75 | #define MAS_REG_DQPEAK_L 0x0c |
76 | #define MAS_REG_DQPEAK_R 0x0d | 76 | #define MAS_REG_DQPEAK_R 0x0d |
77 | #define MAS_REG_VOLUME_CONTROL 0x10 | ||
78 | #define MAS_REG_BALANCE 0x11 | ||
77 | #define MAS_REG_KAVC 0x12 | 79 | #define MAS_REG_KAVC 0x12 |
80 | #define MAS_REG_KBASS 0x14 | ||
81 | #define MAS_REG_KTREBLE 0x15 | ||
82 | |||
83 | #elif CONFIG_CODEC == MAS3507D | ||
84 | #define MAS_REG_KBASS 0x6b | ||
85 | #define MAS_REG_KTREBLE 0x6f | ||
78 | #endif | 86 | #endif |
79 | 87 | ||
80 | /* | 88 | /* |
@@ -90,7 +98,8 @@ | |||
90 | #define MAS_CMD_READ_D1_MEM 0xd0 | 98 | #define MAS_CMD_READ_D1_MEM 0xd0 |
91 | #define MAS_CMD_WRITE_D0_MEM 0xe0 | 99 | #define MAS_CMD_WRITE_D0_MEM 0xe0 |
92 | #define MAS_CMD_WRITE_D1_MEM 0xf0 | 100 | #define MAS_CMD_WRITE_D1_MEM 0xf0 |
93 | #else | 101 | |
102 | #elif CONFIG_CODEC == MAS3507D | ||
94 | #define MAS_CMD_READ_ANCILLARY 0x30 | 103 | #define MAS_CMD_READ_ANCILLARY 0x30 |
95 | #define MAS_CMD_WRITE_REG 0x90 | 104 | #define MAS_CMD_WRITE_REG 0x90 |
96 | #define MAS_CMD_WRITE_D0_MEM 0xa0 | 105 | #define MAS_CMD_WRITE_D0_MEM 0xa0 |
@@ -141,11 +150,15 @@ | |||
141 | #define MAS_D0_MPEG_STATUS_2 0xfd2 | 150 | #define MAS_D0_MPEG_STATUS_2 0xfd2 |
142 | #define MAS_D0_CRC_ERROR_COUNT 0xfd3 | 151 | #define MAS_D0_CRC_ERROR_COUNT 0xfd3 |
143 | 152 | ||
144 | #else /* MAS3507D */ | 153 | #elif CONFIG_CODEC == MAS3507D |
145 | #define MAS_D0_MPEG_FRAME_COUNT 0x300 | 154 | #define MAS_D0_MPEG_FRAME_COUNT 0x300 |
146 | #define MAS_D0_MPEG_STATUS_1 0x301 | 155 | #define MAS_D0_MPEG_STATUS_1 0x301 |
147 | #define MAS_D0_MPEG_STATUS_2 0x302 | 156 | #define MAS_D0_MPEG_STATUS_2 0x302 |
148 | #define MAS_D0_CRC_ERROR_COUNT 0x303 | 157 | #define MAS_D0_CRC_ERROR_COUNT 0x303 |
158 | #define MAS_D0_OUT_LL 0x7f8 | ||
159 | #define MAS_D0_OUT_LR 0x7f9 | ||
160 | #define MAS_D0_OUT_RL 0x7fa | ||
161 | #define MAS_D0_OUT_RR 0x7fb | ||
149 | 162 | ||
150 | #endif | 163 | #endif |
151 | 164 | ||