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Diffstat (limited to 'firmware/export/usb-designware.h')
-rw-r--r-- | firmware/export/usb-designware.h | 287 |
1 files changed, 287 insertions, 0 deletions
diff --git a/firmware/export/usb-designware.h b/firmware/export/usb-designware.h new file mode 100644 index 0000000000..428733b4f5 --- /dev/null +++ b/firmware/export/usb-designware.h | |||
@@ -0,0 +1,287 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2014 Michael Sparmann | ||
11 | * Copyright (C) 2014 by Marcin Bukat | ||
12 | * Copyright (C) 2016 by Cástor Muñoz | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __USB_DESIGNWARE_H__ | ||
24 | #define __USB_DESIGNWARE_H__ | ||
25 | |||
26 | #include <inttypes.h> | ||
27 | #include "config.h" | ||
28 | |||
29 | #ifndef REG32_PTR_T | ||
30 | #define REG32_PTR_T volatile uint32_t * | ||
31 | #endif | ||
32 | |||
33 | /* Global registers */ | ||
34 | #define DWC_GOTGCTL (*((REG32_PTR_T)(OTGBASE + 0x00))) | ||
35 | #define DWC_GOTGINT (*((REG32_PTR_T)(OTGBASE + 0x04))) | ||
36 | #define DWC_GAHBCFG (*((REG32_PTR_T)(OTGBASE + 0x08))) | ||
37 | #define PTXFELVL (1<<8) | ||
38 | #define TXFELVL (1<<7) | ||
39 | #define DMAEN (1<<5) | ||
40 | #define HBSTLEN(x) ((x)<<1) | ||
41 | #define HBSTLEN_SINGLE 0 | ||
42 | #define HBSTLEN_INCR 1 | ||
43 | #define HBSTLEN_INCR4 3 | ||
44 | #define HBSTLEN_INCR8 5 | ||
45 | #define HBSTLEN_INCR16 7 | ||
46 | #define GINT (1<<0) | ||
47 | |||
48 | #define DWC_GUSBCFG (*((REG32_PTR_T)(OTGBASE + 0x0c))) | ||
49 | #define FDMOD (1<<30) | ||
50 | #define TRDT(x) ((x)<<10) | ||
51 | #define DDRSEL (1<<7) | ||
52 | #define PHSEL (1<<6) | ||
53 | #define FSINTF (1<<5) | ||
54 | #define ULPI_UTMI_SEL (1<<4) | ||
55 | #define PHYIF16 (1<<3) | ||
56 | |||
57 | #define DWC_GRSTCTL (*((REG32_PTR_T)(OTGBASE + 0x10))) | ||
58 | #define AHBIDL (1<<31) | ||
59 | #define TXFNUM(x) ((x)<<6) | ||
60 | #define TXFFLSH (1<<5) | ||
61 | #define RXFFLSH (1<<4) | ||
62 | #define CSRST (1<<0) | ||
63 | |||
64 | #define DWC_GINTSTS (*((REG32_PTR_T)(OTGBASE + 0x14))) | ||
65 | #define WKUINT (1<<31) | ||
66 | #define SRQINT (1<<30) | ||
67 | #define DISCINT (1<<29) | ||
68 | #define CIDSCHG (1<<28) | ||
69 | #define PTXFE (1<<26) | ||
70 | #define HCINT (1<<25) | ||
71 | #define HPRTINT (1<<24) | ||
72 | #define FETSUSP (1<<22) | ||
73 | #define IPXFR (1<<21) | ||
74 | #define IISOIXFR (1<<20) | ||
75 | #define OEPINT (1<<19) | ||
76 | #define IEPINT (1<<18) | ||
77 | #define EPMIS (1<<17) | ||
78 | #define EOPF (1<<15) | ||
79 | #define ISOODPR (1<<14) | ||
80 | #define ENUMDNE (1<<13) | ||
81 | #define USBRST (1<<12) | ||
82 | #define USBSUSP (1<<11) | ||
83 | #define ESUSP (1<<10) | ||
84 | #define GOUTNAKEFF (1<<7) | ||
85 | #define GINAKEFF (1<<6) | ||
86 | #define NPTXFE (1<<5) | ||
87 | #define RXFLVL (1<<4) | ||
88 | #define SOF (1<<3) | ||
89 | #define OTGINT (1<<2) | ||
90 | #define MMIS (1<<1) | ||
91 | #define CMOD (1<<0) | ||
92 | |||
93 | #define DWC_GINTMSK (*((REG32_PTR_T)(OTGBASE + 0x18))) | ||
94 | #define DWC_GRXSTSR (*((REG32_PTR_T)(OTGBASE + 0x1c))) | ||
95 | #define DWC_GRXSTSP (*((REG32_PTR_T)(OTGBASE + 0x20))) | ||
96 | #define PKTSTS_GLOBALOUTNAK 1 | ||
97 | #define PKTSTS_OUTRX 2 | ||
98 | #define PKTSTS_HCHIN 2 | ||
99 | #define PKTSTS_OUTDONE 3 | ||
100 | #define PKTSTS_HCHIN_XFER_COMP 3 | ||
101 | #define PKTSTS_SETUPDONE 4 | ||
102 | #define PKTSTS_DATATOGGLEERR 5 | ||
103 | #define PKTSTS_SETUPRX 6 | ||
104 | #define PKTSTS_HCHHALTED 7 | ||
105 | |||
106 | #define DWC_GRXFSIZ (*((REG32_PTR_T)(OTGBASE + 0x24))) | ||
107 | #ifdef USB_DW_SHARED_FIFO | ||
108 | #define DWC_GNPTXFSIZ (*((REG32_PTR_T)(OTGBASE + 0x28))) | ||
109 | #else | ||
110 | #define DWC_TX0FSIZ (*((REG32_PTR_T)(OTGBASE + 0x28))) | ||
111 | #endif | ||
112 | #define DWC_GNPTXSTS (*((REG32_PTR_T)(OTGBASE + 0x2c))) | ||
113 | #define DWC_GI2CCTL (*((REG32_PTR_T)(OTGBASE + 0x30))) | ||
114 | /* reserved */ | ||
115 | #define DWC_GCCFG (*((REG32_PTR_T)(OTGBASE + 0x38))) | ||
116 | #define NOVBUSSENS (1<<21) | ||
117 | #define SOFOUTEN (1<<20) | ||
118 | #define VBUSBSEN (1<<19) | ||
119 | #define VBUSASEN (1<<18) | ||
120 | #define I2CPADEN (1<<17) | ||
121 | #define PWRDWN (1<<16) | ||
122 | |||
123 | #define DWC_CID (*((REG32_PTR_T)(OTGBASE + 0x3c))) | ||
124 | #define DWC_GSNPSID (*((REG32_PTR_T)(OTGBASE + 0x40))) | ||
125 | #define DWC_GHWCFG1 (*((REG32_PTR_T)(OTGBASE + 0x44))) | ||
126 | #define DWC_GHWCFG2 (*((REG32_PTR_T)(OTGBASE + 0x48))) | ||
127 | #define DWC_GHWCFG3 (*((REG32_PTR_T)(OTGBASE + 0x4c))) | ||
128 | #define DWC_GHWCFG4 (*((REG32_PTR_T)(OTGBASE + 0x50))) | ||
129 | #define DWC_GLPMCFG (*((REG32_PTR_T)(OTGBASE + 0x54))) | ||
130 | #define DWC_HPTXFSIZ (*((REG32_PTR_T)(OTGBASE + 0x100))) | ||
131 | #define DWC_DIEPTXF(x) (*((REG32_PTR_T)(OTGBASE + 0x104 + 4*(x)))) /*0..15*/ | ||
132 | |||
133 | /* Host mode registers */ | ||
134 | #define DWC_HCFG (*((REG32_PTR_T)(OTGBASE + 0x400))) | ||
135 | #define DWC_HFIR (*((REG32_PTR_T)(OTGBASE + 0x404))) | ||
136 | #define DWC_HFNUM (*((REG32_PTR_T)(OTGBASE + 0x408))) | ||
137 | /* reserved */ | ||
138 | #define DWC_HPTXSTS (*((REG32_PTR_T)(OTGBASE + 0x410))) | ||
139 | #define DWC_HAINT (*((REG32_PTR_T)(OTGBASE + 0x414))) | ||
140 | #define DWC_HAINTMSK (*((REG32_PTR_T)(OTGBASE + 0x418))) | ||
141 | #define DWC_HPRT (*((REG32_PTR_T)(OTGBASE + 0x440))) | ||
142 | #define DWC_HCCHAR(x) (*((REG32_PTR_T)(OTGBASE + 0x500 + 0x20*(x)))) | ||
143 | #define DWC_HCSPLT(x) (*((REG32_PTR_T)(OTGBASE + 0x504 + 0x20*(x)))) | ||
144 | #define DWC_HCINT(x) (*((REG32_PTR_T)(OTGBASE + 0x508 + 0x20*(x)))) | ||
145 | #define DWC_HCINTMSK(x) (*((REG32_PTR_T)(OTGBASE + 0x50c + 0x20*(x)))) | ||
146 | #define DWC_HCTSIZ(x) (*((REG32_PTR_T)(OTGBASE + 0x510 + 0x20*(x)))) | ||
147 | #define DWC_HCDMA(x) (*((REG32_PTR_T)(OTGBASE + 0x514 + 0x20*(x)))) | ||
148 | |||
149 | /* Device mode registers */ | ||
150 | #define DWC_DCFG (*((REG32_PTR_T)(OTGBASE + 0x800))) | ||
151 | #define EPMISCNT(x) ((x)<<18) | ||
152 | #define DAD(x) ((x)<<4) | ||
153 | #define NZLSOHSK (1<<2) | ||
154 | |||
155 | #define DWC_DCTL (*((REG32_PTR_T)(OTGBASE + 0x804))) | ||
156 | #define POPRGDNE (1<<11) | ||
157 | #define CGONAK (1<<10) | ||
158 | #define SGONAK (1<<9) | ||
159 | #define CGINAK (1<<8) | ||
160 | #define SGINAK (1<<7) | ||
161 | #define TCTL(x) ((x)<<4) | ||
162 | #define GONSTS (1<<3) | ||
163 | #define GINSTS (1<<2) | ||
164 | #define SDIS (1<<1) | ||
165 | #define RWUSIG (1<<0) | ||
166 | |||
167 | #define DWC_DSTS (*((REG32_PTR_T)(OTGBASE + 0x808))) | ||
168 | /* reserved */ | ||
169 | #define DWC_DIEPMSK (*((REG32_PTR_T)(OTGBASE + 0x810))) | ||
170 | #define DWC_DOEPMSK (*((REG32_PTR_T)(OTGBASE + 0x814))) | ||
171 | #define DWC_DAINT (*((REG32_PTR_T)(OTGBASE + 0x818))) | ||
172 | #define DWC_DAINTMSK (*((REG32_PTR_T)(OTGBASE + 0x81c))) | ||
173 | /* reserved */ | ||
174 | #define DWC_DVBUSDIS (*((REG32_PTR_T)(OTGBASE + 0x828))) | ||
175 | #define DWC_DVBUSPULSE (*((REG32_PTR_T)(OTGBASE + 0x82c))) | ||
176 | |||
177 | #ifdef USB_DW_SHARED_FIFO | ||
178 | #define DWC_DTKNQR1 (*((REG32_PTR_T)(OTGBASE + 0x820))) | ||
179 | #define DWC_DTKNQR2 (*((REG32_PTR_T)(OTGBASE + 0x824))) | ||
180 | #define DWC_DTKNQR3 (*((REG32_PTR_T)(OTGBASE + 0x830))) | ||
181 | #define DWC_DTKNQR4 (*((REG32_PTR_T)(OTGBASE + 0x834))) | ||
182 | |||
183 | #else /* !USB_DW_SHARED_FIFO */ | ||
184 | #define DWC_DTHRCTL (*((REG32_PTR_T)(OTGBASE + 0x830))) | ||
185 | #define ARPEN (1<<27) | ||
186 | #define RXTHRLEN(x) ((x)<<17) | ||
187 | #define RXTHREN (1<<16) | ||
188 | #define TXTHRLEN(x) ((x)<<2) | ||
189 | #define ISOTHREN (1<<1) | ||
190 | #define NONISOTHREN (1<<0) | ||
191 | |||
192 | #define DWC_DIEPEMPMSK (*((REG32_PTR_T)(OTGBASE + 0x834))) | ||
193 | #define DWC_DEACHINT (*((REG32_PTR_T)(OTGBASE + 0x838))) | ||
194 | #define DWC_DEACHINTMSK (*((REG32_PTR_T)(OTGBASE + 0x83c))) | ||
195 | #define DWC_DIEPEACHMSK(x) (*((REG32_PTR_T)(OTGBASE + 0x840 + 4*(x)))) | ||
196 | #define DWC_DOEPEACHMSK(x) (*((REG32_PTR_T)(OTGBASE + 0x880 + 4*(x)))) | ||
197 | #endif | ||
198 | |||
199 | #define DWC_DIEPCTL(x) (*((REG32_PTR_T)(OTGBASE + 0x900 + 0x20*(x)))) | ||
200 | #define DWC_DOEPCTL(x) (*((REG32_PTR_T)(OTGBASE + 0xb00 + 0x20*(x)))) | ||
201 | #define EPENA (1<<31) | ||
202 | #define EPDIS (1<<30) | ||
203 | #define SD0PID (1<<28) | ||
204 | #define SNAK (1<<27) | ||
205 | #define CNAK (1<<26) | ||
206 | #define DTXFNUM(x) ((x)<<22) | ||
207 | #define STALL (1<<21) | ||
208 | #define EPTYP(x) ((x)<<18) | ||
209 | #define EPTYP_CONTROL 0 | ||
210 | #define EPTYP_ISOCHRONOUS 1 | ||
211 | #define EPTYP_BULK 2 | ||
212 | #define EPTYP_INTERRUPT 3 | ||
213 | #define NAKSTS (1<<17) | ||
214 | #define USBAEP (1<<15) | ||
215 | #define NEXTEP(x) ((x)<<11) | ||
216 | |||
217 | #define DWC_DIEPINT(x) (*((REG32_PTR_T)(OTGBASE + 0x908 + 0x20*(x)))) | ||
218 | #define DWC_DOEPINT(x) (*((REG32_PTR_T)(OTGBASE + 0xb08 + 0x20*(x)))) | ||
219 | #define TXFE (1<<7) /* IN */ | ||
220 | #define INEPNE (1<<6) /* IN */ | ||
221 | #define ITEPMIS (1<<5) /* IN */ | ||
222 | #define ITTXFE (1<<4) /* IN */ | ||
223 | #define OTEPDIS (1<<4) /* OUT */ | ||
224 | #define TOC (1<<3) /* control IN */ | ||
225 | #define STUP (1<<3) /* control OUT */ | ||
226 | #define AHBERR (1<<2) | ||
227 | #define EPDISD (1<<1) | ||
228 | #define XFRC (1<<0) | ||
229 | |||
230 | #define DWC_DIEPTSIZ(x) (*((REG32_PTR_T)(OTGBASE + 0x910 + 0x20*(x)))) | ||
231 | #define DWC_DOEPTSIZ(x) (*((REG32_PTR_T)(OTGBASE + 0xb10 + 0x20*(x)))) | ||
232 | #define MCCNT(x) ((x)<<29) /* IN */ | ||
233 | #define STUPCNT(x) ((x)<<29) /* control OUT */ | ||
234 | #define RXDPID(x) ((x)<<29) /* isochronous OUT */ | ||
235 | #define PKTCNT(x) ((x)<<19) | ||
236 | #define XFERSIZE(x) ((x)<<0) | ||
237 | |||
238 | #define DWC_DIEPDMA(x) (*((REG32_PTR_T)(OTGBASE + 0x914 + 0x20*(x)))) | ||
239 | #define DWC_DOEPDMA(x) (*((REG32_PTR_T)(OTGBASE + 0xb14 + 0x20*(x)))) | ||
240 | |||
241 | #define DWC_DTXFSTS(x) (*((REG32_PTR_T)(OTGBASE + 0x918 + 0x20*(x)))) | ||
242 | #define DWC_PCGCCTL (*((REG32_PTR_T)(OTGBASE + 0xe00))) | ||
243 | #define DWC_DFIFO(x) (*((REG32_PTR_T)(OTGBASE + 0x1000 + 0x1000*(x)))) | ||
244 | |||
245 | /* Device mode registers by (epnum,epdir), d==0 -> IN */ | ||
246 | #define DWC_EPCTL(n,d) (*((REG32_PTR_T)(OTGBASE + 0x900 + 0x200*(d) + 0x20*(n)))) | ||
247 | #define DWC_EPINT(n,d) (*((REG32_PTR_T)(OTGBASE + 0x908 + 0x200*(d) + 0x20*(n)))) | ||
248 | #define DWC_EPTSIZ(n,d) (*((REG32_PTR_T)(OTGBASE + 0x910 + 0x200*(d) + 0x20*(n)))) | ||
249 | #define DWC_EPDMA(n,d) (*((REG32_PTR_T)(OTGBASE + 0x914 + 0x200*(d) + 0x20*(n)))) | ||
250 | |||
251 | |||
252 | /* HS PHY/interface configuration */ | ||
253 | #define DWC_PHYTYPE_UTMI_8 (0) | ||
254 | #define DWC_PHYTYPE_UTMI_16 (PHYIF16) | ||
255 | #define DWC_PHYTYPE_ULPI_SDR (ULPI_UTMI_SEL) | ||
256 | #define DWC_PHYTYPE_ULPI_DDR (ULPI_UTMI_SEL|DDRSEL) | ||
257 | |||
258 | /* configure USB OTG capabilities on SoC */ | ||
259 | struct usb_dw_config | ||
260 | { | ||
261 | uint8_t phytype; /* DWC_PHYTYPE_ */ | ||
262 | |||
263 | uint16_t rx_fifosz; | ||
264 | uint16_t nptx_fifosz; | ||
265 | uint16_t ptx_fifosz; | ||
266 | #ifdef USB_DW_SHARED_FIFO | ||
267 | bool use_ptxfifo_as_plain_buffer; | ||
268 | #endif | ||
269 | #ifdef USB_DW_ARCH_SLAVE | ||
270 | bool disable_double_buffering; | ||
271 | #else | ||
272 | uint8_t ahb_burst_len; /* HBSTLEN_ */ | ||
273 | #ifndef USB_DW_SHARED_FIFO | ||
274 | uint8_t ahb_threshold; | ||
275 | #endif | ||
276 | #endif | ||
277 | }; | ||
278 | |||
279 | extern const struct usb_dw_config usb_dw_config; | ||
280 | |||
281 | extern void usb_dw_target_enable_clocks(void); | ||
282 | extern void usb_dw_target_disable_clocks(void); | ||
283 | extern void usb_dw_target_enable_irq(void); | ||
284 | extern void usb_dw_target_disable_irq(void); | ||
285 | extern void usb_dw_target_clear_irq(void); | ||
286 | |||
287 | #endif /* __USB_DESIGNWARE_H__ */ | ||