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diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h
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1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id: S5L8700X.h 2008-03-24 A4 $
9 *
10 * Copyright (C) 2008 by Bart van Adrichem
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20/* Copied from imx31l.h */
21#define REG8_PTR_T volatile unsigned char *
22#define REG16_PTR_T volatile unsigned short *
23#define REG32_PTR_T volatile unsigned long *
24
25/* Base Adresses chapter in datasheet
26*/
27#define ARM_BASE_ADDR 0x38000000
28#define MIU_BASE_ADDR 0x38200000 //07
29#define IODMA_BASE_ADDR 0x38400000 //08
30#define USB_H11_BASE_ADDR 0x38600000 //22
31#define USB_F20_BASE_ADDR 0x38800000 //21
32#define USB_H20_BASE_ADDR 0x38A00000
33#define ATA_BASE_ADDR 0x38E00000 //28
34#define ADM_BASE_ADDR 0x39000000 //04
35#define LCD_CTRL_BASE_ADDR 0x39200000 //27
36#define ICU_BASE_ADDR 0x39C00000 //06
37#define EEC_BASE_ADDR 0x39E00000 //16
38#define APB_BRIDGE_BASE_ADDR 0x3C000000
39#define LCD_IF_BASE_ADDR 0x3C100000 //26
40#define FMC_BASE_ADDR 0x3C200000 //12
41#define MMC_SD_BASE_ADDR 0x3C300000 //13
42#define USB_PHY_BASE_ADDR 0x3C400000 //23
43#define CLCK_GEN_BASE_ADDR 0x3C500000 //05
44#define MS_BASE_ADDR 0x3C600000 //14
45#define TIMER_BASE_ADDR 0x3C700000 //11
46#define WDT_BASE_ADDR 0x3C800000 //09
47#define IIC_BASE_ADDR 0x3C900000 //18
48#define IIS_BASE_ADDR 0x3CA00000 //17
49#define SPDIF_OUT_BASE_ADDR 0x3CB00000 //15
50#define UART0_BASE_ADDR 0x3CC00000 //25
51#define UART1_BASE_ADDR 0x3CC08000 //25
52#define SPI_BASE_ADDR 0x3CD00000 //19
53#define ADC_BASE_ADDR 0x3CE00000 //20
54#define GPIO_BASE_ADDR 0x3CF00000 //24
55#define CHIP_ID_BASE_ADDR 0x3D100000 //29
56#define RTC_BASE_ADDR 0x3D200000 //10
57
58
59/* 04. CALMADM2E */
60//Following registers are mapped on IO Area in data memory area of Calm.
61//TODO: not sure if the following list is correct concerning the 'h' added to the adresses in the datasheet
62//#DEFINE 7BIT OFFSET OR IS REG16_PTR_T CORRECT??
63#define CALM_BASE 0x3F0000 //7 BITS LONG
64#define CALM_CONFIG0 (*(REG16_PTR_T)(ADM_BASE_+0x00))
65#define CALM_CONFIG1 (*(REG16_PTR_T)(ADM_BASE_+0x02))
66#define CALM_COMMUN (*(REG16_PTR_T)(ADM_BASE_+0x04))
67#define CALM_DDATA0 (*(REG16_PTR_T)(ADM_BASE_+0x06))
68#define CALM_DDATA1 (*(REG16_PTR_T)(ADM_BASE_+0x08))
69#define CALM_DDATA2 (*(REG16_PTR_T)(ADM_BASE_+0x0A))
70#define CALM_DDATA3 (*(REG16_PTR_T)(ADM_BASE_+0x0C))
71#define CALM_DDATA4 (*(REG16_PTR_T)(ADM_BASE_+0x0E))
72#define CALM_DDATA5 (*(REG16_PTR_T)(ADM_BASE_+0x10))
73#define CALM_DDATA6 (*(REG16_PTR_T)(ADM_BASE_+0x12))
74#define CALM_DDATA7 (*(REG16_PTR_T)(ADM_BASE_+0x14))
75#define CALM_UDATA0 (*(REG16_PTR_T)(ADM_BASE_+0x16))
76#define CALM_UDATA1 (*(REG16_PTR_T)(ADM_BASE_+0x18))
77#define CALM_UDATA2 (*(REG16_PTR_T)(ADM_BASE_+0x1A))
78#define CALM_UDATA3 (*(REG16_PTR_T)(ADM_BASE_+0x1C))
79#define CALM_UDATA4 (*(REG16_PTR_T)(ADM_BASE_+0x1E))
80#define CALM_UDATA5 (*(REG16_PTR_T)(ADM_BASE_+0x20))
81#define CALM_UDATA6 (*(REG16_PTR_T)(ADM_BASE_+0x22))
82#define CALM_UDATA7 (*(REG16_PTR_T)(ADM_BASE_+0x24))
83#define CALM_IBASE_H (*(REG16_PTR_T)(ADM_BASE_+0x26))
84#define CALM_IBASE_L (*(REG16_PTR_T)(ADM_BASE_+0x28))
85#define CALM_DBASE_H (*(REG16_PTR_T)(ADM_BASE_+0x2A))
86#define CALM_DBASE_L (*(REG16_PTR_T)(ADM_BASE_+0x2C))
87#define CALM_XBASE_H (*(REG16_PTR_T)(ADM_BASE_+0x2E))
88#define CALM_XBASE_L (*(REG16_PTR_T)(ADM_BASE_+0x30))
89#define CALM_YBASE_H (*(REG16_PTR_T)(ADM_BASE_+0x32))
90#define CALM_YBASE_L (*(REG16_PTR_T)(ADM_BASE_+0x34))
91#define CALM_S0BASE_H (*(REG16_PTR_T)(ADM_BASE_+0x36))
92#define CALM_SOBASE_L (*(REG16_PTR_T)(ADM_BASE_+0x38))
93#define CALM_S1BASE_H (*(REG16_PTR_T)(ADM_BASE_+0x3A))
94#define CALM_S1BASE_L (*(REG16_PTR_T)(ADM_BASE_+0x3C))
95#define CALM_CACHECON (*(REG16_PTR_T)(ADM_BASE_+0x3E))
96#define CALM_CACHESTAT (*(REG16_PTR_T)(ADM_BASE_+0x40))
97#define CALM_SBFCON (*(REG16_PTR_T)(ADM_BASE_+0x42))
98#define CALM_SBFSTAT (*(REG16_PTR_T)(ADM_BASE_+0x44))
99#define CALM_SBL0OFF_H (*(REG16_PTR_T)(ADM_BASE_+0x46))
100#define CALM_SBL0OFF_L (*(REG16_PTR_T)(ADM_BASE_+0x48))
101#define CALM_SBL1OFF_H (*(REG16_PTR_T)(ADM_BASE_+0x4A))
102#define CALM_SBL1OFF_H (*(REG16_PTR_T)(ADM_BASE_+0x4C))
103#define CALM_SBL0BEGIN_H (*(REG16_PTR_T)(ADM_BASE_+0x4E))
104#define CALM_SBL0BEGIN_L (*(REG16_PTR_T)(ADM_BASE_+0x50))
105#define CALM_SBL1BEGIN_H (*(REG16_PTR_T)(ADM_BASE_+0x52))
106#define CALM_SBL1BEGIN_L (*(REG16_PTR_T)(ADM_BASE_+0x54))
107#define CALM_SBL0END_H (*(REG16_PTR_T)(ADM_BASE_+0x56))
108#define CALM_SBL0END_L (*(REG16_PTR_T)(ADM_BASE_+0x58))
109#define CALM_SBL0END_H (*(REG16_PTR_T)(ADM_BASE_+0x5A))
110#define CALM_SBL0END_L (*(REG16_PTR_T)(ADM_BASE_+0x5C))
111//Following registers are components of SFRS of the target system
112#define ADM_CONFIG (*(REG32_PTR_T)(ADM_BASE_ADDR+0x00))
113#define ADM_COMMUN (*(REG32_PTR_T)(ADM_BASE_ADDR+0x04))
114#define ADM_DDATA0 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x10))
115#define ADM_DDATA1 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x14))
116#define ADM_DDATA2 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x18))
117#define ADM_DDATA3 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x2C))
118#define ADM_DDATA4 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x20))
119#define ADM_DDATA5 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x24))
120#define ADM_DDATA6 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x28))
121#define ADM_DDATA7 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x2C))
122#define ADM_UDATA0 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x30))
123#define ADM_UDATA1 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x34))
124#define ADM_UDATA2 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x38))
125#define ADM_UDATA3 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x3C))
126#define ADM_UDATA4 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x40))
127#define ADM_UDATA5 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x44))
128#define ADM_UDATA6 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x48))
129#define ADM_UDATA7 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x4C))
130#define ADM_IBASE (*(REG32_PTR_T)(ADM_BASE_ADDR+0x50))
131#define ADM_DBASE (*(REG32_PTR_T)(ADM_BASE_ADDR+0x54))
132#define ADM_XBASE (*(REG32_PTR_T)(ADM_BASE_ADDR+0x58))
133#define ADM_YBASE (*(REG32_PTR_T)(ADM_BASE_ADDR+0x5C))
134#define ADM_S0BASE (*(REG32_PTR_T)(ADM_BASE_ADDR+0x60))
135#define ADM_S1BASE (*(REG32_PTR_T)(ADM_BASE_ADDR+0x64))
136
137/* 05. CLOCK & POWER MANAGEMENT */
138#define CLK_CON (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x00))
139#define PLL_CON (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x24))
140#define PLL0_PMS (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x04))
141#define PLL1_PMS (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x08))
142#define PLL0_CNT (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x14))
143#define PLL1_CNT (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x18))
144#define PLL_LOCK (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x20))
145#define PWR_CON (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x28))
146#define PWR_MODE (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x2C))
147#define SWR_CON (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x30))
148#define RST_SR (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x34))
149#define DSP_CLK_MD (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x38))
150#define CLK_CON (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x3C))
151
152/* 06. INTERRUPT CONTROLLER UNIT */
153#define ICU_SRC_PND (*(REG32_PTR_T)(ICU_BASE_ADDR+0x00))
154#define ICU_INT_MOD (*(REG32_PTR_T)(ICU_BASE_ADDR+0x04))
155#define ICU_INT_MSK (*(REG32_PTR_T)(ICU_BASE_ADDR+0x08))
156#define ICU_PRIORITY (*(REG32_PTR_T)(ICU_BASE_ADDR+0x0C))
157#define ICU_INT_PND (*(REG32_PTR_T)(ICU_BASE_ADDR+0x10))
158#define ICU_INT_OFFSET (*(REG32_PTR_T)(ICU_BASE_ADDR+0x14))
159#define ICU_EINT_POL (*(REG32_PTR_T)(ICU_BASE_ADDR+0x18))
160#define ICU_EINT_PEND (*(REG32_PTR_T)(ICU_BASE_ADDR+0x1C))
161#define ICU_EINT_MSK (*(REG32_PTR_T)(ICU_BASE_ADDR+0x20))
162
163/* 07. MEMORY INTERFACE UNIT (MIU) */
164#define MIU_CON (*(REG32_PTR_T)(MIU_BASE_ADDR+0x00))
165#define MIU_COM (*(REG32_PTR_T)(MIU_BASE_ADDR+0x04))
166#define MIU_AREF (*(REG32_PTR_T)(MIU_BASE_ADDR+0x08))
167#define MIU_MRS (*(REG32_PTR_T)(MIU_BASE_ADDR+0x0C))
168#define MIU_SDPARA (*(REG32_PTR_T)(MIU_BASE_ADDR+0x10))
169
170#define MIU_MEM_CONF (*(REG32_PTR_T)(MIU_BASE_ADDR+0x020H)) // 9 BIT ADRESS IN DATASHEET????????
171#define MIU_USR_CMD (*(REG32_PTR_T)(MIU_BASE_ADDR+0x024H))
172#define MIU_AREF (*(REG32_PTR_T)(MIU_BASE_ADDR+0x028H))
173#define MIU_MRS (*(REG32_PTR_T)(MIU_BASE_ADDR+0x02CH))
174#define MIU_DPARAM (*(REG32_PTR_T)(MIU_BASE_ADDR+0x030H))
175#define MIU_SMEM_CONF (*(REG32_PTR_T)(MIU_BASE_ADDR+0x034H))
176#define MIU_S01PARA (*(REG32_PTR_T)(MIU_BASE_ADDR+0x038H))
177#define MIU_S23PARA (*(REG32_PTR_T)(MIU_BASE_ADDR+0x03CH))
178/* TODO:
179#define MIU_ORG
180#define MIU_DLYDQS
181#define MIU_DLYCLK
182#define MIU_DSS_SEL_B
183#define MIU_DSS_SEL_O
184#define MIU_PAD_DSS_SEL_NOR
185#define MIU_PAD_DSS_SEL_ATA
186#define MIU_SSTL2_PAD_ON
187*/
188
189/* 08. IODMA CONTROLLER */
190#define DMA_BASE0 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x00))
191#define DMA_BASE1 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x20))
192#define DMA_BASE2 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x40))
193#define DMA_BASE3 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x60))
194#define DMA_CNT0 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x08))
195#define DMA_CNT1 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x28))
196#define DMA_CNT2 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x48))
197#define DMA_CNT3 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x68))
198#define DMA_CADDR0 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x0C))
199#define DMA_CADDR1 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x2C))
200#define DMA_CADDR2 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x4C))
201#define DMA_CADDR3 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x6C))
202#define DMA_CON0 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x04))
203#define DMA_CON1 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x24))
204#define DMA_CON2 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x44))
205#define DMA_CON3 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x64))
206#define DMA_CTCNT0 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x10))
207#define DMA_CTCNT1 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x30))
208#define DMA_CTCNT2 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x50))
209#define DMA_CTCNT3 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x70))
210#define DMA_COM0 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x14))
211#define DMA_COM1 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x34))
212#define DMA_COM2 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x54))
213#define DMA_COM3 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x74))
214#define DMA_OFF1 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x18))
215#define DMA_ALLST (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x0100))
216
217/* 10. REAL TIMER CLOCK (RTC) */
218#define RTC_CON (*(REG32_PTR_T)(RTC_BASE_ADDR+0x00))
219#define RTC_RST (*(REG32_PTR_T)(RTC_BASE_ADDR+0x04))
220#define RTC_ALM_CON (*(REG32_PTR_T)(RTC_BASE_ADDR+0x08))
221#define RTC_ALM_SEC (*(REG32_PTR_T)(RTC_BASE_ADDR+0x0C))
222#define RTC_ALM_MIN (*(REG32_PTR_T)(RTC_BASE_ADDR+0x10))
223#define RTC_ALM_HOUR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x14))
224#define RTC_ALM_DATE (*(REG32_PTR_T)(RTC_BASE_ADDR+0x18))
225#define RTC_ALM_DAY (*(REG32_PTR_T)(RTC_BASE_ADDR+0x1C))
226#define RTC_ALM_MON (*(REG32_PTR_T)(RTC_BASE_ADDR+0x20))
227#define RTC_AML_YEAR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x24))
228#define RTC_SEC (*(REG32_PTR_T)(RTC_BASE_ADDR+0x28))
229#define RTC_MIN (*(REG32_PTR_T)(RTC_BASE_ADDR+0x2C))
230#define RTC_HOUR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x30))
231#define RTC_DATE (*(REG32_PTR_T)(RTC_BASE_ADDR+0x34))
232#define RTC_DAY (*(REG32_PTR_T)(RTC_BASE_ADDR+0x38))
233#define RTC_MON (*(REG32_PTR_T)(RTC_BASE_ADDR+0x3C))
234#define RTC_YEAR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x40))
235#define RTC_IM (*(REG32_PTR_T)(RTC_BASE_ADDR+0x44))
236#define RTC_PEND (*(REG32_PTR_T)(RTC_BASE_ADDR+0x48))
237
238/* 09. WATCHDOG TIMER*/
239#define WDT_CON (*(REG32_PTR_T)(WDT_BASE_ADDR+0x00))
240#define WDT_CNT (*(REG32_PTR_T)(WDT_BASE_ADDR+0x04))
241
242/* 11. 16 BIT TIMER */
243#define TA_CON (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x00))
244#define TA_CMD (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x04))
245#define TA_DATA0 (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x08))
246#define TA_DATA1 (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x0C))
247#define TA_PRE (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x10))
248#define TA_CNT (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x14))
249#define TB_CON (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x20))
250#define TB_CMD (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x24))
251#define TB_DATA0 (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x28))
252#define TB_DATA1 (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x2C))
253#define TB_PRE (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x30))
254#define TB_CNT (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x34))
255#define TC_CON (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x40))
256#define TC_CMD (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x44))
257#define TC_DATA0 (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x48))
258#define TC_DATA1 (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x4C))
259#define TC_PRE (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x50))
260#define TC_CNT (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x54))
261#define TD_CON (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x60))
262#define TD_CMD (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x64))
263#define TD_DATA0 (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x68))
264#define TD_DATA1 (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x6C))
265#define TD_PRE (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x70))
266#define TD_CNT (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x74))
267
268/* 12. NAND FLASH CONTROLER */
269// TODO: FIFO
270#define FM_CTRL0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0000))
271#define FM_CTRL1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0004))
272#define FM_CMD (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0008))
273#define FM_ADR0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x000C))
274#define FM_ADR1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0010))
275#define FM_ADR2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0014))
276#define FM_ADR3 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0018))
277#define FM_ADR4 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x001C))
278#define FM_ADR5 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0020))
279#define FM_ADR6 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0024))
280#define FM_ADR7 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0028))
281#define FM_ANUM (*(REG32_PTR_T)(FMC_BASE_ADDR+0x002C))
282#define FM_DNUM (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0030))
283#define FM_DATAW0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0034))
284#define FM_DATAW1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0038))
285#define FM_DATAW2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x003C))
286#define FM_DATAW3 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0040))
287#define FM_CSTAT (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0048))
288#define FM_SYND0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x004C))
289#define FM_SYND1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0050))
290#define FM_SYND2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0054))
291#define FM_SYND3 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0058))
292#define FM_SYND4 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x005C))
293#define FM_SYND5 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0060))
294#define FM_SYND6 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0064))
295#define FM_SYND7 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0068))
296#define FM_FIFO (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0080)) // UNTILL (INCLUDING) 0x00FC <--
297#define RS_CTRL (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0100))
298#define RS_PAITY0-0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0110))
299#define RS_PAITY0-1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0114))
300#define RS_PAITY0-2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0118))
301#define RS_PAITY1-0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0120))
302#define RS_PAITY1-1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0124))
303#define RS_PAITY1-2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0128))
304#define RS_PAITY2-0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0130))
305#define RS_PAITY2-1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0134))
306#define RS_PAITY2-2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0138))
307#define RS_PAITY3-0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0140))
308#define RS_PAITY3-1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0144))
309#define RS_PAITY3-2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0148))
310#define RS_SYND0-0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0150))
311#define RS_SYND0-1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0154))
312#define RS_SYND0-2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0158))
313#define RS_SYND1-0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0160))
314#define RS_SYND1-1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0164))
315#define RS_SYND1-2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0168))
316#define RS_SYND2-0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0170))
317#define RS_SYND2-1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0174))
318#define RS_SYND2-2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0178))
319#define RS_SYND3-0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0180))
320#define RS_SYND3-1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0184))
321#define RS_SYND3-2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0188))
322#define FLAG_SYND (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0190))
323
324/* 13. SECURE DIGITAL CARD INTERFACE (SDCI) */
325// TODO
326
327/* 14. MEMORY STICK HOST CONTROLLER */
328//TODO
329
330/* 15. SPDIF TRANSMITTER (SPDIFOUT) */
331#define SPD_CLKCON (*(REG32_PTR_T)(SPDIF_OUT_BASE_ADDR+0x00))
332#define SPD_CON (*(REG32_PTR_T)(SPDIF_OUT_BASE_ADDR+0x04))
333#define SPD_BSTAS (*(REG32_PTR_T)(SPDIF_OUT_BASE_ADDR+0x08))
334#define SPD_CSTAS (*(REG32_PTR_T)(SPDIF_OUT_BASE_ADDR+0x0C))
335#define SPD_DAT (*(REG32_PTR_T)(SPDIF_OUT_BASE_ADDR+0x10))
336#define SPD_CNT (*(REG32_PTR_T)(SPDIF_OUT_BASE_ADDR+0x14))
337
338/* 16. REED-SOLOMON ECC CODEC */
339//TODO
340
341/* 17. IIS Tx/Rx INTERFACE */
342#define I2S_CLK_CON (*(REG32_PTR_T)(IIS_BASE_ADDR+0x00))
343#define I2S_TX_CON (*(REG32_PTR_T)(IIS_BASE_ADDR+0x04))
344#define I2S_TX_COM (*(REG32_PTR_T)(IIS_BASE_ADDR+0x08))
345#define I2S_TX_DB (*(REG32_PTR_T)(IIS_BASE_ADDR+0x10))
346#define I2S_RX_CON (*(REG32_PTR_T)(IIS_BASE_ADDR+0x30))
347#define I2S_RX_COM (*(REG32_PTR_T)(IIS_BASE_ADDR+0x34))
348#define I2S_RX_DB (*(REG32_PTR_T)(IIS_BASE_ADDR+0x38))
349#define I2S_STATUS (*(REG32_PTR_T)(IIS_BASE_ADDR+0x3C))
350
351/* 18. IIC BUS INTERFACE */
352#define IIC_CON (*(REG32_PTR_T)(IIC_BASE_ADDR+0x00))
353#define IIC_STST (*(REG32_PTR_T)(IIC_BASE_ADDR+0x04))
354#define IIC_ADD (*(REG32_PTR_T)(IIC_BASE_ADDR+0x08))
355#define IIC_DS (*(REG32_PTR_T)(IIC_BASE_ADDR+0x0C))
356
357/* 19. SPI (SERIAL PERHIPERAL INTERFACE) */
358#define SP_CLK_CON (*(REG32_PTR_T)(SPI_BASE_ADDR+0x00))
359#define SP_CON (*(REG32_PTR_T)(SPI_BASE_ADDR+0x04))
360#define SP_STA (*(REG32_PTR_T)(SPI_BASE_ADDR+0x08))
361#define SP_PIN (*(REG32_PTR_T)(SPI_BASE_ADDR+0x0C))
362#define SP_TDAT (*(REG32_PTR_T)(SPI_BASE_ADDR+0x10))
363#define SP_RDAT (*(REG32_PTR_T)(SPI_BASE_ADDR+0x14))
364#define SP_PRE (*(REG32_PTR_T)(SPI_BASE_ADDR+0x18))
365
366/* 20. ADC CONTROLLER */
367#define ADC_CON (*(REG32_PTR_T)(ADC_BASE_ADDR+0x00))
368#define ADC_TSC (*(REG32_PTR_T)(ADC_BASE_ADDR+0x04))
369#define ADC_DLY (*(REG32_PTR_T)(ADC_BASE_ADDR+0x08))
370#define ADC_DAT0 (*(REG32_PTR_T)(ADC_BASE_ADDR+0x0C))
371#define ADC_DAT1 (*(REG32_PTR_T)(ADC_BASE_ADDR+0x10))
372#define ADC_UPDN (*(REG32_PTR_T)(ADC_BASE_ADDR+0x14))
373
374/* 21. USB 2.0 FUNCTION CONTROLER SPECIAL REGISTER */
375#define USB2_IN (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x00))
376#define USB2_EIR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x04))
377#define USB2_EIER (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x08))
378#define USB2_FAR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x0C))
379#define USB2_FNR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x10))
380#define USB2_EDR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x14))
381#define USB2_TR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x18))
382#define USB2_SSR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x1C))
383#define USB2_SCR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x20))
384#define USB2_EP0SR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x24))
385#define USB2_EP0CR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x28))
386#define USB2_EP0BR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x60))
387#define USB2_EP1BR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x64))
388#define USB2_EP2BR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x68))
389#define USB2_EP3BR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x6C))
390#define USB2_EP4BR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x70))
391#define USB2_EP5BR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x74))
392#define USB2_EP6BR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x78))
393#define USB2_ESR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x2C))
394#define USB2_ECR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x30))
395#define USB2_BRCR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x34))
396#define USB2_BSCR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x38))
397#define USB2_MPR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x3C))
398#define USB2_MCR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x40))
399#define USB2_MTCR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x44))
400#define USB2_MFCR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x48))
401#define USB2_MTTCR1 (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x4C))
402#define USB2_MTTCR2 (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x50))
403#define USB2_MICR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x84))
404#define USB2_MBAR1 (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x88))
405#define USB2_MBAR2 (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x8C))
406#define USB2_MCAR1 (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x94))
407#define USB2_MCAR2 (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x98))
408
409/* 22. USB 1.1 HOST CONTROLER SPECIAL REGISTER */
410#define HC_REV (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x00))
411#define HC_CON (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x04))
412#define HC_COMSTAT (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x08))
413#define HC_INTSTAT (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x0C))
414#define HC_INTEN (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x10))
415#define HC_INTDIS (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x14))
416#define HC_HCCA (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x18))
417#define HC_PCED (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x1C))
418#define HC_CHED (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x20))
419#define HC_CCED (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x24))
420#define HC_BHED (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x28))
421#define HC_BCED (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x2C))
422#define HC_DH (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x30))
423#define HC_FMI (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x34))
424#define HC_FMR (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x38))
425#define HC_FMNR (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x3C))
426#define HC_PS (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x40))
427#define HC_LSTRESH (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x44))
428#define HC_RHSECA (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x48))
429#define HC_RHDESB (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x4C))
430#define HC_STAT (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x50))
431#define HC_PSTAT (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x54))
432
433/* 23. USB 2.0 PHY CONTROL */
434#define PHY_CTRL (*(REG32_PTR_T)(USB_PHY_BASE_ADDR+0x00))
435#define ULCK_CON (*(REG32_PTR_T)(USB_PHY_BASE_ADDR+0x04))
436#define URST_CON (*(REG32_PTR_T)(USB_PHY_BASE_ADDR+0x08))
437
438/* 24. GPIO PORT CONTROLL */
439#define GPIO_PCON0 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x00))
440#define GPIO_PDAT0 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x04))
441#define GPIO_PCON1 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x10))
442#define GPIO_PDAT1 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x14))
443#define GPIO_PCON2 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x20))
444#define GPIO_PDAT2 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x24))
445#define GPIO_PCON3 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x30))
446#define GPIO_PDAT3 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x34))
447#define GPIO_PCON4 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x40))
448#define GPIO_PDAT4 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x44))
449#define GPIO_PCON5 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x50))
450#define GPIO_PDAT5 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x54))
451#define GPIO_PCON6 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x60))
452#define GPIO_PDAT6 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x64))
453#define GPIO_PCON7 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x70))
454#define GPIO_PDAT7 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x74))
455#define GPIO_PCON10 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0xA0))
456#define GPIO_PDAT10 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0xA4))
457#define GPIO_PCON11 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0xF8))
458#define GPIO_PDAT11 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0xFC))
459#define GPIO_PCON_ASRAM (*(REG32_PTR_T)(GPIO_BASE_ADDR+0xF0))
460#define GPIO_PCON_SDRAM (*(REG32_PTR_T)(GPIO_BASE_ADDR+0xF4))
461
462/* 25. UART */
463#define UART0_LCON (*(REG32_PTR_T)(UART0_BASE_ADDR+0x00))
464#define UART0_CON (*(REG32_PTR_T)(UART0_BASE_ADDR+0x04))
465#define UART0_FCON (*(REG32_PTR_T)(UART0_BASE_ADDR+0x08))
466#define UART0_MCON (*(REG32_PTR_T)(UART0_BASE_ADDR+0x0C))
467#define UART0_TRSTAT (*(REG32_PTR_T)(UART0_BASE_ADDR+0x10))
468#define UART0_ERSTAT (*(REG32_PTR_T)(UART0_BASE_ADDR+0x14))
469#define UART0_FSTAT (*(REG32_PTR_T)(UART0_BASE_ADDR+0x18))
470#define UART0_MSTAT (*(REG32_PTR_T)(UART0_BASE_ADDR+0x1C))
471#define UART0_TXH (*(REG32_PTR_T)(UART0_BASE_ADDR+0x10))
472#define UART0_RXH (*(REG32_PTR_T)(UART0_BASE_ADDR+0x24))
473#define UART0_BRDIV (*(REG32_PTR_T)(UART0_BASE_ADDR+0x28))
474
475#define UART1_LCON (*(REG32_PTR_T)(UART1_BASE_ADDR+0x00))
476#define UART1_CON (*(REG32_PTR_T)(UART1_BASE_ADDR+0x04))
477#define UART1_FCON (*(REG32_PTR_T)(UART1_BASE_ADDR+0x08))
478#define UART1_MCON (*(REG32_PTR_T)(UART1_BASE_ADDR+0x0C))
479#define UART1_TRSTAT (*(REG32_PTR_T)(UART1_BASE_ADDR+0x10))
480#define UART1_ERSTAT (*(REG32_PTR_T)(UART1_BASE_ADDR+0x14))
481#define UART1_FSTAT (*(REG32_PTR_T)(UART1_BASE_ADDR+0x18))
482#define UART1_MSTAT (*(REG32_PTR_T)(UART1_BASE_ADDR+0x1C))
483#define UART1_TXH (*(REG32_PTR_T)(UART1_BASE_ADDR+0x10))
484#define UART1_RXH (*(REG32_PTR_T)(UART1_BASE_ADDR+0x24))
485#define UART1_BRDIV (*(REG32_PTR_T)(UART1_BASE_ADDR+0x28))
486
487/* 26. LCD INTERFACE CONTROLLER */
488// TODO: WDATA
489#define LCD_CON (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x00))
490#define LCD_WCMD (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x04))
491#define LCD_RCMD (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x0C))
492#define LCD_RDATA (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x10))
493#define LCD_DBUFF (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x14))
494#define LCD_INTCON (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x18))
495#define LCD_STATUS (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x1C))
496#define LCD_PHTIME (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x20))
497#define LCD_RST_TIME (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x24))
498#define LCD_DRV_RST (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x28))
499#define LCD_WDATA (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x40)) // UNTILL (INCLUDING) 0x5C <--
500
501/* 27. CLCD CONTROLLER */
502#define CLCD_CON1 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x00))
503#define CLCD_CON2 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x04))
504#define CLCD_TCON1 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x08))
505#define CLCD_TCON2 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x0C))
506#define CLCD_TCON3 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x10))
507#define CLCD_OSD1 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x14))
508#define CLCD_OSD2 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x18))
509#define CLCD_OSD3 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x1C))
510#define CLCD_B1SADDR1 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x20))
511#define CLCD_B2SADDR1 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x24))
512#define CLCD_F1SADDR1 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x28))
513#define CLCD_F2SADDR1 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x2C))
514#define CLCD_B1SADDR2 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x30))
515#define CLCD_B2SADDR2 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x34))
516#define CLCD_F1SADDR2 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x38))
517#define CLCD_F2SADDR2 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x3C))
518#define CLCD_B1SADDR3 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x40))
519#define CLCD_B2SADDR3 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x44))
520#define CLCD_F1SADDR3 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x48))
521#define CLCD_F2SADDR3 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x4C))
522#define CLCD_INTCON (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x50))
523#define CLCD_KEYCON (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x54))
524#define CLCD_KEYVAL (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x58))
525#define CLCD_BGCON (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x5C))
526#define CLCD_FGCON (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x60))
527#define CLCD_DITHCON (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x64))
528
529/* 28. ATA CONTROLLER */
530// TODO
531
532/* 29. CHIP ID */
533
534#define REG_ONE (*(REG32_PTR_T)(CHIP_ID_BASE_ADDR+0x00))
535#define REG_TWO (*(REG32_PTR_T)(CHIP_ID_BASE_ADDR+0x04))
536
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-05 00:52:13 +0000