diff options
Diffstat (limited to 'firmware/export/s5l8700.h')
-rw-r--r-- | firmware/export/s5l8700.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h index 420212ff3b..e8497ff337 100644 --- a/firmware/export/s5l8700.h +++ b/firmware/export/s5l8700.h | |||
@@ -118,6 +118,13 @@ | |||
118 | #define PLLLOCK (*(REG32_PTR_T)(0x3C500020)) /* PLL lock status register */ | 118 | #define PLLLOCK (*(REG32_PTR_T)(0x3C500020)) /* PLL lock status register */ |
119 | #define PLLCON (*(REG32_PTR_T)(0x3C500024)) /* PLL control register */ | 119 | #define PLLCON (*(REG32_PTR_T)(0x3C500024)) /* PLL control register */ |
120 | #define PWRCON (*(REG32_PTR_T)(0x3C500028)) /* Clock power control register */ | 120 | #define PWRCON (*(REG32_PTR_T)(0x3C500028)) /* Clock power control register */ |
121 | #if CONFIG_CPU==S5L8701 | ||
122 | #define CLOCKGATE_UARTC0 8 | ||
123 | #define CLOCKGATE_UARTC1 9 | ||
124 | #define CLOCKGATE_UARTC2 13 | ||
125 | #else /* S5L8700 */ | ||
126 | #define CLOCKGATE_UARTC 8 | ||
127 | #endif | ||
121 | #define PWRMODE (*(REG32_PTR_T)(0x3C50002C)) /* Power mode control register */ | 128 | #define PWRMODE (*(REG32_PTR_T)(0x3C50002C)) /* Power mode control register */ |
122 | #define SWRCON (*(REG32_PTR_T)(0x3C500030)) /* Software reset control register */ | 129 | #define SWRCON (*(REG32_PTR_T)(0x3C500030)) /* Software reset control register */ |
123 | #define RSTSR (*(REG32_PTR_T)(0x3C500034)) /* Reset status register */ | 130 | #define RSTSR (*(REG32_PTR_T)(0x3C500034)) /* Reset status register */ |
@@ -136,11 +143,16 @@ | |||
136 | #define INTMSK_TIMERD (1<<5) | 143 | #define INTMSK_TIMERD (1<<5) |
137 | #define INTMSK_ECC (1<<19) | 144 | #define INTMSK_ECC (1<<19) |
138 | #define INTMSK_USB_OTG (1<<16) | 145 | #define INTMSK_USB_OTG (1<<16) |
146 | #define INTMSK_UART0 (0) /* Unknown */ | ||
147 | #define INTMSK_UART1 (1<<12) | ||
148 | #define INTMSK_UART2 (1<<7) | ||
139 | #else | 149 | #else |
140 | #define INTMSK_TIMERA (1<<5) | 150 | #define INTMSK_TIMERA (1<<5) |
141 | #define INTMSK_TIMERB (1<<7) | 151 | #define INTMSK_TIMERB (1<<7) |
142 | #define INTMSK_TIMERC (1<<8) | 152 | #define INTMSK_TIMERC (1<<8) |
143 | #define INTMSK_TIMERD (1<<9) | 153 | #define INTMSK_TIMERD (1<<9) |
154 | #define INTMSK_UART0 (1<<22) | ||
155 | #define INTMSK_UART1 (1<<14) | ||
144 | #endif | 156 | #endif |
145 | #define PRIORITY (*(REG32_PTR_T)(0x39C0000C)) /* IRQ priority control register */ | 157 | #define PRIORITY (*(REG32_PTR_T)(0x39C0000C)) /* IRQ priority control register */ |
146 | #define INTPND (*(REG32_PTR_T)(0x39C00010)) /* Indicates the interrupt request status. */ | 158 | #define INTPND (*(REG32_PTR_T)(0x39C00010)) /* Indicates the interrupt request status. */ |
@@ -577,6 +589,29 @@ | |||
577 | #define PCON_SDRAM (*(REG32_PTR_T)(0x3CF000F4)) /* Configures the pins of port sdram */ | 589 | #define PCON_SDRAM (*(REG32_PTR_T)(0x3CF000F4)) /* Configures the pins of port sdram */ |
578 | 590 | ||
579 | /* 25. UART */ | 591 | /* 25. UART */ |
592 | #if CONFIG_CPU==S5L8701 | ||
593 | /* s5l8701 UC870X HW: 3 UARTC, 1 port per UARTC */ | ||
594 | #define S5L8701_N_UARTC 3 | ||
595 | #define S5L8701_N_PORTS 3 | ||
596 | |||
597 | #define UARTC0_BASE_ADDR 0x3CC00000 | ||
598 | #define UARTC0_N_PORTS 1 | ||
599 | #define UARTC0_PORT_OFFSET 0x0 | ||
600 | #define UARTC1_BASE_ADDR 0x3CC08000 | ||
601 | #define UARTC1_N_PORTS 1 | ||
602 | #define UARTC1_PORT_OFFSET 0x0 | ||
603 | #define UARTC2_BASE_ADDR 0x3CC0C000 | ||
604 | #define UARTC2_N_PORTS 1 | ||
605 | #define UARTC2_PORT_OFFSET 0x0 | ||
606 | |||
607 | #else | ||
608 | /* s5l8700 UC870X HW: 1 UARTC, 2 ports */ | ||
609 | #define S5L8700_N_UARTC 1 | ||
610 | #define S5L8700_N_PORTS 2 | ||
611 | |||
612 | #define UARTC_BASE_ADDR 0x3CC00000 | ||
613 | #define UARTC_N_PORTS 2 | ||
614 | #define UARTC_PORT_OFFSET 0x8000 | ||
580 | 615 | ||
581 | /* UART 0 */ | 616 | /* UART 0 */ |
582 | #define ULCON0 (*(REG32_PTR_T)(0x3CC00000)) /* Line Control Register */ | 617 | #define ULCON0 (*(REG32_PTR_T)(0x3CC00000)) /* Line Control Register */ |
@@ -603,6 +638,7 @@ | |||
603 | #define UTXH1 (*(REG32_PTR_T)(0x3CC08020)) /* Transmit Buffer Register */ | 638 | #define UTXH1 (*(REG32_PTR_T)(0x3CC08020)) /* Transmit Buffer Register */ |
604 | #define URXH1 (*(REG32_PTR_T)(0x3CC08024)) /* Receive Buffer Register */ | 639 | #define URXH1 (*(REG32_PTR_T)(0x3CC08024)) /* Receive Buffer Register */ |
605 | #define UBRDIV1 (*(REG32_PTR_T)(0x3CC08028)) /* Baud Rate Divisor Register */ | 640 | #define UBRDIV1 (*(REG32_PTR_T)(0x3CC08028)) /* Baud Rate Divisor Register */ |
641 | #endif | ||
606 | 642 | ||
607 | /* 26. LCD INTERFACE CONTROLLER */ | 643 | /* 26. LCD INTERFACE CONTROLLER */ |
608 | #if CONFIG_CPU==S5L8700 | 644 | #if CONFIG_CPU==S5L8700 |