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Diffstat (limited to 'firmware/export/s5l8700.h')
-rw-r--r--firmware/export/s5l8700.h26
1 files changed, 26 insertions, 0 deletions
diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h
index f652a62a2e..f9e015baff 100644
--- a/firmware/export/s5l8700.h
+++ b/firmware/export/s5l8700.h
@@ -120,6 +120,7 @@
120#define RSTSR (*(REG32_PTR_T)(0x3C500034)) /* Reset status register */ 120#define RSTSR (*(REG32_PTR_T)(0x3C500034)) /* Reset status register */
121#define DSPCLKMD (*(REG32_PTR_T)(0x3C500038)) /* DSP clock mode register */ 121#define DSPCLKMD (*(REG32_PTR_T)(0x3C500038)) /* DSP clock mode register */
122#define CLKCON2 (*(REG32_PTR_T)(0x3C50003C)) /* clock control register 2 */ 122#define CLKCON2 (*(REG32_PTR_T)(0x3C50003C)) /* clock control register 2 */
123#define PWRCONEXT (*(REG32_PTR_T)(0x3C500040))
123 124
124/* 06. INTERRUPT CONTROLLER UNIT */ 125/* 06. INTERRUPT CONTROLLER UNIT */
125#define SRCPND (*(REG32_PTR_T)(0x39C00000)) /* Indicates the interrupt request status. */ 126#define SRCPND (*(REG32_PTR_T)(0x39C00000)) /* Indicates the interrupt request status. */
@@ -670,3 +671,28 @@
670#define REG_ONE (*(REG32_PTR_T)(0x3D100000)) /* Receive the first 32 bits from a fuse box */ 671#define REG_ONE (*(REG32_PTR_T)(0x3D100000)) /* Receive the first 32 bits from a fuse box */
671#define REG_TWO (*(REG32_PTR_T)(0x3D100004)) /* Receive the other 8 bits from a fuse box */ 672#define REG_TWO (*(REG32_PTR_T)(0x3D100004)) /* Receive the other 8 bits from a fuse box */
672 673
674
675/* Hardware AES crypto unit - S5L8701 only */
676#if CONFIG_CPU==S5L8701
677
678#define ICONSRCPND (*(REG32_PTR_T)(0x39C00000))
679#define ICONINTPND (*(REG32_PTR_T)(0x39C00010))
680#define AESCONTROL (*(REG32_PTR_T)(0x39800000))
681#define AESGO (*(REG32_PTR_T)(0x39800004))
682#define AESUNKREG0 (*(REG32_PTR_T)(0x39800008))
683#define AESSTATUS (*(REG32_PTR_T)(0x3980000C))
684#define AESUNKREG1 (*(REG32_PTR_T)(0x39800010))
685#define AESKEYLEN (*(REG32_PTR_T)(0x39800014))
686#define AESOUTSIZE (*(REG32_PTR_T)(0x39800018))
687#define AESOUTADDR (*(REG32_PTR_T)(0x39800020))
688#define AESINSIZE (*(REG32_PTR_T)(0x39800024))
689#define AESINADDR (*(REG32_PTR_T)(0x39800028))
690#define AESAUXSIZE (*(REG32_PTR_T)(0x3980002C))
691#define AESAUXADDR (*(REG32_PTR_T)(0x39800030))
692#define AESSIZE3 (*(REG32_PTR_T)(0x39800034))
693#define AESTYPE (*(REG32_PTR_T)(0x3980006C))
694#define HASHCTRL (*(REG32_PTR_T)(0x3C600000))
695#define HASHRESULT ((REG32_PTR_T)(0x3C600020))
696#define HASHDATAIN ((REG32_PTR_T)(0x3C600040))
697
698#endif /* CONFIG_CPU==S5L8701 */