summaryrefslogtreecommitdiff
path: root/firmware/export/pp5020.h
diff options
context:
space:
mode:
Diffstat (limited to 'firmware/export/pp5020.h')
-rw-r--r--firmware/export/pp5020.h113
1 files changed, 68 insertions, 45 deletions
diff --git a/firmware/export/pp5020.h b/firmware/export/pp5020.h
index 60d14491e0..ade1f138a0 100644
--- a/firmware/export/pp5020.h
+++ b/firmware/export/pp5020.h
@@ -20,11 +20,72 @@
20#define __PP5020_H__ 20#define __PP5020_H__
21 21
22/* All info gleaned and/or copied from the iPodLinux project. */ 22/* All info gleaned and/or copied from the iPodLinux project. */
23
24/* DRAM starts at 0x10000000, but in Rockbox we remap it to 0x00000000 */
23#define DRAM_START 0x10000000 25#define DRAM_START 0x10000000
24 26
27/* Processor ID */
28#define PROCESSOR_ID (*(volatile unsigned long *)(0x60000000))
29
30#define PROC_ID_CPU 0x55
31#define PROC_ID_COP 0xaa
32
33/* Interrupts */
34#define CPU_INT_EN (*(volatile unsigned long*)(0x60004024))
35#define CPU_HI_INT_EN (*(volatile unsigned long*)(0x60004124))
36#define CPU_INT_CLR (*(volatile unsigned long*)(0x60004028))
37#define CPU_HI_INT_CLR (*(volatile unsigned long*)(0x60004128))
38#define CPU_INT_STAT (*(volatile unsigned long*)(0x64004000))
39#define CPU_HI_INT_STAT (*(volatile unsigned long*)(0x64004100))
40
41#define TIMER1_IRQ 0
42#define TIMER2_IRQ 1
43#define I2S_IRQ 10
44#define IDE_IRQ 23
45#define GPIO_IRQ (32+0)
46#define SER0_IRQ (32+4)
47#define SER1_IRQ (32+5)
48#define I2C_IRQ (32+8)
49
50#define TIMER1_MASK (1 << TIMER1_IRQ)
51#define TIMER2_MASK (1 << TIMER2_IRQ)
52#define I2S_MASK (1 << I2S_IRQ)
53#define IDE_MASK (1 << IDE_IRQ)
54#define GPIO_MASK (1 << (GPIO_IRQ-32))
55#define SER0_MASK (1 << (SER0_IRQ-32))
56#define SER1_MASK (1 << (SER1_IRQ-32))
57#define I2C_MASK (1 << (I2C_IRQ-32))
58
59/* Timers */
60#define TIMER1_CFG (*(volatile unsigned long *)(0x60005000))
61#define TIMER1_VAL (*(volatile unsigned long *)(0x60005004))
62#define TIMER2_CFG (*(volatile unsigned long *)(0x60005008))
63#define TIMER2_VAL (*(volatile unsigned long *)(0x6000500c))
64#define USEC_TIMER (*(volatile unsigned long *)(0x60005010))
65
66/* Device Controller */
67#define DEV_RS (*(volatile unsigned long *)(0x60006004))
68#define DEV_EN (*(volatile unsigned long *)(0x6000600c))
69
70#define DEV_SYSTEM 0x4
71#define DEV_I2C 0x1000
72#define DEV_USB 0x400000
73
74/* Processors Control */
25#define CPU_CTL (*(volatile unsigned long *)(0x60007000)) 75#define CPU_CTL (*(volatile unsigned long *)(0x60007000))
26#define COP_CTL (*(volatile unsigned long *)(0x60007004)) 76#define COP_CTL (*(volatile unsigned long *)(0x60007004))
27 77
78#define PROC_SLEEP 0x80000000
79#define PROC_WAKE 0x0
80
81/* Cache Control */
82#define CACHE_CTL (*(volatile unsigned long *)(0x6000c000))
83
84#define CACHE_DISABLE 0
85#define CACHE_ENABLE 1
86#define CACHE_INIT 4
87
88/* GPIO Ports */
28#define GPIOA_ENABLE (*(volatile unsigned long *)(0x6000d000)) 89#define GPIOA_ENABLE (*(volatile unsigned long *)(0x6000d000))
29#define GPIOB_ENABLE (*(volatile unsigned long *)(0x6000d004)) 90#define GPIOB_ENABLE (*(volatile unsigned long *)(0x6000d004))
30#define GPIOC_ENABLE (*(volatile unsigned long *)(0x6000d008)) 91#define GPIOC_ENABLE (*(volatile unsigned long *)(0x6000d008))
@@ -124,56 +185,24 @@
124#define GPIOK_INT_CLR (*(volatile unsigned long *)(0x6000d178)) 185#define GPIOK_INT_CLR (*(volatile unsigned long *)(0x6000d178))
125#define GPIOL_INT_CLR (*(volatile unsigned long *)(0x6000d17c)) 186#define GPIOL_INT_CLR (*(volatile unsigned long *)(0x6000d17c))
126 187
127#define DEV_RS (*(volatile unsigned long *)(0x60006004)) 188/* Device initialization */
128#define DEV_EN (*(volatile unsigned long *)(0x6000600c))
129
130#define DEV_SYSTEM 0x4
131#define DEV_I2C 0x1000
132#define DEV_USB 0x400000
133
134#define DEV_INIT (*(volatile unsigned long *)(0x70000020)) 189#define DEV_INIT (*(volatile unsigned long *)(0x70000020))
135 190
136#define INIT_USB 0x80000000 191#define INIT_USB 0x80000000
137 192
138#define TIMER1_CFG (*(volatile unsigned long *)(0x60005000)) 193/* I2C */
139#define TIMER1_VAL (*(volatile unsigned long *)(0x60005004))
140#define TIMER2_CFG (*(volatile unsigned long *)(0x60005008))
141#define TIMER2_VAL (*(volatile unsigned long *)(0x6000500c))
142#define USEC_TIMER (*(volatile unsigned long *)(0x60005010))
143
144#define CPU_INT_STAT (*(volatile unsigned long*)(0x64004000))
145#define CPU_HI_INT_STAT (*(volatile unsigned long*)(0x64004100))
146#define CPU_INT_EN (*(volatile unsigned long*)(0x60004024))
147#define CPU_HI_INT_EN (*(volatile unsigned long*)(0x60004124))
148#define CPU_INT_CLR (*(volatile unsigned long*)(0x60004028))
149#define CPU_HI_INT_CLR (*(volatile unsigned long*)(0x60004128))
150
151#define TIMER1_IRQ 0
152#define TIMER2_IRQ 1
153#define I2S_IRQ 10
154#define IDE_IRQ 23
155#define GPIO_IRQ (32+0)
156#define SER0_IRQ (32+4)
157#define SER1_IRQ (32+5)
158#define I2C_IRQ (32+8)
159
160#define TIMER1_MASK (1 << TIMER1_IRQ)
161#define TIMER2_MASK (1 << TIMER2_IRQ)
162#define I2S_MASK (1 << I2S_IRQ)
163#define IDE_MASK (1 << IDE_IRQ)
164#define GPIO_MASK (1 << (GPIO_IRQ-32))
165#define SER0_MASK (1 << (SER0_IRQ-32))
166#define SER1_MASK (1 << (SER1_IRQ-32))
167#define I2C_MASK (1 << (I2C_IRQ-32))
168
169#define I2C_BASE 0x7000c000 194#define I2C_BASE 0x7000c000
170 195
196/* I2S */
171#define IISCONFIG (*(volatile unsigned long*)(0x70002800)) 197#define IISCONFIG (*(volatile unsigned long*)(0x70002800))
172
173#define IISFIFO_CFG (*(volatile unsigned long*)(0x7000280c)) 198#define IISFIFO_CFG (*(volatile unsigned long*)(0x7000280c))
174#define IISFIFO_WR (*(volatile unsigned long*)(0x70002840)) 199#define IISFIFO_WR (*(volatile unsigned long*)(0x70002840))
175#define IISFIFO_RD (*(volatile unsigned long*)(0x70002880)) 200#define IISFIFO_RD (*(volatile unsigned long*)(0x70002880))
176 201
202/* USB controller */
203#define USB_BASE 0xc5000000
204
205/* Memory controller */
177#define MMAP0_LOGICAL (*(volatile unsigned long*)(0xf000f000)) 206#define MMAP0_LOGICAL (*(volatile unsigned long*)(0xf000f000))
178#define MMAP0_PHYSICAL (*(volatile unsigned long*)(0xf000f004)) 207#define MMAP0_PHYSICAL (*(volatile unsigned long*)(0xf000f004))
179#define MMAP1_LOGICAL (*(volatile unsigned long*)(0xf000f008)) 208#define MMAP1_LOGICAL (*(volatile unsigned long*)(0xf000f008))
@@ -183,10 +212,4 @@
183#define MMAP3_LOGICAL (*(volatile unsigned long*)(0xf000f018)) 212#define MMAP3_LOGICAL (*(volatile unsigned long*)(0xf000f018))
184#define MMAP3_PHYSICAL (*(volatile unsigned long*)(0xf000f01c)) 213#define MMAP3_PHYSICAL (*(volatile unsigned long*)(0xf000f01c))
185 214
186/* The PortalPlayer USB controller uses base address 0xc5000000 */
187#define USB_BASE 0xc5000000
188
189#define PROC_SLEEP 0x80000000
190#define PROC_WAKE 0x0
191
192#endif 215#endif