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-rw-r--r--firmware/export/jz4740.h9804
1 files changed, 4902 insertions, 4902 deletions
diff --git a/firmware/export/jz4740.h b/firmware/export/jz4740.h
index 7ad10b76a6..7a7a0d17bf 100644
--- a/firmware/export/jz4740.h
+++ b/firmware/export/jz4740.h
@@ -1,4902 +1,4902 @@
1/* 1/*
2 * Include file for Ingenic Semiconductor's JZ4740 CPU. 2 * Include file for Ingenic Semiconductor's JZ4740 CPU.
3 */ 3 */
4#ifndef __JZ4740_H__ 4#ifndef __JZ4740_H__
5#define __JZ4740_H__ 5#define __JZ4740_H__
6 6
7#ifndef __ASSEMBLY__ 7#ifndef __ASSEMBLY__
8 8
9#define cache_unroll(base,op) \ 9#define cache_unroll(base,op) \
10 __asm__ __volatile__(" \ 10 __asm__ __volatile__(" \
11 .set noreorder; \ 11 .set noreorder; \
12 .set mips3; \ 12 .set mips3; \
13 cache %1, (%0); \ 13 cache %1, (%0); \
14 .set mips0; \ 14 .set mips0; \
15 .set reorder" \ 15 .set reorder" \
16 : \ 16 : \
17 : "r" (base), \ 17 : "r" (base), \
18 "i" (op)); 18 "i" (op));
19 19
20#define Index_Invalidate_I 0x00 20#define Index_Invalidate_I 0x00
21#define Index_Writeback_Inv_D 0x01 21#define Index_Writeback_Inv_D 0x01
22 22
23#define CFG_DCACHE_SIZE 16384 23#define CFG_DCACHE_SIZE 16384
24#define CFG_ICACHE_SIZE 16384 24#define CFG_ICACHE_SIZE 16384
25#define CFG_CACHELINE_SIZE 32 25#define CFG_CACHELINE_SIZE 32
26 26
27#define KSEG0BASE 0x80003FFF /* HACK */ 27#define KSEG0BASE 0x80003FFF /* HACK */
28 28
29static inline void jz_flush_dcache(void) 29static inline void jz_flush_dcache(void)
30{ 30{
31 unsigned long start; 31 unsigned long start;
32 unsigned long end; 32 unsigned long end;
33 33
34 start = KSEG0BASE; 34 start = KSEG0BASE;
35 end = start + CFG_DCACHE_SIZE; 35 end = start + CFG_DCACHE_SIZE;
36 while (start < end) { 36 while (start < end) {
37 cache_unroll(start,Index_Writeback_Inv_D); 37 cache_unroll(start,Index_Writeback_Inv_D);
38 start += CFG_CACHELINE_SIZE; 38 start += CFG_CACHELINE_SIZE;
39 } 39 }
40} 40}
41 41
42static inline void jz_flush_icache(void) 42static inline void jz_flush_icache(void)
43{ 43{
44 unsigned long start; 44 unsigned long start;
45 unsigned long end; 45 unsigned long end;
46 46
47 start = KSEG0BASE; 47 start = KSEG0BASE;
48 end = start + CFG_ICACHE_SIZE; 48 end = start + CFG_ICACHE_SIZE;
49 while(start < end) { 49 while(start < end) {
50 cache_unroll(start,Index_Invalidate_I); 50 cache_unroll(start,Index_Invalidate_I);
51 start += CFG_CACHELINE_SIZE; 51 start += CFG_CACHELINE_SIZE;
52 } 52 }
53} 53}
54 54
55/* cpu pipeline flush */ 55/* cpu pipeline flush */
56static inline void jz_sync(void) 56static inline void jz_sync(void)
57{ 57{
58 __asm__ volatile ("sync"); 58 __asm__ volatile ("sync");
59} 59}
60 60
61#define REG8(addr) (*(volatile unsigned char *)(addr)) 61#define REG8(addr) (*(volatile unsigned char *)(addr))
62#define REG16(addr) (*(volatile unsigned short *)(addr)) 62#define REG16(addr) (*(volatile unsigned short *)(addr))
63#define REG32(addr) (*(volatile unsigned int *)(addr)) 63#define REG32(addr) (*(volatile unsigned int *)(addr))
64 64
65#endif /* !ASSEMBLY */ 65#endif /* !ASSEMBLY */
66 66
67//---------------------------------------------------------------------- 67//----------------------------------------------------------------------
68// Boot ROM Specification 68// Boot ROM Specification
69// 69//
70 70
71/* NOR Boot config */ 71/* NOR Boot config */
72#define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */ 72#define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */
73#define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */ 73#define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */
74#define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */ 74#define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */
75 75
76/* NAND Boot config */ 76/* NAND Boot config */
77#define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */ 77#define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */
78#define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */ 78#define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */
79#define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */ 79#define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */
80#define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */ 80#define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */
81 81
82 82
83//---------------------------------------------------------------------- 83//----------------------------------------------------------------------
84// Register Definitions 84// Register Definitions
85// 85//
86#define CPM_BASE 0xB0000000 86#define CPM_BASE 0xB0000000
87#define INTC_BASE 0xB0001000 87#define INTC_BASE 0xB0001000
88#define TCU_BASE 0xB0002000 88#define TCU_BASE 0xB0002000
89#define WDT_BASE 0xB0002000 89#define WDT_BASE 0xB0002000
90#define RTC_BASE 0xB0003000 90#define RTC_BASE 0xB0003000
91#define GPIO_BASE 0xB0010000 91#define GPIO_BASE 0xB0010000
92#define AIC_BASE 0xB0020000 92#define AIC_BASE 0xB0020000
93#define ICDC_BASE 0xB0020000 93#define ICDC_BASE 0xB0020000
94#define MSC_BASE 0xB0021000 94#define MSC_BASE 0xB0021000
95#define UART0_BASE 0xB0030000 95#define UART0_BASE 0xB0030000
96#define I2C_BASE 0xB0042000 96#define I2C_BASE 0xB0042000
97#define SSI_BASE 0xB0043000 97#define SSI_BASE 0xB0043000
98#define SADC_BASE 0xB0070000 98#define SADC_BASE 0xB0070000
99#define EMC_BASE 0xB3010000 99#define EMC_BASE 0xB3010000
100#define DMAC_BASE 0xB3020000 100#define DMAC_BASE 0xB3020000
101#define UHC_BASE 0xB3030000 101#define UHC_BASE 0xB3030000
102#define UDC_BASE 0xB3040000 102#define UDC_BASE 0xB3040000
103#define LCD_BASE 0xB3050000 103#define LCD_BASE 0xB3050000
104#define SLCD_BASE 0xB3050000 104#define SLCD_BASE 0xB3050000
105#define CIM_BASE 0xB3060000 105#define CIM_BASE 0xB3060000
106#define ETH_BASE 0xB3100000 106#define ETH_BASE 0xB3100000
107 107
108 108
109/************************************************************************* 109/*************************************************************************
110 * INTC (Interrupt Controller) 110 * INTC (Interrupt Controller)
111 *************************************************************************/ 111 *************************************************************************/
112#define INTC_ISR (INTC_BASE + 0x00) 112#define INTC_ISR (INTC_BASE + 0x00)
113#define INTC_IMR (INTC_BASE + 0x04) 113#define INTC_IMR (INTC_BASE + 0x04)
114#define INTC_IMSR (INTC_BASE + 0x08) 114#define INTC_IMSR (INTC_BASE + 0x08)
115#define INTC_IMCR (INTC_BASE + 0x0c) 115#define INTC_IMCR (INTC_BASE + 0x0c)
116#define INTC_IPR (INTC_BASE + 0x10) 116#define INTC_IPR (INTC_BASE + 0x10)
117 117
118#define REG_INTC_ISR REG32(INTC_ISR) 118#define REG_INTC_ISR REG32(INTC_ISR)
119#define REG_INTC_IMR REG32(INTC_IMR) 119#define REG_INTC_IMR REG32(INTC_IMR)
120#define REG_INTC_IMSR REG32(INTC_IMSR) 120#define REG_INTC_IMSR REG32(INTC_IMSR)
121#define REG_INTC_IMCR REG32(INTC_IMCR) 121#define REG_INTC_IMCR REG32(INTC_IMCR)
122#define REG_INTC_IPR REG32(INTC_IPR) 122#define REG_INTC_IPR REG32(INTC_IPR)
123 123
124// 1st-level interrupts 124// 1st-level interrupts
125#define IRQ_I2C 1 125#define IRQ_I2C 1
126#define IRQ_EMC 2 126#define IRQ_EMC 2
127#define IRQ_UHC 3 127#define IRQ_UHC 3
128#define IRQ_UART0 9 128#define IRQ_UART0 9
129#define IRQ_SADC 12 129#define IRQ_SADC 12
130#define IRQ_MSC 14 130#define IRQ_MSC 14
131#define IRQ_RTC 15 131#define IRQ_RTC 15
132#define IRQ_SSI 16 132#define IRQ_SSI 16
133#define IRQ_CIM 17 133#define IRQ_CIM 17
134#define IRQ_AIC 18 134#define IRQ_AIC 18
135#define IRQ_ETH 19 135#define IRQ_ETH 19
136#define IRQ_DMAC 20 136#define IRQ_DMAC 20
137#define IRQ_TCU2 21 137#define IRQ_TCU2 21
138#define IRQ_TCU1 22 138#define IRQ_TCU1 22
139#define IRQ_TCU0 23 139#define IRQ_TCU0 23
140#define IRQ_UDC 24 140#define IRQ_UDC 24
141#define IRQ_GPIO3 25 141#define IRQ_GPIO3 25
142#define IRQ_GPIO2 26 142#define IRQ_GPIO2 26
143#define IRQ_GPIO1 27 143#define IRQ_GPIO1 27
144#define IRQ_GPIO0 28 144#define IRQ_GPIO0 28
145#define IRQ_IPU 29 145#define IRQ_IPU 29
146#define IRQ_LCD 30 146#define IRQ_LCD 30
147 147
148// 2nd-level interrupts 148// 2nd-level interrupts
149#define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */ 149#define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */
150#define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */ 150#define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */
151 151
152 152
153/************************************************************************* 153/*************************************************************************
154 * RTC 154 * RTC
155 *************************************************************************/ 155 *************************************************************************/
156#define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */ 156#define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */
157#define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */ 157#define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */
158#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */ 158#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */
159#define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */ 159#define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */
160 160
161#define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */ 161#define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */
162#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */ 162#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */
163#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */ 163#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */
164#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */ 164#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */
165#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */ 165#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */
166#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */ 166#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */
167 167
168#define REG_RTC_RCR REG32(RTC_RCR) 168#define REG_RTC_RCR REG32(RTC_RCR)
169#define REG_RTC_RSR REG32(RTC_RSR) 169#define REG_RTC_RSR REG32(RTC_RSR)
170#define REG_RTC_RSAR REG32(RTC_RSAR) 170#define REG_RTC_RSAR REG32(RTC_RSAR)
171#define REG_RTC_RGR REG32(RTC_RGR) 171#define REG_RTC_RGR REG32(RTC_RGR)
172#define REG_RTC_HCR REG32(RTC_HCR) 172#define REG_RTC_HCR REG32(RTC_HCR)
173#define REG_RTC_HWFCR REG32(RTC_HWFCR) 173#define REG_RTC_HWFCR REG32(RTC_HWFCR)
174#define REG_RTC_HRCR REG32(RTC_HRCR) 174#define REG_RTC_HRCR REG32(RTC_HRCR)
175#define REG_RTC_HWCR REG32(RTC_HWCR) 175#define REG_RTC_HWCR REG32(RTC_HWCR)
176#define REG_RTC_HWRSR REG32(RTC_HWRSR) 176#define REG_RTC_HWRSR REG32(RTC_HWRSR)
177#define REG_RTC_HSPR REG32(RTC_HSPR) 177#define REG_RTC_HSPR REG32(RTC_HSPR)
178 178
179/* RTC Control Register */ 179/* RTC Control Register */
180#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */ 180#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */
181#define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */ 181#define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */
182#define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */ 182#define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */
183#define RTC_RCR_AF (1 << 4) /* Alarm Flag */ 183#define RTC_RCR_AF (1 << 4) /* Alarm Flag */
184#define RTC_RCR_AF_BIT 4 /* Alarm Flag */ 184#define RTC_RCR_AF_BIT 4 /* Alarm Flag */
185#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */ 185#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */
186#define RTC_RCR_AE (1 << 2) /* Alarm Enable */ 186#define RTC_RCR_AE (1 << 2) /* Alarm Enable */
187#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */ 187#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */
188 188
189/* RTC Regulator Register */ 189/* RTC Regulator Register */
190#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */ 190#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */
191#define RTC_RGR_ADJC_BIT 16 191#define RTC_RGR_ADJC_BIT 16
192#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT) 192#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT)
193#define RTC_RGR_NC1HZ_BIT 0 193#define RTC_RGR_NC1HZ_BIT 0
194#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT) 194#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT)
195 195
196/* Hibernate Control Register */ 196/* Hibernate Control Register */
197#define RTC_HCR_PD (1 << 0) /* Power Down */ 197#define RTC_HCR_PD (1 << 0) /* Power Down */
198 198
199/* Hibernate Wakeup Filter Counter Register */ 199/* Hibernate Wakeup Filter Counter Register */
200#define RTC_HWFCR_BIT 5 200#define RTC_HWFCR_BIT 5
201#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT) 201#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT)
202 202
203/* Hibernate Reset Counter Register */ 203/* Hibernate Reset Counter Register */
204#define RTC_HRCR_BIT 5 204#define RTC_HRCR_BIT 5
205#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT) 205#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT)
206 206
207/* Hibernate Wakeup Control Register */ 207/* Hibernate Wakeup Control Register */
208#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */ 208#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */
209 209
210/* Hibernate Wakeup Status Register */ 210/* Hibernate Wakeup Status Register */
211#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */ 211#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */
212#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */ 212#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */
213#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */ 213#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */
214#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */ 214#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */
215 215
216 216
217/************************************************************************* 217/*************************************************************************
218 * CPM (Clock reset and Power control Management) 218 * CPM (Clock reset and Power control Management)
219 *************************************************************************/ 219 *************************************************************************/
220#define CPM_CPCCR (CPM_BASE+0x00) 220#define CPM_CPCCR (CPM_BASE+0x00)
221#define CPM_CPPCR (CPM_BASE+0x10) 221#define CPM_CPPCR (CPM_BASE+0x10)
222#define CPM_I2SCDR (CPM_BASE+0x60) 222#define CPM_I2SCDR (CPM_BASE+0x60)
223#define CPM_LPCDR (CPM_BASE+0x64) 223#define CPM_LPCDR (CPM_BASE+0x64)
224#define CPM_MSCCDR (CPM_BASE+0x68) 224#define CPM_MSCCDR (CPM_BASE+0x68)
225#define CPM_UHCCDR (CPM_BASE+0x6C) 225#define CPM_UHCCDR (CPM_BASE+0x6C)
226 226
227#define CPM_LCR (CPM_BASE+0x04) 227#define CPM_LCR (CPM_BASE+0x04)
228#define CPM_CLKGR (CPM_BASE+0x20) 228#define CPM_CLKGR (CPM_BASE+0x20)
229#define CPM_SCR (CPM_BASE+0x24) 229#define CPM_SCR (CPM_BASE+0x24)
230 230
231#define CPM_HCR (CPM_BASE+0x30) 231#define CPM_HCR (CPM_BASE+0x30)
232#define CPM_HWFCR (CPM_BASE+0x34) 232#define CPM_HWFCR (CPM_BASE+0x34)
233#define CPM_HRCR (CPM_BASE+0x38) 233#define CPM_HRCR (CPM_BASE+0x38)
234#define CPM_HWCR (CPM_BASE+0x3c) 234#define CPM_HWCR (CPM_BASE+0x3c)
235#define CPM_HWSR (CPM_BASE+0x40) 235#define CPM_HWSR (CPM_BASE+0x40)
236#define CPM_HSPR (CPM_BASE+0x44) 236#define CPM_HSPR (CPM_BASE+0x44)
237 237
238#define CPM_RSR (CPM_BASE+0x08) 238#define CPM_RSR (CPM_BASE+0x08)
239 239
240 240
241#define REG_CPM_CPCCR REG32(CPM_CPCCR) 241#define REG_CPM_CPCCR REG32(CPM_CPCCR)
242#define REG_CPM_CPPCR REG32(CPM_CPPCR) 242#define REG_CPM_CPPCR REG32(CPM_CPPCR)
243#define REG_CPM_I2SCDR REG32(CPM_I2SCDR) 243#define REG_CPM_I2SCDR REG32(CPM_I2SCDR)
244#define REG_CPM_LPCDR REG32(CPM_LPCDR) 244#define REG_CPM_LPCDR REG32(CPM_LPCDR)
245#define REG_CPM_MSCCDR REG32(CPM_MSCCDR) 245#define REG_CPM_MSCCDR REG32(CPM_MSCCDR)
246#define REG_CPM_UHCCDR REG32(CPM_UHCCDR) 246#define REG_CPM_UHCCDR REG32(CPM_UHCCDR)
247 247
248#define REG_CPM_LCR REG32(CPM_LCR) 248#define REG_CPM_LCR REG32(CPM_LCR)
249#define REG_CPM_CLKGR REG32(CPM_CLKGR) 249#define REG_CPM_CLKGR REG32(CPM_CLKGR)
250#define REG_CPM_SCR REG32(CPM_SCR) 250#define REG_CPM_SCR REG32(CPM_SCR)
251#define REG_CPM_HCR REG32(CPM_HCR) 251#define REG_CPM_HCR REG32(CPM_HCR)
252#define REG_CPM_HWFCR REG32(CPM_HWFCR) 252#define REG_CPM_HWFCR REG32(CPM_HWFCR)
253#define REG_CPM_HRCR REG32(CPM_HRCR) 253#define REG_CPM_HRCR REG32(CPM_HRCR)
254#define REG_CPM_HWCR REG32(CPM_HWCR) 254#define REG_CPM_HWCR REG32(CPM_HWCR)
255#define REG_CPM_HWSR REG32(CPM_HWSR) 255#define REG_CPM_HWSR REG32(CPM_HWSR)
256#define REG_CPM_HSPR REG32(CPM_HSPR) 256#define REG_CPM_HSPR REG32(CPM_HSPR)
257 257
258#define REG_CPM_RSR REG32(CPM_RSR) 258#define REG_CPM_RSR REG32(CPM_RSR)
259 259
260 260
261/* Clock Control Register */ 261/* Clock Control Register */
262#define CPM_CPCCR_I2CS (1 << 31) 262#define CPM_CPCCR_I2CS (1 << 31)
263#define CPM_CPCCR_CLKOEN (1 << 30) 263#define CPM_CPCCR_CLKOEN (1 << 30)
264#define CPM_CPCCR_UCS (1 << 29) 264#define CPM_CPCCR_UCS (1 << 29)
265#define CPM_CPCCR_UDIV_BIT 23 265#define CPM_CPCCR_UDIV_BIT 23
266#define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT) 266#define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT)
267#define CPM_CPCCR_CE (1 << 22) 267#define CPM_CPCCR_CE (1 << 22)
268#define CPM_CPCCR_PCS (1 << 21) 268#define CPM_CPCCR_PCS (1 << 21)
269#define CPM_CPCCR_LDIV_BIT 16 269#define CPM_CPCCR_LDIV_BIT 16
270#define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT) 270#define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT)
271#define CPM_CPCCR_MDIV_BIT 12 271#define CPM_CPCCR_MDIV_BIT 12
272#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT) 272#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT)
273#define CPM_CPCCR_PDIV_BIT 8 273#define CPM_CPCCR_PDIV_BIT 8
274#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT) 274#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT)
275#define CPM_CPCCR_HDIV_BIT 4 275#define CPM_CPCCR_HDIV_BIT 4
276#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT) 276#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT)
277#define CPM_CPCCR_CDIV_BIT 0 277#define CPM_CPCCR_CDIV_BIT 0
278#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT) 278#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
279 279
280/* I2S Clock Divider Register */ 280/* I2S Clock Divider Register */
281#define CPM_I2SCDR_I2SDIV_BIT 0 281#define CPM_I2SCDR_I2SDIV_BIT 0
282#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT) 282#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
283 283
284/* LCD Pixel Clock Divider Register */ 284/* LCD Pixel Clock Divider Register */
285#define CPM_LPCDR_PIXDIV_BIT 0 285#define CPM_LPCDR_PIXDIV_BIT 0
286#define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT) 286#define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT)
287 287
288/* MSC Clock Divider Register */ 288/* MSC Clock Divider Register */
289#define CPM_MSCCDR_MSCDIV_BIT 0 289#define CPM_MSCCDR_MSCDIV_BIT 0
290#define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT) 290#define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT)
291 291
292/* PLL Control Register */ 292/* PLL Control Register */
293#define CPM_CPPCR_PLLM_BIT 23 293#define CPM_CPPCR_PLLM_BIT 23
294#define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT) 294#define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT)
295#define CPM_CPPCR_PLLN_BIT 18 295#define CPM_CPPCR_PLLN_BIT 18
296#define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT) 296#define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT)
297#define CPM_CPPCR_PLLOD_BIT 16 297#define CPM_CPPCR_PLLOD_BIT 16
298#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT) 298#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT)
299#define CPM_CPPCR_PLLS (1 << 10) 299#define CPM_CPPCR_PLLS (1 << 10)
300#define CPM_CPPCR_PLLBP (1 << 9) 300#define CPM_CPPCR_PLLBP (1 << 9)
301#define CPM_CPPCR_PLLEN (1 << 8) 301#define CPM_CPPCR_PLLEN (1 << 8)
302#define CPM_CPPCR_PLLST_BIT 0 302#define CPM_CPPCR_PLLST_BIT 0
303#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT) 303#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
304 304
305/* Low Power Control Register */ 305/* Low Power Control Register */
306#define CPM_LCR_DOZE_DUTY_BIT 3 306#define CPM_LCR_DOZE_DUTY_BIT 3
307#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT) 307#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
308#define CPM_LCR_DOZE_ON (1 << 2) 308#define CPM_LCR_DOZE_ON (1 << 2)
309#define CPM_LCR_LPM_BIT 0 309#define CPM_LCR_LPM_BIT 0
310#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT) 310#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
311 #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT) 311 #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT)
312 #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT) 312 #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT)
313 313
314/* Clock Gate Register */ 314/* Clock Gate Register */
315#define CPM_CLKGR_UART1 (1 << 15) 315#define CPM_CLKGR_UART1 (1 << 15)
316#define CPM_CLKGR_UHC (1 << 14) 316#define CPM_CLKGR_UHC (1 << 14)
317#define CPM_CLKGR_IPU (1 << 13) 317#define CPM_CLKGR_IPU (1 << 13)
318#define CPM_CLKGR_DMAC (1 << 12) 318#define CPM_CLKGR_DMAC (1 << 12)
319#define CPM_CLKGR_UDC (1 << 11) 319#define CPM_CLKGR_UDC (1 << 11)
320#define CPM_CLKGR_LCD (1 << 10) 320#define CPM_CLKGR_LCD (1 << 10)
321#define CPM_CLKGR_CIM (1 << 9) 321#define CPM_CLKGR_CIM (1 << 9)
322#define CPM_CLKGR_SADC (1 << 8) 322#define CPM_CLKGR_SADC (1 << 8)
323#define CPM_CLKGR_MSC (1 << 7) 323#define CPM_CLKGR_MSC (1 << 7)
324#define CPM_CLKGR_AIC1 (1 << 6) 324#define CPM_CLKGR_AIC1 (1 << 6)
325#define CPM_CLKGR_AIC2 (1 << 5) 325#define CPM_CLKGR_AIC2 (1 << 5)
326#define CPM_CLKGR_SSI (1 << 4) 326#define CPM_CLKGR_SSI (1 << 4)
327#define CPM_CLKGR_I2C (1 << 3) 327#define CPM_CLKGR_I2C (1 << 3)
328#define CPM_CLKGR_RTC (1 << 2) 328#define CPM_CLKGR_RTC (1 << 2)
329#define CPM_CLKGR_TCU (1 << 1) 329#define CPM_CLKGR_TCU (1 << 1)
330#define CPM_CLKGR_UART0 (1 << 0) 330#define CPM_CLKGR_UART0 (1 << 0)
331 331
332/* Sleep Control Register */ 332/* Sleep Control Register */
333#define CPM_SCR_O1ST_BIT 8 333#define CPM_SCR_O1ST_BIT 8
334#define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT) 334#define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT)
335#define CPM_SCR_USBPHY_ENABLE (1 << 6) 335#define CPM_SCR_USBPHY_ENABLE (1 << 6)
336#define CPM_SCR_OSC_ENABLE (1 << 4) 336#define CPM_SCR_OSC_ENABLE (1 << 4)
337 337
338/* Hibernate Control Register */ 338/* Hibernate Control Register */
339#define CPM_HCR_PD (1 << 0) 339#define CPM_HCR_PD (1 << 0)
340 340
341/* Wakeup Filter Counter Register in Hibernate Mode */ 341/* Wakeup Filter Counter Register in Hibernate Mode */
342#define CPM_HWFCR_TIME_BIT 0 342#define CPM_HWFCR_TIME_BIT 0
343#define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT) 343#define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT)
344 344
345/* Reset Counter Register in Hibernate Mode */ 345/* Reset Counter Register in Hibernate Mode */
346#define CPM_HRCR_TIME_BIT 0 346#define CPM_HRCR_TIME_BIT 0
347#define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT) 347#define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT)
348 348
349/* Wakeup Control Register in Hibernate Mode */ 349/* Wakeup Control Register in Hibernate Mode */
350#define CPM_HWCR_WLE_LOW (0 << 2) 350#define CPM_HWCR_WLE_LOW (0 << 2)
351#define CPM_HWCR_WLE_HIGH (1 << 2) 351#define CPM_HWCR_WLE_HIGH (1 << 2)
352#define CPM_HWCR_PIN_WAKEUP (1 << 1) 352#define CPM_HWCR_PIN_WAKEUP (1 << 1)
353#define CPM_HWCR_RTC_WAKEUP (1 << 0) 353#define CPM_HWCR_RTC_WAKEUP (1 << 0)
354 354
355/* Wakeup Status Register in Hibernate Mode */ 355/* Wakeup Status Register in Hibernate Mode */
356#define CPM_HWSR_WSR_PIN (1 << 1) 356#define CPM_HWSR_WSR_PIN (1 << 1)
357#define CPM_HWSR_WSR_RTC (1 << 0) 357#define CPM_HWSR_WSR_RTC (1 << 0)
358 358
359/* Reset Status Register */ 359/* Reset Status Register */
360#define CPM_RSR_HR (1 << 2) 360#define CPM_RSR_HR (1 << 2)
361#define CPM_RSR_WR (1 << 1) 361#define CPM_RSR_WR (1 << 1)
362#define CPM_RSR_PR (1 << 0) 362#define CPM_RSR_PR (1 << 0)
363 363
364 364
365/************************************************************************* 365/*************************************************************************
366 * TCU (Timer Counter Unit) 366 * TCU (Timer Counter Unit)
367 *************************************************************************/ 367 *************************************************************************/
368#define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */ 368#define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */
369#define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */ 369#define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */
370#define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */ 370#define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */
371#define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */ 371#define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */
372#define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */ 372#define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */
373#define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */ 373#define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */
374#define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */ 374#define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */
375#define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */ 375#define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */
376#define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */ 376#define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */
377#define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */ 377#define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */
378#define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */ 378#define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */
379#define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */ 379#define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */
380#define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */ 380#define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */
381#define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */ 381#define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */
382#define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */ 382#define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */
383#define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */ 383#define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */
384#define TCU_TDFR1 (TCU_BASE + 0x50) 384#define TCU_TDFR1 (TCU_BASE + 0x50)
385#define TCU_TDHR1 (TCU_BASE + 0x54) 385#define TCU_TDHR1 (TCU_BASE + 0x54)
386#define TCU_TCNT1 (TCU_BASE + 0x58) 386#define TCU_TCNT1 (TCU_BASE + 0x58)
387#define TCU_TCSR1 (TCU_BASE + 0x5C) 387#define TCU_TCSR1 (TCU_BASE + 0x5C)
388#define TCU_TDFR2 (TCU_BASE + 0x60) 388#define TCU_TDFR2 (TCU_BASE + 0x60)
389#define TCU_TDHR2 (TCU_BASE + 0x64) 389#define TCU_TDHR2 (TCU_BASE + 0x64)
390#define TCU_TCNT2 (TCU_BASE + 0x68) 390#define TCU_TCNT2 (TCU_BASE + 0x68)
391#define TCU_TCSR2 (TCU_BASE + 0x6C) 391#define TCU_TCSR2 (TCU_BASE + 0x6C)
392#define TCU_TDFR3 (TCU_BASE + 0x70) 392#define TCU_TDFR3 (TCU_BASE + 0x70)
393#define TCU_TDHR3 (TCU_BASE + 0x74) 393#define TCU_TDHR3 (TCU_BASE + 0x74)
394#define TCU_TCNT3 (TCU_BASE + 0x78) 394#define TCU_TCNT3 (TCU_BASE + 0x78)
395#define TCU_TCSR3 (TCU_BASE + 0x7C) 395#define TCU_TCSR3 (TCU_BASE + 0x7C)
396#define TCU_TDFR4 (TCU_BASE + 0x80) 396#define TCU_TDFR4 (TCU_BASE + 0x80)
397#define TCU_TDHR4 (TCU_BASE + 0x84) 397#define TCU_TDHR4 (TCU_BASE + 0x84)
398#define TCU_TCNT4 (TCU_BASE + 0x88) 398#define TCU_TCNT4 (TCU_BASE + 0x88)
399#define TCU_TCSR4 (TCU_BASE + 0x8C) 399#define TCU_TCSR4 (TCU_BASE + 0x8C)
400#define TCU_TDFR5 (TCU_BASE + 0x90) 400#define TCU_TDFR5 (TCU_BASE + 0x90)
401#define TCU_TDHR5 (TCU_BASE + 0x94) 401#define TCU_TDHR5 (TCU_BASE + 0x94)
402#define TCU_TCNT5 (TCU_BASE + 0x98) 402#define TCU_TCNT5 (TCU_BASE + 0x98)
403#define TCU_TCSR5 (TCU_BASE + 0x9C) 403#define TCU_TCSR5 (TCU_BASE + 0x9C)
404 404
405#define REG_TCU_TSR REG32(TCU_TSR) 405#define REG_TCU_TSR REG32(TCU_TSR)
406#define REG_TCU_TSSR REG32(TCU_TSSR) 406#define REG_TCU_TSSR REG32(TCU_TSSR)
407#define REG_TCU_TSCR REG32(TCU_TSCR) 407#define REG_TCU_TSCR REG32(TCU_TSCR)
408#define REG_TCU_TER REG8(TCU_TER) 408#define REG_TCU_TER REG8(TCU_TER)
409#define REG_TCU_TESR REG8(TCU_TESR) 409#define REG_TCU_TESR REG8(TCU_TESR)
410#define REG_TCU_TECR REG8(TCU_TECR) 410#define REG_TCU_TECR REG8(TCU_TECR)
411#define REG_TCU_TFR REG32(TCU_TFR) 411#define REG_TCU_TFR REG32(TCU_TFR)
412#define REG_TCU_TFSR REG32(TCU_TFSR) 412#define REG_TCU_TFSR REG32(TCU_TFSR)
413#define REG_TCU_TFCR REG32(TCU_TFCR) 413#define REG_TCU_TFCR REG32(TCU_TFCR)
414#define REG_TCU_TMR REG32(TCU_TMR) 414#define REG_TCU_TMR REG32(TCU_TMR)
415#define REG_TCU_TMSR REG32(TCU_TMSR) 415#define REG_TCU_TMSR REG32(TCU_TMSR)
416#define REG_TCU_TMCR REG32(TCU_TMCR) 416#define REG_TCU_TMCR REG32(TCU_TMCR)
417#define REG_TCU_TDFR0 REG16(TCU_TDFR0) 417#define REG_TCU_TDFR0 REG16(TCU_TDFR0)
418#define REG_TCU_TDHR0 REG16(TCU_TDHR0) 418#define REG_TCU_TDHR0 REG16(TCU_TDHR0)
419#define REG_TCU_TCNT0 REG16(TCU_TCNT0) 419#define REG_TCU_TCNT0 REG16(TCU_TCNT0)
420#define REG_TCU_TCSR0 REG16(TCU_TCSR0) 420#define REG_TCU_TCSR0 REG16(TCU_TCSR0)
421#define REG_TCU_TDFR1 REG16(TCU_TDFR1) 421#define REG_TCU_TDFR1 REG16(TCU_TDFR1)
422#define REG_TCU_TDHR1 REG16(TCU_TDHR1) 422#define REG_TCU_TDHR1 REG16(TCU_TDHR1)
423#define REG_TCU_TCNT1 REG16(TCU_TCNT1) 423#define REG_TCU_TCNT1 REG16(TCU_TCNT1)
424#define REG_TCU_TCSR1 REG16(TCU_TCSR1) 424#define REG_TCU_TCSR1 REG16(TCU_TCSR1)
425#define REG_TCU_TDFR2 REG16(TCU_TDFR2) 425#define REG_TCU_TDFR2 REG16(TCU_TDFR2)
426#define REG_TCU_TDHR2 REG16(TCU_TDHR2) 426#define REG_TCU_TDHR2 REG16(TCU_TDHR2)
427#define REG_TCU_TCNT2 REG16(TCU_TCNT2) 427#define REG_TCU_TCNT2 REG16(TCU_TCNT2)
428#define REG_TCU_TCSR2 REG16(TCU_TCSR2) 428#define REG_TCU_TCSR2 REG16(TCU_TCSR2)
429#define REG_TCU_TDFR3 REG16(TCU_TDFR3) 429#define REG_TCU_TDFR3 REG16(TCU_TDFR3)
430#define REG_TCU_TDHR3 REG16(TCU_TDHR3) 430#define REG_TCU_TDHR3 REG16(TCU_TDHR3)
431#define REG_TCU_TCNT3 REG16(TCU_TCNT3) 431#define REG_TCU_TCNT3 REG16(TCU_TCNT3)
432#define REG_TCU_TCSR3 REG16(TCU_TCSR3) 432#define REG_TCU_TCSR3 REG16(TCU_TCSR3)
433#define REG_TCU_TDFR4 REG16(TCU_TDFR4) 433#define REG_TCU_TDFR4 REG16(TCU_TDFR4)
434#define REG_TCU_TDHR4 REG16(TCU_TDHR4) 434#define REG_TCU_TDHR4 REG16(TCU_TDHR4)
435#define REG_TCU_TCNT4 REG16(TCU_TCNT4) 435#define REG_TCU_TCNT4 REG16(TCU_TCNT4)
436#define REG_TCU_TCSR4 REG16(TCU_TCSR4) 436#define REG_TCU_TCSR4 REG16(TCU_TCSR4)
437 437
438// n = 0,1,2,3,4,5 438// n = 0,1,2,3,4,5
439#define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */ 439#define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */
440#define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */ 440#define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */
441#define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */ 441#define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */
442#define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */ 442#define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */
443 443
444#define REG_TCU_TDFR(n) REG16(TCU_TDFR((n))) 444#define REG_TCU_TDFR(n) REG16(TCU_TDFR((n)))
445#define REG_TCU_TDHR(n) REG16(TCU_TDHR((n))) 445#define REG_TCU_TDHR(n) REG16(TCU_TDHR((n)))
446#define REG_TCU_TCNT(n) REG16(TCU_TCNT((n))) 446#define REG_TCU_TCNT(n) REG16(TCU_TCNT((n)))
447#define REG_TCU_TCSR(n) REG16(TCU_TCSR((n))) 447#define REG_TCU_TCSR(n) REG16(TCU_TCSR((n)))
448 448
449// Register definitions 449// Register definitions
450#define TCU_TCSR_PWM_SD (1 << 9) 450#define TCU_TCSR_PWM_SD (1 << 9)
451#define TCU_TCSR_PWM_INITL_HIGH (1 << 8) 451#define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
452#define TCU_TCSR_PWM_EN (1 << 7) 452#define TCU_TCSR_PWM_EN (1 << 7)
453#define TCU_TCSR_PRESCALE_BIT 3 453#define TCU_TCSR_PRESCALE_BIT 3
454#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT) 454#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
455 #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT) 455 #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
456 #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT) 456 #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
457 #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT) 457 #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
458 #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT) 458 #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
459 #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT) 459 #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
460 #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT) 460 #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
461#define TCU_TCSR_EXT_EN (1 << 2) 461#define TCU_TCSR_EXT_EN (1 << 2)
462#define TCU_TCSR_RTC_EN (1 << 1) 462#define TCU_TCSR_RTC_EN (1 << 1)
463#define TCU_TCSR_PCK_EN (1 << 0) 463#define TCU_TCSR_PCK_EN (1 << 0)
464 464
465#define TCU_TER_TCEN5 (1 << 5) 465#define TCU_TER_TCEN5 (1 << 5)
466#define TCU_TER_TCEN4 (1 << 4) 466#define TCU_TER_TCEN4 (1 << 4)
467#define TCU_TER_TCEN3 (1 << 3) 467#define TCU_TER_TCEN3 (1 << 3)
468#define TCU_TER_TCEN2 (1 << 2) 468#define TCU_TER_TCEN2 (1 << 2)
469#define TCU_TER_TCEN1 (1 << 1) 469#define TCU_TER_TCEN1 (1 << 1)
470#define TCU_TER_TCEN0 (1 << 0) 470#define TCU_TER_TCEN0 (1 << 0)
471 471
472#define TCU_TESR_TCST5 (1 << 5) 472#define TCU_TESR_TCST5 (1 << 5)
473#define TCU_TESR_TCST4 (1 << 4) 473#define TCU_TESR_TCST4 (1 << 4)
474#define TCU_TESR_TCST3 (1 << 3) 474#define TCU_TESR_TCST3 (1 << 3)
475#define TCU_TESR_TCST2 (1 << 2) 475#define TCU_TESR_TCST2 (1 << 2)
476#define TCU_TESR_TCST1 (1 << 1) 476#define TCU_TESR_TCST1 (1 << 1)
477#define TCU_TESR_TCST0 (1 << 0) 477#define TCU_TESR_TCST0 (1 << 0)
478 478
479#define TCU_TECR_TCCL5 (1 << 5) 479#define TCU_TECR_TCCL5 (1 << 5)
480#define TCU_TECR_TCCL4 (1 << 4) 480#define TCU_TECR_TCCL4 (1 << 4)
481#define TCU_TECR_TCCL3 (1 << 3) 481#define TCU_TECR_TCCL3 (1 << 3)
482#define TCU_TECR_TCCL2 (1 << 2) 482#define TCU_TECR_TCCL2 (1 << 2)
483#define TCU_TECR_TCCL1 (1 << 1) 483#define TCU_TECR_TCCL1 (1 << 1)
484#define TCU_TECR_TCCL0 (1 << 0) 484#define TCU_TECR_TCCL0 (1 << 0)
485 485
486#define TCU_TFR_HFLAG5 (1 << 21) 486#define TCU_TFR_HFLAG5 (1 << 21)
487#define TCU_TFR_HFLAG4 (1 << 20) 487#define TCU_TFR_HFLAG4 (1 << 20)
488#define TCU_TFR_HFLAG3 (1 << 19) 488#define TCU_TFR_HFLAG3 (1 << 19)
489#define TCU_TFR_HFLAG2 (1 << 18) 489#define TCU_TFR_HFLAG2 (1 << 18)
490#define TCU_TFR_HFLAG1 (1 << 17) 490#define TCU_TFR_HFLAG1 (1 << 17)
491#define TCU_TFR_HFLAG0 (1 << 16) 491#define TCU_TFR_HFLAG0 (1 << 16)
492#define TCU_TFR_FFLAG5 (1 << 5) 492#define TCU_TFR_FFLAG5 (1 << 5)
493#define TCU_TFR_FFLAG4 (1 << 4) 493#define TCU_TFR_FFLAG4 (1 << 4)
494#define TCU_TFR_FFLAG3 (1 << 3) 494#define TCU_TFR_FFLAG3 (1 << 3)
495#define TCU_TFR_FFLAG2 (1 << 2) 495#define TCU_TFR_FFLAG2 (1 << 2)
496#define TCU_TFR_FFLAG1 (1 << 1) 496#define TCU_TFR_FFLAG1 (1 << 1)
497#define TCU_TFR_FFLAG0 (1 << 0) 497#define TCU_TFR_FFLAG0 (1 << 0)
498 498
499#define TCU_TFSR_HFLAG5 (1 << 21) 499#define TCU_TFSR_HFLAG5 (1 << 21)
500#define TCU_TFSR_HFLAG4 (1 << 20) 500#define TCU_TFSR_HFLAG4 (1 << 20)
501#define TCU_TFSR_HFLAG3 (1 << 19) 501#define TCU_TFSR_HFLAG3 (1 << 19)
502#define TCU_TFSR_HFLAG2 (1 << 18) 502#define TCU_TFSR_HFLAG2 (1 << 18)
503#define TCU_TFSR_HFLAG1 (1 << 17) 503#define TCU_TFSR_HFLAG1 (1 << 17)
504#define TCU_TFSR_HFLAG0 (1 << 16) 504#define TCU_TFSR_HFLAG0 (1 << 16)
505#define TCU_TFSR_FFLAG5 (1 << 5) 505#define TCU_TFSR_FFLAG5 (1 << 5)
506#define TCU_TFSR_FFLAG4 (1 << 4) 506#define TCU_TFSR_FFLAG4 (1 << 4)
507#define TCU_TFSR_FFLAG3 (1 << 3) 507#define TCU_TFSR_FFLAG3 (1 << 3)
508#define TCU_TFSR_FFLAG2 (1 << 2) 508#define TCU_TFSR_FFLAG2 (1 << 2)
509#define TCU_TFSR_FFLAG1 (1 << 1) 509#define TCU_TFSR_FFLAG1 (1 << 1)
510#define TCU_TFSR_FFLAG0 (1 << 0) 510#define TCU_TFSR_FFLAG0 (1 << 0)
511 511
512#define TCU_TFCR_HFLAG5 (1 << 21) 512#define TCU_TFCR_HFLAG5 (1 << 21)
513#define TCU_TFCR_HFLAG4 (1 << 20) 513#define TCU_TFCR_HFLAG4 (1 << 20)
514#define TCU_TFCR_HFLAG3 (1 << 19) 514#define TCU_TFCR_HFLAG3 (1 << 19)
515#define TCU_TFCR_HFLAG2 (1 << 18) 515#define TCU_TFCR_HFLAG2 (1 << 18)
516#define TCU_TFCR_HFLAG1 (1 << 17) 516#define TCU_TFCR_HFLAG1 (1 << 17)
517#define TCU_TFCR_HFLAG0 (1 << 16) 517#define TCU_TFCR_HFLAG0 (1 << 16)
518#define TCU_TFCR_FFLAG5 (1 << 5) 518#define TCU_TFCR_FFLAG5 (1 << 5)
519#define TCU_TFCR_FFLAG4 (1 << 4) 519#define TCU_TFCR_FFLAG4 (1 << 4)
520#define TCU_TFCR_FFLAG3 (1 << 3) 520#define TCU_TFCR_FFLAG3 (1 << 3)
521#define TCU_TFCR_FFLAG2 (1 << 2) 521#define TCU_TFCR_FFLAG2 (1 << 2)
522#define TCU_TFCR_FFLAG1 (1 << 1) 522#define TCU_TFCR_FFLAG1 (1 << 1)
523#define TCU_TFCR_FFLAG0 (1 << 0) 523#define TCU_TFCR_FFLAG0 (1 << 0)
524 524
525#define TCU_TMR_HMASK5 (1 << 21) 525#define TCU_TMR_HMASK5 (1 << 21)
526#define TCU_TMR_HMASK4 (1 << 20) 526#define TCU_TMR_HMASK4 (1 << 20)
527#define TCU_TMR_HMASK3 (1 << 19) 527#define TCU_TMR_HMASK3 (1 << 19)
528#define TCU_TMR_HMASK2 (1 << 18) 528#define TCU_TMR_HMASK2 (1 << 18)
529#define TCU_TMR_HMASK1 (1 << 17) 529#define TCU_TMR_HMASK1 (1 << 17)
530#define TCU_TMR_HMASK0 (1 << 16) 530#define TCU_TMR_HMASK0 (1 << 16)
531#define TCU_TMR_FMASK5 (1 << 5) 531#define TCU_TMR_FMASK5 (1 << 5)
532#define TCU_TMR_FMASK4 (1 << 4) 532#define TCU_TMR_FMASK4 (1 << 4)
533#define TCU_TMR_FMASK3 (1 << 3) 533#define TCU_TMR_FMASK3 (1 << 3)
534#define TCU_TMR_FMASK2 (1 << 2) 534#define TCU_TMR_FMASK2 (1 << 2)
535#define TCU_TMR_FMASK1 (1 << 1) 535#define TCU_TMR_FMASK1 (1 << 1)
536#define TCU_TMR_FMASK0 (1 << 0) 536#define TCU_TMR_FMASK0 (1 << 0)
537 537
538#define TCU_TMSR_HMST5 (1 << 21) 538#define TCU_TMSR_HMST5 (1 << 21)
539#define TCU_TMSR_HMST4 (1 << 20) 539#define TCU_TMSR_HMST4 (1 << 20)
540#define TCU_TMSR_HMST3 (1 << 19) 540#define TCU_TMSR_HMST3 (1 << 19)
541#define TCU_TMSR_HMST2 (1 << 18) 541#define TCU_TMSR_HMST2 (1 << 18)
542#define TCU_TMSR_HMST1 (1 << 17) 542#define TCU_TMSR_HMST1 (1 << 17)
543#define TCU_TMSR_HMST0 (1 << 16) 543#define TCU_TMSR_HMST0 (1 << 16)
544#define TCU_TMSR_FMST5 (1 << 5) 544#define TCU_TMSR_FMST5 (1 << 5)
545#define TCU_TMSR_FMST4 (1 << 4) 545#define TCU_TMSR_FMST4 (1 << 4)
546#define TCU_TMSR_FMST3 (1 << 3) 546#define TCU_TMSR_FMST3 (1 << 3)
547#define TCU_TMSR_FMST2 (1 << 2) 547#define TCU_TMSR_FMST2 (1 << 2)
548#define TCU_TMSR_FMST1 (1 << 1) 548#define TCU_TMSR_FMST1 (1 << 1)
549#define TCU_TMSR_FMST0 (1 << 0) 549#define TCU_TMSR_FMST0 (1 << 0)
550 550
551#define TCU_TMCR_HMCL5 (1 << 21) 551#define TCU_TMCR_HMCL5 (1 << 21)
552#define TCU_TMCR_HMCL4 (1 << 20) 552#define TCU_TMCR_HMCL4 (1 << 20)
553#define TCU_TMCR_HMCL3 (1 << 19) 553#define TCU_TMCR_HMCL3 (1 << 19)
554#define TCU_TMCR_HMCL2 (1 << 18) 554#define TCU_TMCR_HMCL2 (1 << 18)
555#define TCU_TMCR_HMCL1 (1 << 17) 555#define TCU_TMCR_HMCL1 (1 << 17)
556#define TCU_TMCR_HMCL0 (1 << 16) 556#define TCU_TMCR_HMCL0 (1 << 16)
557#define TCU_TMCR_FMCL5 (1 << 5) 557#define TCU_TMCR_FMCL5 (1 << 5)
558#define TCU_TMCR_FMCL4 (1 << 4) 558#define TCU_TMCR_FMCL4 (1 << 4)
559#define TCU_TMCR_FMCL3 (1 << 3) 559#define TCU_TMCR_FMCL3 (1 << 3)
560#define TCU_TMCR_FMCL2 (1 << 2) 560#define TCU_TMCR_FMCL2 (1 << 2)
561#define TCU_TMCR_FMCL1 (1 << 1) 561#define TCU_TMCR_FMCL1 (1 << 1)
562#define TCU_TMCR_FMCL0 (1 << 0) 562#define TCU_TMCR_FMCL0 (1 << 0)
563 563
564#define TCU_TSR_WDTS (1 << 16) 564#define TCU_TSR_WDTS (1 << 16)
565#define TCU_TSR_STOP5 (1 << 5) 565#define TCU_TSR_STOP5 (1 << 5)
566#define TCU_TSR_STOP4 (1 << 4) 566#define TCU_TSR_STOP4 (1 << 4)
567#define TCU_TSR_STOP3 (1 << 3) 567#define TCU_TSR_STOP3 (1 << 3)
568#define TCU_TSR_STOP2 (1 << 2) 568#define TCU_TSR_STOP2 (1 << 2)
569#define TCU_TSR_STOP1 (1 << 1) 569#define TCU_TSR_STOP1 (1 << 1)
570#define TCU_TSR_STOP0 (1 << 0) 570#define TCU_TSR_STOP0 (1 << 0)
571 571
572#define TCU_TSSR_WDTSS (1 << 16) 572#define TCU_TSSR_WDTSS (1 << 16)
573#define TCU_TSSR_STPS5 (1 << 5) 573#define TCU_TSSR_STPS5 (1 << 5)
574#define TCU_TSSR_STPS4 (1 << 4) 574#define TCU_TSSR_STPS4 (1 << 4)
575#define TCU_TSSR_STPS3 (1 << 3) 575#define TCU_TSSR_STPS3 (1 << 3)
576#define TCU_TSSR_STPS2 (1 << 2) 576#define TCU_TSSR_STPS2 (1 << 2)
577#define TCU_TSSR_STPS1 (1 << 1) 577#define TCU_TSSR_STPS1 (1 << 1)
578#define TCU_TSSR_STPS0 (1 << 0) 578#define TCU_TSSR_STPS0 (1 << 0)
579 579
580#define TCU_TSSR_WDTSC (1 << 16) 580#define TCU_TSSR_WDTSC (1 << 16)
581#define TCU_TSSR_STPC5 (1 << 5) 581#define TCU_TSSR_STPC5 (1 << 5)
582#define TCU_TSSR_STPC4 (1 << 4) 582#define TCU_TSSR_STPC4 (1 << 4)
583#define TCU_TSSR_STPC3 (1 << 3) 583#define TCU_TSSR_STPC3 (1 << 3)
584#define TCU_TSSR_STPC2 (1 << 2) 584#define TCU_TSSR_STPC2 (1 << 2)
585#define TCU_TSSR_STPC1 (1 << 1) 585#define TCU_TSSR_STPC1 (1 << 1)
586#define TCU_TSSR_STPC0 (1 << 0) 586#define TCU_TSSR_STPC0 (1 << 0)
587 587
588 588
589/************************************************************************* 589/*************************************************************************
590 * WDT (WatchDog Timer) 590 * WDT (WatchDog Timer)
591 *************************************************************************/ 591 *************************************************************************/
592#define WDT_TDR (WDT_BASE + 0x00) 592#define WDT_TDR (WDT_BASE + 0x00)
593#define WDT_TCER (WDT_BASE + 0x04) 593#define WDT_TCER (WDT_BASE + 0x04)
594#define WDT_TCNT (WDT_BASE + 0x08) 594#define WDT_TCNT (WDT_BASE + 0x08)
595#define WDT_TCSR (WDT_BASE + 0x0C) 595#define WDT_TCSR (WDT_BASE + 0x0C)
596 596
597#define REG_WDT_TDR REG16(WDT_TDR) 597#define REG_WDT_TDR REG16(WDT_TDR)
598#define REG_WDT_TCER REG8(WDT_TCER) 598#define REG_WDT_TCER REG8(WDT_TCER)
599#define REG_WDT_TCNT REG16(WDT_TCNT) 599#define REG_WDT_TCNT REG16(WDT_TCNT)
600#define REG_WDT_TCSR REG16(WDT_TCSR) 600#define REG_WDT_TCSR REG16(WDT_TCSR)
601 601
602// Register definition 602// Register definition
603#define WDT_TCSR_PRESCALE_BIT 3 603#define WDT_TCSR_PRESCALE_BIT 3
604#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT) 604#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
605 #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT) 605 #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
606 #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT) 606 #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
607 #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT) 607 #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
608 #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT) 608 #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
609 #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT) 609 #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
610 #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT) 610 #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
611#define WDT_TCSR_EXT_EN (1 << 2) 611#define WDT_TCSR_EXT_EN (1 << 2)
612#define WDT_TCSR_RTC_EN (1 << 1) 612#define WDT_TCSR_RTC_EN (1 << 1)
613#define WDT_TCSR_PCK_EN (1 << 0) 613#define WDT_TCSR_PCK_EN (1 << 0)
614 614
615#define WDT_TCER_TCEN (1 << 0) 615#define WDT_TCER_TCEN (1 << 0)
616 616
617 617
618/************************************************************************* 618/*************************************************************************
619 * DMAC (DMA Controller) 619 * DMAC (DMA Controller)
620 *************************************************************************/ 620 *************************************************************************/
621 621
622#define MAX_DMA_NUM 6 /* max 6 channels */ 622#define MAX_DMA_NUM 6 /* max 6 channels */
623 623
624#define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */ 624#define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */
625#define DMAC_DTAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */ 625#define DMAC_DTAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */
626#define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */ 626#define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */
627#define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */ 627#define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */
628#define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */ 628#define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */
629#define DMAC_DCMD(n) (DMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */ 629#define DMAC_DCMD(n) (DMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */
630#define DMAC_DDA(n) (DMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */ 630#define DMAC_DDA(n) (DMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */
631#define DMAC_DMACR (DMAC_BASE + 0x0300) /* DMA control register */ 631#define DMAC_DMACR (DMAC_BASE + 0x0300) /* DMA control register */
632#define DMAC_DMAIPR (DMAC_BASE + 0x0304) /* DMA interrupt pending */ 632#define DMAC_DMAIPR (DMAC_BASE + 0x0304) /* DMA interrupt pending */
633#define DMAC_DMADBR (DMAC_BASE + 0x0308) /* DMA doorbell */ 633#define DMAC_DMADBR (DMAC_BASE + 0x0308) /* DMA doorbell */
634#define DMAC_DMADBSR (DMAC_BASE + 0x030C) /* DMA doorbell set */ 634#define DMAC_DMADBSR (DMAC_BASE + 0x030C) /* DMA doorbell set */
635 635
636// channel 0 636// channel 0
637#define DMAC_DSAR0 DMAC_DSAR(0) 637#define DMAC_DSAR0 DMAC_DSAR(0)
638#define DMAC_DTAR0 DMAC_DTAR(0) 638#define DMAC_DTAR0 DMAC_DTAR(0)
639#define DMAC_DTCR0 DMAC_DTCR(0) 639#define DMAC_DTCR0 DMAC_DTCR(0)
640#define DMAC_DRSR0 DMAC_DRSR(0) 640#define DMAC_DRSR0 DMAC_DRSR(0)
641#define DMAC_DCCSR0 DMAC_DCCSR(0) 641#define DMAC_DCCSR0 DMAC_DCCSR(0)
642#define DMAC_DCMD0 DMAC_DCMD(0) 642#define DMAC_DCMD0 DMAC_DCMD(0)
643#define DMAC_DDA0 DMAC_DDA(0) 643#define DMAC_DDA0 DMAC_DDA(0)
644 644
645// channel 1 645// channel 1
646#define DMAC_DSAR1 DMAC_DSAR(1) 646#define DMAC_DSAR1 DMAC_DSAR(1)
647#define DMAC_DTAR1 DMAC_DTAR(1) 647#define DMAC_DTAR1 DMAC_DTAR(1)
648#define DMAC_DTCR1 DMAC_DTCR(1) 648#define DMAC_DTCR1 DMAC_DTCR(1)
649#define DMAC_DRSR1 DMAC_DRSR(1) 649#define DMAC_DRSR1 DMAC_DRSR(1)
650#define DMAC_DCCSR1 DMAC_DCCSR(1) 650#define DMAC_DCCSR1 DMAC_DCCSR(1)
651#define DMAC_DCMD1 DMAC_DCMD(1) 651#define DMAC_DCMD1 DMAC_DCMD(1)
652#define DMAC_DDA1 DMAC_DDA(1) 652#define DMAC_DDA1 DMAC_DDA(1)
653 653
654// channel 2 654// channel 2
655#define DMAC_DSAR2 DMAC_DSAR(2) 655#define DMAC_DSAR2 DMAC_DSAR(2)
656#define DMAC_DTAR2 DMAC_DTAR(2) 656#define DMAC_DTAR2 DMAC_DTAR(2)
657#define DMAC_DTCR2 DMAC_DTCR(2) 657#define DMAC_DTCR2 DMAC_DTCR(2)
658#define DMAC_DRSR2 DMAC_DRSR(2) 658#define DMAC_DRSR2 DMAC_DRSR(2)
659#define DMAC_DCCSR2 DMAC_DCCSR(2) 659#define DMAC_DCCSR2 DMAC_DCCSR(2)
660#define DMAC_DCMD2 DMAC_DCMD(2) 660#define DMAC_DCMD2 DMAC_DCMD(2)
661#define DMAC_DDA2 DMAC_DDA(2) 661#define DMAC_DDA2 DMAC_DDA(2)
662 662
663// channel 3 663// channel 3
664#define DMAC_DSAR3 DMAC_DSAR(3) 664#define DMAC_DSAR3 DMAC_DSAR(3)
665#define DMAC_DTAR3 DMAC_DTAR(3) 665#define DMAC_DTAR3 DMAC_DTAR(3)
666#define DMAC_DTCR3 DMAC_DTCR(3) 666#define DMAC_DTCR3 DMAC_DTCR(3)
667#define DMAC_DRSR3 DMAC_DRSR(3) 667#define DMAC_DRSR3 DMAC_DRSR(3)
668#define DMAC_DCCSR3 DMAC_DCCSR(3) 668#define DMAC_DCCSR3 DMAC_DCCSR(3)
669#define DMAC_DCMD3 DMAC_DCMD(3) 669#define DMAC_DCMD3 DMAC_DCMD(3)
670#define DMAC_DDA3 DMAC_DDA(3) 670#define DMAC_DDA3 DMAC_DDA(3)
671 671
672// channel 4 672// channel 4
673#define DMAC_DSAR4 DMAC_DSAR(4) 673#define DMAC_DSAR4 DMAC_DSAR(4)
674#define DMAC_DTAR4 DMAC_DTAR(4) 674#define DMAC_DTAR4 DMAC_DTAR(4)
675#define DMAC_DTCR4 DMAC_DTCR(4) 675#define DMAC_DTCR4 DMAC_DTCR(4)
676#define DMAC_DRSR4 DMAC_DRSR(4) 676#define DMAC_DRSR4 DMAC_DRSR(4)
677#define DMAC_DCCSR4 DMAC_DCCSR(4) 677#define DMAC_DCCSR4 DMAC_DCCSR(4)
678#define DMAC_DCMD4 DMAC_DCMD(4) 678#define DMAC_DCMD4 DMAC_DCMD(4)
679#define DMAC_DDA4 DMAC_DDA(4) 679#define DMAC_DDA4 DMAC_DDA(4)
680 680
681// channel 5 681// channel 5
682#define DMAC_DSAR5 DMAC_DSAR(5) 682#define DMAC_DSAR5 DMAC_DSAR(5)
683#define DMAC_DTAR5 DMAC_DTAR(5) 683#define DMAC_DTAR5 DMAC_DTAR(5)
684#define DMAC_DTCR5 DMAC_DTCR(5) 684#define DMAC_DTCR5 DMAC_DTCR(5)
685#define DMAC_DRSR5 DMAC_DRSR(5) 685#define DMAC_DRSR5 DMAC_DRSR(5)
686#define DMAC_DCCSR5 DMAC_DCCSR(5) 686#define DMAC_DCCSR5 DMAC_DCCSR(5)
687#define DMAC_DCMD5 DMAC_DCMD(5) 687#define DMAC_DCMD5 DMAC_DCMD(5)
688#define DMAC_DDA5 DMAC_DDA(5) 688#define DMAC_DDA5 DMAC_DDA(5)
689 689
690#define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n))) 690#define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n)))
691#define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n))) 691#define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n)))
692#define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n))) 692#define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n)))
693#define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n))) 693#define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n)))
694#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n))) 694#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n)))
695#define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n))) 695#define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n)))
696#define REG_DMAC_DDA(n) REG32(DMAC_DDA((n))) 696#define REG_DMAC_DDA(n) REG32(DMAC_DDA((n)))
697#define REG_DMAC_DMACR REG32(DMAC_DMACR) 697#define REG_DMAC_DMACR REG32(DMAC_DMACR)
698#define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR) 698#define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR)
699#define REG_DMAC_DMADBR REG32(DMAC_DMADBR) 699#define REG_DMAC_DMADBR REG32(DMAC_DMADBR)
700#define REG_DMAC_DMADBSR REG32(DMAC_DMADBSR) 700#define REG_DMAC_DMADBSR REG32(DMAC_DMADBSR)
701 701
702// DMA request source register 702// DMA request source register
703#define DMAC_DRSR_RS_BIT 0 703#define DMAC_DRSR_RS_BIT 0
704#define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT) 704#define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT)
705 #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT) 705 #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT)
706 #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT) 706 #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT)
707 #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT) 707 #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT)
708 #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT) 708 #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT)
709 #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT) 709 #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT)
710 #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT) 710 #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT)
711 #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT) 711 #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT)
712 #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT) 712 #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT)
713 #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT) 713 #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT)
714 #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT) 714 #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT)
715 #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT) 715 #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT)
716 #define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT) 716 #define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT)
717 717
718// DMA channel control/status register 718// DMA channel control/status register
719#define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */ 719#define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */
720#define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */ 720#define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */
721#define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT) 721#define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT)
722#define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */ 722#define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */
723#define DMAC_DCCSR_AR (1 << 4) /* address error */ 723#define DMAC_DCCSR_AR (1 << 4) /* address error */
724#define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */ 724#define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */
725#define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */ 725#define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */
726#define DMAC_DCCSR_CT (1 << 1) /* count terminated */ 726#define DMAC_DCCSR_CT (1 << 1) /* count terminated */
727#define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */ 727#define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */
728 728
729// DMA channel command register 729// DMA channel command register
730#define DMAC_DCMD_SAI (1 << 23) /* source address increment */ 730#define DMAC_DCMD_SAI (1 << 23) /* source address increment */
731#define DMAC_DCMD_DAI (1 << 22) /* dest address increment */ 731#define DMAC_DCMD_DAI (1 << 22) /* dest address increment */
732#define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */ 732#define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */
733#define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT) 733#define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT)
734 #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT) 734 #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT)
735 #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT) 735 #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT)
736 #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT) 736 #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT)
737 #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT) 737 #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT)
738 #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT) 738 #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT)
739 #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT) 739 #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT)
740 #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT) 740 #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT)
741 #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT) 741 #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT)
742 #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT) 742 #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT)
743 #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT) 743 #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT)
744 #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT) 744 #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT)
745 #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT) 745 #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT)
746 #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT) 746 #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT)
747 #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT) 747 #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT)
748 #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT) 748 #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT)
749 #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT) 749 #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT)
750#define DMAC_DCMD_SWDH_BIT 14 /* source port width */ 750#define DMAC_DCMD_SWDH_BIT 14 /* source port width */
751#define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT) 751#define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT)
752 #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT) 752 #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT)
753 #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT) 753 #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT)
754 #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT) 754 #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT)
755#define DMAC_DCMD_DWDH_BIT 12 /* dest port width */ 755#define DMAC_DCMD_DWDH_BIT 12 /* dest port width */
756#define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT) 756#define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT)
757 #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT) 757 #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT)
758 #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT) 758 #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT)
759 #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT) 759 #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT)
760#define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */ 760#define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */
761#define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT) 761#define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT)
762 #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT) 762 #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT)
763 #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT) 763 #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT)
764 #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT) 764 #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT)
765 #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT) 765 #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT)
766 #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT) 766 #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT)
767#define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */ 767#define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */
768#define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */ 768#define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */
769#define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */ 769#define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */
770#define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */ 770#define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */
771#define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */ 771#define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */
772#define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */ 772#define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */
773 773
774// DMA descriptor address register 774// DMA descriptor address register
775#define DMAC_DDA_BASE_BIT 12 /* descriptor base address */ 775#define DMAC_DDA_BASE_BIT 12 /* descriptor base address */
776#define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT) 776#define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT)
777#define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */ 777#define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */
778#define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT) 778#define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT)
779 779
780// DMA control register 780// DMA control register
781#define DMAC_DMACR_PR_BIT 8 /* channel priority mode */ 781#define DMAC_DMACR_PR_BIT 8 /* channel priority mode */
782#define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT) 782#define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT)
783 #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT) 783 #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT)
784 #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT) 784 #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT)
785 #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT) 785 #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT)
786 #define DMAC_DMACR_PR_RR (3 << DMAC_DMACR_PR_BIT) /* round robin */ 786 #define DMAC_DMACR_PR_RR (3 << DMAC_DMACR_PR_BIT) /* round robin */
787#define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */ 787#define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */
788#define DMAC_DMACR_AR (1 << 2) /* address error flag */ 788#define DMAC_DMACR_AR (1 << 2) /* address error flag */
789#define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */ 789#define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */
790 790
791// DMA doorbell register 791// DMA doorbell register
792#define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */ 792#define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */
793#define DMAC_DMADBR_DB4 (1 << 5) /* doorbell for channel 4 */ 793#define DMAC_DMADBR_DB4 (1 << 5) /* doorbell for channel 4 */
794#define DMAC_DMADBR_DB3 (1 << 5) /* doorbell for channel 3 */ 794#define DMAC_DMADBR_DB3 (1 << 5) /* doorbell for channel 3 */
795#define DMAC_DMADBR_DB2 (1 << 5) /* doorbell for channel 2 */ 795#define DMAC_DMADBR_DB2 (1 << 5) /* doorbell for channel 2 */
796#define DMAC_DMADBR_DB1 (1 << 5) /* doorbell for channel 1 */ 796#define DMAC_DMADBR_DB1 (1 << 5) /* doorbell for channel 1 */
797#define DMAC_DMADBR_DB0 (1 << 5) /* doorbell for channel 0 */ 797#define DMAC_DMADBR_DB0 (1 << 5) /* doorbell for channel 0 */
798 798
799// DMA doorbell set register 799// DMA doorbell set register
800#define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */ 800#define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */
801#define DMAC_DMADBSR_DBS4 (1 << 5) /* enable doorbell for channel 4 */ 801#define DMAC_DMADBSR_DBS4 (1 << 5) /* enable doorbell for channel 4 */
802#define DMAC_DMADBSR_DBS3 (1 << 5) /* enable doorbell for channel 3 */ 802#define DMAC_DMADBSR_DBS3 (1 << 5) /* enable doorbell for channel 3 */
803#define DMAC_DMADBSR_DBS2 (1 << 5) /* enable doorbell for channel 2 */ 803#define DMAC_DMADBSR_DBS2 (1 << 5) /* enable doorbell for channel 2 */
804#define DMAC_DMADBSR_DBS1 (1 << 5) /* enable doorbell for channel 1 */ 804#define DMAC_DMADBSR_DBS1 (1 << 5) /* enable doorbell for channel 1 */
805#define DMAC_DMADBSR_DBS0 (1 << 5) /* enable doorbell for channel 0 */ 805#define DMAC_DMADBSR_DBS0 (1 << 5) /* enable doorbell for channel 0 */
806 806
807// DMA interrupt pending register 807// DMA interrupt pending register
808#define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */ 808#define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */
809#define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */ 809#define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */
810#define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */ 810#define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */
811#define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */ 811#define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */
812#define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */ 812#define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */
813#define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */ 813#define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */
814 814
815 815
816/************************************************************************* 816/*************************************************************************
817 * GPIO (General-Purpose I/O Ports) 817 * GPIO (General-Purpose I/O Ports)
818 *************************************************************************/ 818 *************************************************************************/
819#define MAX_GPIO_NUM 128 819#define MAX_GPIO_NUM 128
820 820
821//n = 0,1,2,3 821//n = 0,1,2,3
822#define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */ 822#define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
823#define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */ 823#define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
824#define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */ 824#define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
825#define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */ 825#define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
826#define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */ 826#define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
827#define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */ 827#define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
828#define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */ 828#define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
829#define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */ 829#define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */
830#define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */ 830#define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */
831#define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */ 831#define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */
832#define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */ 832#define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
833#define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */ 833#define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
834#define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */ 834#define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
835#define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */ 835#define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
836#define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */ 836#define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
837#define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */ 837#define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
838#define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */ 838#define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
839#define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */ 839#define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
840#define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */ 840#define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
841#define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */ 841#define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */
842#define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */ 842#define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */
843#define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */ 843#define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */
844#define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */ 844#define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */
845#define GPIO_PXFLGC(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Flag clear Register */ 845#define GPIO_PXFLGC(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Flag clear Register */
846 846
847#define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */ 847#define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */
848#define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */ 848#define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */
849#define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n))) 849#define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n)))
850#define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n))) 850#define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n)))
851#define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */ 851#define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */
852#define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n))) 852#define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n)))
853#define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n))) 853#define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n)))
854#define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */ 854#define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */
855#define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n))) 855#define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n)))
856#define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n))) 856#define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n)))
857#define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO or intr, 1:FUNC */ 857#define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO or intr, 1:FUNC */
858#define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n))) 858#define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n)))
859#define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n))) 859#define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n)))
860#define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/ 860#define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/
861#define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n))) 861#define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n)))
862#define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n))) 862#define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n)))
863#define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */ 863#define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */
864#define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n))) 864#define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n)))
865#define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n))) 865#define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n)))
866#define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:level-trigger, 1:edge-trigger */ 866#define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:level-trigger, 1:edge-trigger */
867#define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n))) 867#define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n)))
868#define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n))) 868#define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n)))
869#define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */ 869#define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */
870#define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC((n))) /* interrupt flag */ 870#define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC((n))) /* interrupt flag */
871 871
872 872
873/************************************************************************* 873/*************************************************************************
874 * UART 874 * UART
875 *************************************************************************/ 875 *************************************************************************/
876 876
877#define IRDA_BASE UART0_BASE 877#define IRDA_BASE UART0_BASE
878#define UART_BASE UART0_BASE 878#define UART_BASE UART0_BASE
879#define UART_OFF 0x1000 879#define UART_OFF 0x1000
880 880
881/* Register Offset */ 881/* Register Offset */
882#define OFF_RDR (0x00) /* R 8b H'xx */ 882#define OFF_RDR (0x00) /* R 8b H'xx */
883#define OFF_TDR (0x00) /* W 8b H'xx */ 883#define OFF_TDR (0x00) /* W 8b H'xx */
884#define OFF_DLLR (0x00) /* RW 8b H'00 */ 884#define OFF_DLLR (0x00) /* RW 8b H'00 */
885#define OFF_DLHR (0x04) /* RW 8b H'00 */ 885#define OFF_DLHR (0x04) /* RW 8b H'00 */
886#define OFF_IER (0x04) /* RW 8b H'00 */ 886#define OFF_IER (0x04) /* RW 8b H'00 */
887#define OFF_ISR (0x08) /* R 8b H'01 */ 887#define OFF_ISR (0x08) /* R 8b H'01 */
888#define OFF_FCR (0x08) /* W 8b H'00 */ 888#define OFF_FCR (0x08) /* W 8b H'00 */
889#define OFF_LCR (0x0C) /* RW 8b H'00 */ 889#define OFF_LCR (0x0C) /* RW 8b H'00 */
890#define OFF_MCR (0x10) /* RW 8b H'00 */ 890#define OFF_MCR (0x10) /* RW 8b H'00 */
891#define OFF_LSR (0x14) /* R 8b H'00 */ 891#define OFF_LSR (0x14) /* R 8b H'00 */
892#define OFF_MSR (0x18) /* R 8b H'00 */ 892#define OFF_MSR (0x18) /* R 8b H'00 */
893#define OFF_SPR (0x1C) /* RW 8b H'00 */ 893#define OFF_SPR (0x1C) /* RW 8b H'00 */
894#define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */ 894#define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */
895#define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */ 895#define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */
896#define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */ 896#define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */
897 897
898/* Register Address */ 898/* Register Address */
899#define UART0_RDR (UART0_BASE + OFF_RDR) 899#define UART0_RDR (UART0_BASE + OFF_RDR)
900#define UART0_TDR (UART0_BASE + OFF_TDR) 900#define UART0_TDR (UART0_BASE + OFF_TDR)
901#define UART0_DLLR (UART0_BASE + OFF_DLLR) 901#define UART0_DLLR (UART0_BASE + OFF_DLLR)
902#define UART0_DLHR (UART0_BASE + OFF_DLHR) 902#define UART0_DLHR (UART0_BASE + OFF_DLHR)
903#define UART0_IER (UART0_BASE + OFF_IER) 903#define UART0_IER (UART0_BASE + OFF_IER)
904#define UART0_ISR (UART0_BASE + OFF_ISR) 904#define UART0_ISR (UART0_BASE + OFF_ISR)
905#define UART0_FCR (UART0_BASE + OFF_FCR) 905#define UART0_FCR (UART0_BASE + OFF_FCR)
906#define UART0_LCR (UART0_BASE + OFF_LCR) 906#define UART0_LCR (UART0_BASE + OFF_LCR)
907#define UART0_MCR (UART0_BASE + OFF_MCR) 907#define UART0_MCR (UART0_BASE + OFF_MCR)
908#define UART0_LSR (UART0_BASE + OFF_LSR) 908#define UART0_LSR (UART0_BASE + OFF_LSR)
909#define UART0_MSR (UART0_BASE + OFF_MSR) 909#define UART0_MSR (UART0_BASE + OFF_MSR)
910#define UART0_SPR (UART0_BASE + OFF_SPR) 910#define UART0_SPR (UART0_BASE + OFF_SPR)
911#define UART0_SIRCR (UART0_BASE + OFF_SIRCR) 911#define UART0_SIRCR (UART0_BASE + OFF_SIRCR)
912#define UART0_UMR (UART0_BASE + OFF_UMR) 912#define UART0_UMR (UART0_BASE + OFF_UMR)
913#define UART0_UACR (UART0_BASE + OFF_UACR) 913#define UART0_UACR (UART0_BASE + OFF_UACR)
914 914
915/* 915/*
916 * Define macros for UART_IER 916 * Define macros for UART_IER
917 * UART Interrupt Enable Register 917 * UART Interrupt Enable Register
918 */ 918 */
919#define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */ 919#define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */
920#define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */ 920#define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */
921#define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */ 921#define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
922#define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */ 922#define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */
923#define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */ 923#define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
924 924
925/* 925/*
926 * Define macros for UART_ISR 926 * Define macros for UART_ISR
927 * UART Interrupt Status Register 927 * UART Interrupt Status Register
928 */ 928 */
929#define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */ 929#define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
930#define UART_ISR_IID (7 << 1) /* Source of Interrupt */ 930#define UART_ISR_IID (7 << 1) /* Source of Interrupt */
931#define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */ 931#define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */
932#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */ 932#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
933#define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */ 933#define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */
934#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */ 934#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
935#define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */ 935#define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */
936#define UART_ISR_FFMS_NO_FIFO (0 << 6) 936#define UART_ISR_FFMS_NO_FIFO (0 << 6)
937#define UART_ISR_FFMS_FIFO_MODE (3 << 6) 937#define UART_ISR_FFMS_FIFO_MODE (3 << 6)
938 938
939/* 939/*
940 * Define macros for UART_FCR 940 * Define macros for UART_FCR
941 * UART FIFO Control Register 941 * UART FIFO Control Register
942 */ 942 */
943#define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */ 943#define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
944#define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */ 944#define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
945#define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */ 945#define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
946#define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */ 946#define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */
947#define UART_FCR_UUE (1 << 4) /* 0: disable UART */ 947#define UART_FCR_UUE (1 << 4) /* 0: disable UART */
948#define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */ 948#define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
949#define UART_FCR_RTRG_1 (0 << 6) 949#define UART_FCR_RTRG_1 (0 << 6)
950#define UART_FCR_RTRG_4 (1 << 6) 950#define UART_FCR_RTRG_4 (1 << 6)
951#define UART_FCR_RTRG_8 (2 << 6) 951#define UART_FCR_RTRG_8 (2 << 6)
952#define UART_FCR_RTRG_15 (3 << 6) 952#define UART_FCR_RTRG_15 (3 << 6)
953 953
954/* 954/*
955 * Define macros for UART_LCR 955 * Define macros for UART_LCR
956 * UART Line Control Register 956 * UART Line Control Register
957 */ 957 */
958#define UART_LCR_WLEN (3 << 0) /* word length */ 958#define UART_LCR_WLEN (3 << 0) /* word length */
959#define UART_LCR_WLEN_5 (0 << 0) 959#define UART_LCR_WLEN_5 (0 << 0)
960#define UART_LCR_WLEN_6 (1 << 0) 960#define UART_LCR_WLEN_6 (1 << 0)
961#define UART_LCR_WLEN_7 (2 << 0) 961#define UART_LCR_WLEN_7 (2 << 0)
962#define UART_LCR_WLEN_8 (3 << 0) 962#define UART_LCR_WLEN_8 (3 << 0)
963#define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 963#define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
964 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ 964 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
965#define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 965#define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
966 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ 966 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
967#define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 967#define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
968 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ 968 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
969 969
970#define UART_LCR_PE (1 << 3) /* 0: parity disable */ 970#define UART_LCR_PE (1 << 3) /* 0: parity disable */
971#define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */ 971#define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
972#define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */ 972#define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */
973#define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */ 973#define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
974#define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */ 974#define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */
975 975
976/* 976/*
977 * Define macros for UART_LSR 977 * Define macros for UART_LSR
978 * UART Line Status Register 978 * UART Line Status Register
979 */ 979 */
980#define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */ 980#define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */
981#define UART_LSR_ORER (1 << 1) /* 0: no overrun error */ 981#define UART_LSR_ORER (1 << 1) /* 0: no overrun error */
982#define UART_LSR_PER (1 << 2) /* 0: no parity error */ 982#define UART_LSR_PER (1 << 2) /* 0: no parity error */
983#define UART_LSR_FER (1 << 3) /* 0; no framing error */ 983#define UART_LSR_FER (1 << 3) /* 0; no framing error */
984#define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */ 984#define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */
985#define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */ 985#define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */
986#define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */ 986#define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */
987#define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */ 987#define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */
988 988
989/* 989/*
990 * Define macros for UART_MCR 990 * Define macros for UART_MCR
991 * UART Modem Control Register 991 * UART Modem Control Register
992 */ 992 */
993#define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */ 993#define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */
994#define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */ 994#define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */
995#define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */ 995#define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */
996#define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */ 996#define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */
997#define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */ 997#define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
998#define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */ 998#define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */
999 999
1000/* 1000/*
1001 * Define macros for UART_MSR 1001 * Define macros for UART_MSR
1002 * UART Modem Status Register 1002 * UART Modem Status Register
1003 */ 1003 */
1004#define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */ 1004#define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */
1005#define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */ 1005#define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */
1006#define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */ 1006#define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */
1007#define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */ 1007#define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */
1008#define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */ 1008#define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */
1009#define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */ 1009#define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */
1010#define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */ 1010#define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */
1011#define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */ 1011#define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */
1012 1012
1013/* 1013/*
1014 * Define macros for SIRCR 1014 * Define macros for SIRCR
1015 * Slow IrDA Control Register 1015 * Slow IrDA Control Register
1016 */ 1016 */
1017#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */ 1017#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */
1018#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */ 1018#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */
1019#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length 1019#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
1020 1: 0 pulse width is 1.6us for 115.2Kbps */ 1020 1: 0 pulse width is 1.6us for 115.2Kbps */
1021#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */ 1021#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
1022#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */ 1022#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
1023 1023
1024 1024
1025/************************************************************************* 1025/*************************************************************************
1026 * AIC (AC97/I2S Controller) 1026 * AIC (AC97/I2S Controller)
1027 *************************************************************************/ 1027 *************************************************************************/
1028#define AIC_FR (AIC_BASE + 0x000) 1028#define AIC_FR (AIC_BASE + 0x000)
1029#define AIC_CR (AIC_BASE + 0x004) 1029#define AIC_CR (AIC_BASE + 0x004)
1030#define AIC_ACCR1 (AIC_BASE + 0x008) 1030#define AIC_ACCR1 (AIC_BASE + 0x008)
1031#define AIC_ACCR2 (AIC_BASE + 0x00C) 1031#define AIC_ACCR2 (AIC_BASE + 0x00C)
1032#define AIC_I2SCR (AIC_BASE + 0x010) 1032#define AIC_I2SCR (AIC_BASE + 0x010)
1033#define AIC_SR (AIC_BASE + 0x014) 1033#define AIC_SR (AIC_BASE + 0x014)
1034#define AIC_ACSR (AIC_BASE + 0x018) 1034#define AIC_ACSR (AIC_BASE + 0x018)
1035#define AIC_I2SSR (AIC_BASE + 0x01C) 1035#define AIC_I2SSR (AIC_BASE + 0x01C)
1036#define AIC_ACCAR (AIC_BASE + 0x020) 1036#define AIC_ACCAR (AIC_BASE + 0x020)
1037#define AIC_ACCDR (AIC_BASE + 0x024) 1037#define AIC_ACCDR (AIC_BASE + 0x024)
1038#define AIC_ACSAR (AIC_BASE + 0x028) 1038#define AIC_ACSAR (AIC_BASE + 0x028)
1039#define AIC_ACSDR (AIC_BASE + 0x02C) 1039#define AIC_ACSDR (AIC_BASE + 0x02C)
1040#define AIC_I2SDIV (AIC_BASE + 0x030) 1040#define AIC_I2SDIV (AIC_BASE + 0x030)
1041#define AIC_DR (AIC_BASE + 0x034) 1041#define AIC_DR (AIC_BASE + 0x034)
1042 1042
1043#define REG_AIC_FR REG32(AIC_FR) 1043#define REG_AIC_FR REG32(AIC_FR)
1044#define REG_AIC_CR REG32(AIC_CR) 1044#define REG_AIC_CR REG32(AIC_CR)
1045#define REG_AIC_ACCR1 REG32(AIC_ACCR1) 1045#define REG_AIC_ACCR1 REG32(AIC_ACCR1)
1046#define REG_AIC_ACCR2 REG32(AIC_ACCR2) 1046#define REG_AIC_ACCR2 REG32(AIC_ACCR2)
1047#define REG_AIC_I2SCR REG32(AIC_I2SCR) 1047#define REG_AIC_I2SCR REG32(AIC_I2SCR)
1048#define REG_AIC_SR REG32(AIC_SR) 1048#define REG_AIC_SR REG32(AIC_SR)
1049#define REG_AIC_ACSR REG32(AIC_ACSR) 1049#define REG_AIC_ACSR REG32(AIC_ACSR)
1050#define REG_AIC_I2SSR REG32(AIC_I2SSR) 1050#define REG_AIC_I2SSR REG32(AIC_I2SSR)
1051#define REG_AIC_ACCAR REG32(AIC_ACCAR) 1051#define REG_AIC_ACCAR REG32(AIC_ACCAR)
1052#define REG_AIC_ACCDR REG32(AIC_ACCDR) 1052#define REG_AIC_ACCDR REG32(AIC_ACCDR)
1053#define REG_AIC_ACSAR REG32(AIC_ACSAR) 1053#define REG_AIC_ACSAR REG32(AIC_ACSAR)
1054#define REG_AIC_ACSDR REG32(AIC_ACSDR) 1054#define REG_AIC_ACSDR REG32(AIC_ACSDR)
1055#define REG_AIC_I2SDIV REG32(AIC_I2SDIV) 1055#define REG_AIC_I2SDIV REG32(AIC_I2SDIV)
1056#define REG_AIC_DR REG32(AIC_DR) 1056#define REG_AIC_DR REG32(AIC_DR)
1057 1057
1058/* AIC Controller Configuration Register (AIC_FR) */ 1058/* AIC Controller Configuration Register (AIC_FR) */
1059 1059
1060#define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */ 1060#define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */
1061#define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT) 1061#define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT)
1062#define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */ 1062#define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */
1063#define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT) 1063#define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT)
1064#define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */ 1064#define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */
1065#define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */ 1065#define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */
1066#define AIC_FR_RST (1 << 3) /* AIC registers reset */ 1066#define AIC_FR_RST (1 << 3) /* AIC registers reset */
1067#define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */ 1067#define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */
1068#define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */ 1068#define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */
1069#define AIC_FR_ENB (1 << 0) /* AIC enable bit */ 1069#define AIC_FR_ENB (1 << 0) /* AIC enable bit */
1070 1070
1071/* AIC Controller Common Control Register (AIC_CR) */ 1071/* AIC Controller Common Control Register (AIC_CR) */
1072 1072
1073#define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */ 1073#define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */
1074#define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT) 1074#define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT)
1075 #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT) 1075 #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT)
1076 #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT) 1076 #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT)
1077 #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT) 1077 #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT)
1078 #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT) 1078 #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT)
1079 #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT) 1079 #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT)
1080#define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */ 1080#define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */
1081#define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT) 1081#define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT)
1082 #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT) 1082 #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT)
1083 #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT) 1083 #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT)
1084 #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT) 1084 #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT)
1085 #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT) 1085 #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT)
1086 #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT) 1086 #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT)
1087#define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */ 1087#define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */
1088#define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */ 1088#define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */
1089#define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */ 1089#define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */
1090#define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */ 1090#define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */
1091#define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */ 1091#define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */
1092#define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */ 1092#define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */
1093#define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */ 1093#define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */
1094#define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */ 1094#define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */
1095#define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */ 1095#define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */
1096#define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */ 1096#define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */
1097#define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */ 1097#define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */
1098#define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */ 1098#define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */
1099#define AIC_CR_EREC (1 << 0) /* Enable Record Function */ 1099#define AIC_CR_EREC (1 << 0) /* Enable Record Function */
1100 1100
1101/* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */ 1101/* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */
1102 1102
1103#define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */ 1103#define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */
1104#define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT) 1104#define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT)
1105 #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */ 1105 #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */
1106 #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */ 1106 #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */
1107 #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */ 1107 #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */
1108 #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */ 1108 #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */
1109 #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */ 1109 #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */
1110 #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */ 1110 #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */
1111 #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */ 1111 #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */
1112 #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */ 1112 #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */
1113 #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */ 1113 #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */
1114 #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */ 1114 #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */
1115#define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */ 1115#define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */
1116#define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT) 1116#define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT)
1117 #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */ 1117 #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */
1118 #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */ 1118 #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */
1119 #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */ 1119 #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */
1120 #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */ 1120 #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */
1121 #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */ 1121 #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */
1122 #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */ 1122 #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */
1123 #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */ 1123 #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */
1124 #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */ 1124 #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */
1125 #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */ 1125 #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */
1126 #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */ 1126 #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */
1127 1127
1128/* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */ 1128/* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */
1129 1129
1130#define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */ 1130#define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */
1131#define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */ 1131#define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */
1132#define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */ 1132#define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */
1133#define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */ 1133#define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */
1134#define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT) 1134#define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT)
1135 #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */ 1135 #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */
1136 #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */ 1136 #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */
1137 #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */ 1137 #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */
1138 #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */ 1138 #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */
1139#define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */ 1139#define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */
1140#define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT) 1140#define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT)
1141 #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */ 1141 #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */
1142 #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */ 1142 #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */
1143 #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */ 1143 #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */
1144 #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */ 1144 #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */
1145#define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */ 1145#define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */
1146#define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */ 1146#define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */
1147#define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */ 1147#define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */
1148#define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */ 1148#define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */
1149 1149
1150/* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */ 1150/* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */
1151 1151
1152#define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */ 1152#define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */
1153#define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */ 1153#define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */
1154#define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT) 1154#define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT)
1155 #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */ 1155 #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */
1156 #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */ 1156 #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */
1157 #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */ 1157 #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */
1158 #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */ 1158 #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */
1159 #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */ 1159 #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */
1160#define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */ 1160#define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */
1161 1161
1162/* AIC Controller FIFO Status Register (AIC_SR) */ 1162/* AIC Controller FIFO Status Register (AIC_SR) */
1163 1163
1164#define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */ 1164#define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */
1165#define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT) 1165#define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT)
1166#define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */ 1166#define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */
1167#define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT) 1167#define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT)
1168#define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */ 1168#define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */
1169#define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */ 1169#define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */
1170#define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */ 1170#define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */
1171#define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */ 1171#define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */
1172 1172
1173/* AIC Controller AC-link Status Register (AIC_ACSR) */ 1173/* AIC Controller AC-link Status Register (AIC_ACSR) */
1174 1174
1175#define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */ 1175#define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */
1176#define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */ 1176#define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */
1177#define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */ 1177#define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */
1178#define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */ 1178#define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */
1179#define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */ 1179#define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */
1180#define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */ 1180#define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */
1181 1181
1182/* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */ 1182/* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */
1183 1183
1184#define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */ 1184#define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */
1185 1185
1186/* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */ 1186/* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */
1187 1187
1188#define AIC_ACCAR_CAR_BIT 0 1188#define AIC_ACCAR_CAR_BIT 0
1189#define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT) 1189#define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT)
1190 1190
1191/* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */ 1191/* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */
1192 1192
1193#define AIC_ACCDR_CDR_BIT 0 1193#define AIC_ACCDR_CDR_BIT 0
1194#define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT) 1194#define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT)
1195 1195
1196/* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */ 1196/* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */
1197 1197
1198#define AIC_ACSAR_SAR_BIT 0 1198#define AIC_ACSAR_SAR_BIT 0
1199#define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT) 1199#define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT)
1200 1200
1201/* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */ 1201/* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */
1202 1202
1203#define AIC_ACSDR_SDR_BIT 0 1203#define AIC_ACSDR_SDR_BIT 0
1204#define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT) 1204#define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT)
1205 1205
1206/* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */ 1206/* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */
1207 1207
1208#define AIC_I2SDIV_DIV_BIT 0 1208#define AIC_I2SDIV_DIV_BIT 0
1209#define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT) 1209#define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT)
1210 #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */ 1210 #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */
1211 #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */ 1211 #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */
1212 #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */ 1212 #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */
1213 #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */ 1213 #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */
1214 #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */ 1214 #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */
1215 #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */ 1215 #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */
1216 1216
1217 1217
1218/************************************************************************* 1218/*************************************************************************
1219 * ICDC (Internal CODEC) 1219 * ICDC (Internal CODEC)
1220 *************************************************************************/ 1220 *************************************************************************/
1221#define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */ 1221#define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */
1222#define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */ 1222#define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */
1223#define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */ 1223#define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */
1224#define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */ 1224#define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */
1225#define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */ 1225#define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */
1226#define ICDC_CDCCR1 (ICDC_BASE + 0x0080) 1226#define ICDC_CDCCR1 (ICDC_BASE + 0x0080)
1227#define ICDC_CDCCR2 (ICDC_BASE + 0x0084) 1227#define ICDC_CDCCR2 (ICDC_BASE + 0x0084)
1228 1228
1229#define REG_ICDC_CR REG32(ICDC_CR) 1229#define REG_ICDC_CR REG32(ICDC_CR)
1230#define REG_ICDC_APWAIT REG32(ICDC_APWAIT) 1230#define REG_ICDC_APWAIT REG32(ICDC_APWAIT)
1231#define REG_ICDC_APPRE REG32(ICDC_APPRE) 1231#define REG_ICDC_APPRE REG32(ICDC_APPRE)
1232#define REG_ICDC_APHPEN REG32(ICDC_APHPEN) 1232#define REG_ICDC_APHPEN REG32(ICDC_APHPEN)
1233#define REG_ICDC_APSR REG32(ICDC_APSR) 1233#define REG_ICDC_APSR REG32(ICDC_APSR)
1234#define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1) 1234#define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1)
1235#define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2) 1235#define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2)
1236 1236
1237/* ICDC Control Register */ 1237/* ICDC Control Register */
1238#define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */ 1238#define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */
1239#define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT) 1239#define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT)
1240#define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */ 1240#define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */
1241#define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT) 1241#define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT)
1242 #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT) 1242 #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT)
1243 #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT) 1243 #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT)
1244 #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT) 1244 #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT)
1245 #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT) 1245 #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT)
1246 #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT) 1246 #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT)
1247 #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT) 1247 #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT)
1248 #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT) 1248 #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT)
1249 #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT) 1249 #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT)
1250 #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT) 1250 #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT)
1251#define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */ 1251#define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */
1252#define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT) 1252#define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT)
1253 #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT) 1253 #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT)
1254 #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT) 1254 #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT)
1255 #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT) 1255 #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT)
1256 #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT) 1256 #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT)
1257#define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */ 1257#define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */
1258#define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT) 1258#define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT)
1259 #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT) 1259 #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT)
1260 #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT) 1260 #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT)
1261 #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT) 1261 #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT)
1262 #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT) 1262 #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT)
1263#define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */ 1263#define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */
1264#define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */ 1264#define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */
1265#define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */ 1265#define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */
1266#define ICDC_CR_EADC (1 << 10) /* Enable ADC */ 1266#define ICDC_CR_EADC (1 << 10) /* Enable ADC */
1267#define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */ 1267#define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */
1268#define ICDC_CR_EDAC (1 << 8) /* Enable DAC */ 1268#define ICDC_CR_EDAC (1 << 8) /* Enable DAC */
1269#define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */ 1269#define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */
1270#define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */ 1270#define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */
1271#define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */ 1271#define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */
1272#define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */ 1272#define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */
1273#define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */ 1273#define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */
1274#define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */ 1274#define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */
1275 1275
1276/* Anti-Pop WAIT Stage Timing Control Register */ 1276/* Anti-Pop WAIT Stage Timing Control Register */
1277#define ICDC_APWAIT_WAITSN_BIT 0 1277#define ICDC_APWAIT_WAITSN_BIT 0
1278#define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT) 1278#define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT)
1279 1279
1280/* Anti-Pop HPEN-PRE Stage Timing Control Register */ 1280/* Anti-Pop HPEN-PRE Stage Timing Control Register */
1281#define ICDC_APPRE_PRESN_BIT 0 1281#define ICDC_APPRE_PRESN_BIT 0
1282#define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT) 1282#define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT)
1283 1283
1284/* Anti-Pop HPEN Stage Timing Control Register */ 1284/* Anti-Pop HPEN Stage Timing Control Register */
1285#define ICDC_APHPEN_HPENSN_BIT 0 1285#define ICDC_APHPEN_HPENSN_BIT 0
1286#define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT) 1286#define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT)
1287 1287
1288/* Anti-Pop Status Register */ 1288/* Anti-Pop Status Register */
1289#define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */ 1289#define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */
1290#define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT) 1290#define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT)
1291#define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */ 1291#define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */
1292#define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */ 1292#define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */
1293 #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */ 1293 #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */
1294#define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */ 1294#define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */
1295 #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */ 1295 #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */
1296 #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */ 1296 #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */
1297 #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */ 1297 #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */
1298 #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */ 1298 #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */
1299#define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */ 1299#define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */
1300#define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT) 1300#define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT)
1301 1301
1302 1302
1303/************************************************************************* 1303/*************************************************************************
1304 * I2C 1304 * I2C
1305 *************************************************************************/ 1305 *************************************************************************/
1306#define I2C_DR (I2C_BASE + 0x000) 1306#define I2C_DR (I2C_BASE + 0x000)
1307#define I2C_CR (I2C_BASE + 0x004) 1307#define I2C_CR (I2C_BASE + 0x004)
1308#define I2C_SR (I2C_BASE + 0x008) 1308#define I2C_SR (I2C_BASE + 0x008)
1309#define I2C_GR (I2C_BASE + 0x00C) 1309#define I2C_GR (I2C_BASE + 0x00C)
1310 1310
1311#define REG_I2C_DR REG8(I2C_DR) 1311#define REG_I2C_DR REG8(I2C_DR)
1312#define REG_I2C_CR REG8(I2C_CR) 1312#define REG_I2C_CR REG8(I2C_CR)
1313#define REG_I2C_SR REG8(I2C_SR) 1313#define REG_I2C_SR REG8(I2C_SR)
1314#define REG_I2C_GR REG16(I2C_GR) 1314#define REG_I2C_GR REG16(I2C_GR)
1315 1315
1316/* I2C Control Register (I2C_CR) */ 1316/* I2C Control Register (I2C_CR) */
1317 1317
1318#define I2C_CR_IEN (1 << 4) 1318#define I2C_CR_IEN (1 << 4)
1319#define I2C_CR_STA (1 << 3) 1319#define I2C_CR_STA (1 << 3)
1320#define I2C_CR_STO (1 << 2) 1320#define I2C_CR_STO (1 << 2)
1321#define I2C_CR_AC (1 << 1) 1321#define I2C_CR_AC (1 << 1)
1322#define I2C_CR_I2CE (1 << 0) 1322#define I2C_CR_I2CE (1 << 0)
1323 1323
1324/* I2C Status Register (I2C_SR) */ 1324/* I2C Status Register (I2C_SR) */
1325 1325
1326#define I2C_SR_STX (1 << 4) 1326#define I2C_SR_STX (1 << 4)
1327#define I2C_SR_BUSY (1 << 3) 1327#define I2C_SR_BUSY (1 << 3)
1328#define I2C_SR_TEND (1 << 2) 1328#define I2C_SR_TEND (1 << 2)
1329#define I2C_SR_DRF (1 << 1) 1329#define I2C_SR_DRF (1 << 1)
1330#define I2C_SR_ACKF (1 << 0) 1330#define I2C_SR_ACKF (1 << 0)
1331 1331
1332 1332
1333/************************************************************************* 1333/*************************************************************************
1334 * SSI 1334 * SSI
1335 *************************************************************************/ 1335 *************************************************************************/
1336#define SSI_DR (SSI_BASE + 0x000) 1336#define SSI_DR (SSI_BASE + 0x000)
1337#define SSI_CR0 (SSI_BASE + 0x004) 1337#define SSI_CR0 (SSI_BASE + 0x004)
1338#define SSI_CR1 (SSI_BASE + 0x008) 1338#define SSI_CR1 (SSI_BASE + 0x008)
1339#define SSI_SR (SSI_BASE + 0x00C) 1339#define SSI_SR (SSI_BASE + 0x00C)
1340#define SSI_ITR (SSI_BASE + 0x010) 1340#define SSI_ITR (SSI_BASE + 0x010)
1341#define SSI_ICR (SSI_BASE + 0x014) 1341#define SSI_ICR (SSI_BASE + 0x014)
1342#define SSI_GR (SSI_BASE + 0x018) 1342#define SSI_GR (SSI_BASE + 0x018)
1343 1343
1344#define REG_SSI_DR REG32(SSI_DR) 1344#define REG_SSI_DR REG32(SSI_DR)
1345#define REG_SSI_CR0 REG16(SSI_CR0) 1345#define REG_SSI_CR0 REG16(SSI_CR0)
1346#define REG_SSI_CR1 REG32(SSI_CR1) 1346#define REG_SSI_CR1 REG32(SSI_CR1)
1347#define REG_SSI_SR REG32(SSI_SR) 1347#define REG_SSI_SR REG32(SSI_SR)
1348#define REG_SSI_ITR REG16(SSI_ITR) 1348#define REG_SSI_ITR REG16(SSI_ITR)
1349#define REG_SSI_ICR REG8(SSI_ICR) 1349#define REG_SSI_ICR REG8(SSI_ICR)
1350#define REG_SSI_GR REG16(SSI_GR) 1350#define REG_SSI_GR REG16(SSI_GR)
1351 1351
1352/* SSI Data Register (SSI_DR) */ 1352/* SSI Data Register (SSI_DR) */
1353 1353
1354#define SSI_DR_GPC_BIT 0 1354#define SSI_DR_GPC_BIT 0
1355#define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT) 1355#define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT)
1356 1356
1357/* SSI Control Register 0 (SSI_CR0) */ 1357/* SSI Control Register 0 (SSI_CR0) */
1358 1358
1359#define SSI_CR0_SSIE (1 << 15) 1359#define SSI_CR0_SSIE (1 << 15)
1360#define SSI_CR0_TIE (1 << 14) 1360#define SSI_CR0_TIE (1 << 14)
1361#define SSI_CR0_RIE (1 << 13) 1361#define SSI_CR0_RIE (1 << 13)
1362#define SSI_CR0_TEIE (1 << 12) 1362#define SSI_CR0_TEIE (1 << 12)
1363#define SSI_CR0_REIE (1 << 11) 1363#define SSI_CR0_REIE (1 << 11)
1364#define SSI_CR0_LOOP (1 << 10) 1364#define SSI_CR0_LOOP (1 << 10)
1365#define SSI_CR0_RFINE (1 << 9) 1365#define SSI_CR0_RFINE (1 << 9)
1366#define SSI_CR0_RFINC (1 << 8) 1366#define SSI_CR0_RFINC (1 << 8)
1367#define SSI_CR0_FSEL (1 << 6) 1367#define SSI_CR0_FSEL (1 << 6)
1368#define SSI_CR0_TFLUSH (1 << 2) 1368#define SSI_CR0_TFLUSH (1 << 2)
1369#define SSI_CR0_RFLUSH (1 << 1) 1369#define SSI_CR0_RFLUSH (1 << 1)
1370#define SSI_CR0_DISREV (1 << 0) 1370#define SSI_CR0_DISREV (1 << 0)
1371 1371
1372/* SSI Control Register 1 (SSI_CR1) */ 1372/* SSI Control Register 1 (SSI_CR1) */
1373 1373
1374#define SSI_CR1_FRMHL_BIT 30 1374#define SSI_CR1_FRMHL_BIT 30
1375#define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT) 1375#define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT)
1376 #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */ 1376 #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */
1377 #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */ 1377 #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */
1378 #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */ 1378 #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */
1379 #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */ 1379 #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */
1380#define SSI_CR1_TFVCK_BIT 28 1380#define SSI_CR1_TFVCK_BIT 28
1381#define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT) 1381#define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT)
1382 #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT) 1382 #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT)
1383 #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT) 1383 #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT)
1384 #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT) 1384 #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT)
1385 #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT) 1385 #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT)
1386#define SSI_CR1_TCKFI_BIT 26 1386#define SSI_CR1_TCKFI_BIT 26
1387#define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT) 1387#define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT)
1388 #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT) 1388 #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT)
1389 #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT) 1389 #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT)
1390 #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT) 1390 #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT)
1391 #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT) 1391 #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT)
1392#define SSI_CR1_LFST (1 << 25) 1392#define SSI_CR1_LFST (1 << 25)
1393#define SSI_CR1_ITFRM (1 << 24) 1393#define SSI_CR1_ITFRM (1 << 24)
1394#define SSI_CR1_UNFIN (1 << 23) 1394#define SSI_CR1_UNFIN (1 << 23)
1395#define SSI_CR1_MULTS (1 << 22) 1395#define SSI_CR1_MULTS (1 << 22)
1396#define SSI_CR1_FMAT_BIT 20 1396#define SSI_CR1_FMAT_BIT 20
1397#define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT) 1397#define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT)
1398 #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */ 1398 #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */
1399 #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */ 1399 #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */
1400 #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ 1400 #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */
1401 #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ 1401 #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */
1402#define SSI_CR1_TTRG_BIT 16 1402#define SSI_CR1_TTRG_BIT 16
1403#define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT) 1403#define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT)
1404 #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT) 1404 #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT)
1405 #define SSI_CR1_TTRG_8 (1 << SSI_CR1_TTRG_BIT) 1405 #define SSI_CR1_TTRG_8 (1 << SSI_CR1_TTRG_BIT)
1406 #define SSI_CR1_TTRG_16 (2 << SSI_CR1_TTRG_BIT) 1406 #define SSI_CR1_TTRG_16 (2 << SSI_CR1_TTRG_BIT)
1407 #define SSI_CR1_TTRG_24 (3 << SSI_CR1_TTRG_BIT) 1407 #define SSI_CR1_TTRG_24 (3 << SSI_CR1_TTRG_BIT)
1408 #define SSI_CR1_TTRG_32 (4 << SSI_CR1_TTRG_BIT) 1408 #define SSI_CR1_TTRG_32 (4 << SSI_CR1_TTRG_BIT)
1409 #define SSI_CR1_TTRG_40 (5 << SSI_CR1_TTRG_BIT) 1409 #define SSI_CR1_TTRG_40 (5 << SSI_CR1_TTRG_BIT)
1410 #define SSI_CR1_TTRG_48 (6 << SSI_CR1_TTRG_BIT) 1410 #define SSI_CR1_TTRG_48 (6 << SSI_CR1_TTRG_BIT)
1411 #define SSI_CR1_TTRG_56 (7 << SSI_CR1_TTRG_BIT) 1411 #define SSI_CR1_TTRG_56 (7 << SSI_CR1_TTRG_BIT)
1412 #define SSI_CR1_TTRG_64 (8 << SSI_CR1_TTRG_BIT) 1412 #define SSI_CR1_TTRG_64 (8 << SSI_CR1_TTRG_BIT)
1413 #define SSI_CR1_TTRG_72 (9 << SSI_CR1_TTRG_BIT) 1413 #define SSI_CR1_TTRG_72 (9 << SSI_CR1_TTRG_BIT)
1414 #define SSI_CR1_TTRG_80 (10<< SSI_CR1_TTRG_BIT) 1414 #define SSI_CR1_TTRG_80 (10<< SSI_CR1_TTRG_BIT)
1415 #define SSI_CR1_TTRG_88 (11<< SSI_CR1_TTRG_BIT) 1415 #define SSI_CR1_TTRG_88 (11<< SSI_CR1_TTRG_BIT)
1416 #define SSI_CR1_TTRG_96 (12<< SSI_CR1_TTRG_BIT) 1416 #define SSI_CR1_TTRG_96 (12<< SSI_CR1_TTRG_BIT)
1417 #define SSI_CR1_TTRG_104 (13<< SSI_CR1_TTRG_BIT) 1417 #define SSI_CR1_TTRG_104 (13<< SSI_CR1_TTRG_BIT)
1418 #define SSI_CR1_TTRG_112 (14<< SSI_CR1_TTRG_BIT) 1418 #define SSI_CR1_TTRG_112 (14<< SSI_CR1_TTRG_BIT)
1419 #define SSI_CR1_TTRG_120 (15<< SSI_CR1_TTRG_BIT) 1419 #define SSI_CR1_TTRG_120 (15<< SSI_CR1_TTRG_BIT)
1420#define SSI_CR1_MCOM_BIT 12 1420#define SSI_CR1_MCOM_BIT 12
1421#define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT) 1421#define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT)
1422 #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */ 1422 #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */
1423 #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */ 1423 #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */
1424 #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */ 1424 #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */
1425 #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */ 1425 #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */
1426 #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */ 1426 #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */
1427 #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */ 1427 #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */
1428 #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */ 1428 #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */
1429 #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */ 1429 #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */
1430 #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */ 1430 #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */
1431 #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */ 1431 #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */
1432 #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */ 1432 #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */
1433 #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */ 1433 #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */
1434 #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */ 1434 #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */
1435 #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */ 1435 #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */
1436 #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */ 1436 #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */
1437 #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */ 1437 #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */
1438#define SSI_CR1_RTRG_BIT 8 1438#define SSI_CR1_RTRG_BIT 8
1439#define SSI_CR1_RTRG_MASK (0xf << SSI_CR1_RTRG_BIT) 1439#define SSI_CR1_RTRG_MASK (0xf << SSI_CR1_RTRG_BIT)
1440 #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT) 1440 #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT)
1441 #define SSI_CR1_RTRG_8 (1 << SSI_CR1_RTRG_BIT) 1441 #define SSI_CR1_RTRG_8 (1 << SSI_CR1_RTRG_BIT)
1442 #define SSI_CR1_RTRG_16 (2 << SSI_CR1_RTRG_BIT) 1442 #define SSI_CR1_RTRG_16 (2 << SSI_CR1_RTRG_BIT)
1443 #define SSI_CR1_RTRG_24 (3 << SSI_CR1_RTRG_BIT) 1443 #define SSI_CR1_RTRG_24 (3 << SSI_CR1_RTRG_BIT)
1444 #define SSI_CR1_RTRG_32 (4 << SSI_CR1_RTRG_BIT) 1444 #define SSI_CR1_RTRG_32 (4 << SSI_CR1_RTRG_BIT)
1445 #define SSI_CR1_RTRG_40 (5 << SSI_CR1_RTRG_BIT) 1445 #define SSI_CR1_RTRG_40 (5 << SSI_CR1_RTRG_BIT)
1446 #define SSI_CR1_RTRG_48 (6 << SSI_CR1_RTRG_BIT) 1446 #define SSI_CR1_RTRG_48 (6 << SSI_CR1_RTRG_BIT)
1447 #define SSI_CR1_RTRG_56 (7 << SSI_CR1_RTRG_BIT) 1447 #define SSI_CR1_RTRG_56 (7 << SSI_CR1_RTRG_BIT)
1448 #define SSI_CR1_RTRG_64 (8 << SSI_CR1_RTRG_BIT) 1448 #define SSI_CR1_RTRG_64 (8 << SSI_CR1_RTRG_BIT)
1449 #define SSI_CR1_RTRG_72 (9 << SSI_CR1_RTRG_BIT) 1449 #define SSI_CR1_RTRG_72 (9 << SSI_CR1_RTRG_BIT)
1450 #define SSI_CR1_RTRG_80 (10<< SSI_CR1_RTRG_BIT) 1450 #define SSI_CR1_RTRG_80 (10<< SSI_CR1_RTRG_BIT)
1451 #define SSI_CR1_RTRG_88 (11<< SSI_CR1_RTRG_BIT) 1451 #define SSI_CR1_RTRG_88 (11<< SSI_CR1_RTRG_BIT)
1452 #define SSI_CR1_RTRG_96 (12<< SSI_CR1_RTRG_BIT) 1452 #define SSI_CR1_RTRG_96 (12<< SSI_CR1_RTRG_BIT)
1453 #define SSI_CR1_RTRG_104 (13<< SSI_CR1_RTRG_BIT) 1453 #define SSI_CR1_RTRG_104 (13<< SSI_CR1_RTRG_BIT)
1454 #define SSI_CR1_RTRG_112 (14<< SSI_CR1_RTRG_BIT) 1454 #define SSI_CR1_RTRG_112 (14<< SSI_CR1_RTRG_BIT)
1455 #define SSI_CR1_RTRG_120 (15<< SSI_CR1_RTRG_BIT) 1455 #define SSI_CR1_RTRG_120 (15<< SSI_CR1_RTRG_BIT)
1456#define SSI_CR1_FLEN_BIT 4 1456#define SSI_CR1_FLEN_BIT 4
1457#define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT) 1457#define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT)
1458 #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT) 1458 #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT)
1459 #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT) 1459 #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT)
1460 #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT) 1460 #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT)
1461 #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT) 1461 #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT)
1462 #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT) 1462 #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT)
1463 #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT) 1463 #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT)
1464 #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT) 1464 #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT)
1465 #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT) 1465 #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT)
1466 #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT) 1466 #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT)
1467 #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT) 1467 #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT)
1468 #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT) 1468 #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT)
1469 #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT) 1469 #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT)
1470 #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT) 1470 #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT)
1471 #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT) 1471 #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT)
1472 #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT) 1472 #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT)
1473 #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT) 1473 #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT)
1474#define SSI_CR1_PHA (1 << 1) 1474#define SSI_CR1_PHA (1 << 1)
1475#define SSI_CR1_POL (1 << 0) 1475#define SSI_CR1_POL (1 << 0)
1476 1476
1477/* SSI Status Register (SSI_SR) */ 1477/* SSI Status Register (SSI_SR) */
1478 1478
1479#define SSI_SR_TFIFONUM_BIT 16 1479#define SSI_SR_TFIFONUM_BIT 16
1480#define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT) 1480#define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT)
1481#define SSI_SR_RFIFONUM_BIT 8 1481#define SSI_SR_RFIFONUM_BIT 8
1482#define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT) 1482#define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT)
1483#define SSI_SR_END (1 << 7) 1483#define SSI_SR_END (1 << 7)
1484#define SSI_SR_BUSY (1 << 6) 1484#define SSI_SR_BUSY (1 << 6)
1485#define SSI_SR_TFF (1 << 5) 1485#define SSI_SR_TFF (1 << 5)
1486#define SSI_SR_RFE (1 << 4) 1486#define SSI_SR_RFE (1 << 4)
1487#define SSI_SR_TFHE (1 << 3) 1487#define SSI_SR_TFHE (1 << 3)
1488#define SSI_SR_RFHF (1 << 2) 1488#define SSI_SR_RFHF (1 << 2)
1489#define SSI_SR_UNDR (1 << 1) 1489#define SSI_SR_UNDR (1 << 1)
1490#define SSI_SR_OVER (1 << 0) 1490#define SSI_SR_OVER (1 << 0)
1491 1491
1492/* SSI Interval Time Control Register (SSI_ITR) */ 1492/* SSI Interval Time Control Register (SSI_ITR) */
1493 1493
1494#define SSI_ITR_CNTCLK (1 << 15) 1494#define SSI_ITR_CNTCLK (1 << 15)
1495#define SSI_ITR_IVLTM_BIT 0 1495#define SSI_ITR_IVLTM_BIT 0
1496#define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT) 1496#define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT)
1497 1497
1498 1498
1499/************************************************************************* 1499/*************************************************************************
1500 * MSC 1500 * MSC
1501 *************************************************************************/ 1501 *************************************************************************/
1502#define MSC_STRPCL (MSC_BASE + 0x000) 1502#define MSC_STRPCL (MSC_BASE + 0x000)
1503#define MSC_STAT (MSC_BASE + 0x004) 1503#define MSC_STAT (MSC_BASE + 0x004)
1504#define MSC_CLKRT (MSC_BASE + 0x008) 1504#define MSC_CLKRT (MSC_BASE + 0x008)
1505#define MSC_CMDAT (MSC_BASE + 0x00C) 1505#define MSC_CMDAT (MSC_BASE + 0x00C)
1506#define MSC_RESTO (MSC_BASE + 0x010) 1506#define MSC_RESTO (MSC_BASE + 0x010)
1507#define MSC_RDTO (MSC_BASE + 0x014) 1507#define MSC_RDTO (MSC_BASE + 0x014)
1508#define MSC_BLKLEN (MSC_BASE + 0x018) 1508#define MSC_BLKLEN (MSC_BASE + 0x018)
1509#define MSC_NOB (MSC_BASE + 0x01C) 1509#define MSC_NOB (MSC_BASE + 0x01C)
1510#define MSC_SNOB (MSC_BASE + 0x020) 1510#define MSC_SNOB (MSC_BASE + 0x020)
1511#define MSC_IMASK (MSC_BASE + 0x024) 1511#define MSC_IMASK (MSC_BASE + 0x024)
1512#define MSC_IREG (MSC_BASE + 0x028) 1512#define MSC_IREG (MSC_BASE + 0x028)
1513#define MSC_CMD (MSC_BASE + 0x02C) 1513#define MSC_CMD (MSC_BASE + 0x02C)
1514#define MSC_ARG (MSC_BASE + 0x030) 1514#define MSC_ARG (MSC_BASE + 0x030)
1515#define MSC_RES (MSC_BASE + 0x034) 1515#define MSC_RES (MSC_BASE + 0x034)
1516#define MSC_RXFIFO (MSC_BASE + 0x038) 1516#define MSC_RXFIFO (MSC_BASE + 0x038)
1517#define MSC_TXFIFO (MSC_BASE + 0x03C) 1517#define MSC_TXFIFO (MSC_BASE + 0x03C)
1518 1518
1519#define REG_MSC_STRPCL REG16(MSC_STRPCL) 1519#define REG_MSC_STRPCL REG16(MSC_STRPCL)
1520#define REG_MSC_STAT REG32(MSC_STAT) 1520#define REG_MSC_STAT REG32(MSC_STAT)
1521#define REG_MSC_CLKRT REG16(MSC_CLKRT) 1521#define REG_MSC_CLKRT REG16(MSC_CLKRT)
1522#define REG_MSC_CMDAT REG32(MSC_CMDAT) 1522#define REG_MSC_CMDAT REG32(MSC_CMDAT)
1523#define REG_MSC_RESTO REG16(MSC_RESTO) 1523#define REG_MSC_RESTO REG16(MSC_RESTO)
1524#define REG_MSC_RDTO REG16(MSC_RDTO) 1524#define REG_MSC_RDTO REG16(MSC_RDTO)
1525#define REG_MSC_BLKLEN REG16(MSC_BLKLEN) 1525#define REG_MSC_BLKLEN REG16(MSC_BLKLEN)
1526#define REG_MSC_NOB REG16(MSC_NOB) 1526#define REG_MSC_NOB REG16(MSC_NOB)
1527#define REG_MSC_SNOB REG16(MSC_SNOB) 1527#define REG_MSC_SNOB REG16(MSC_SNOB)
1528#define REG_MSC_IMASK REG16(MSC_IMASK) 1528#define REG_MSC_IMASK REG16(MSC_IMASK)
1529#define REG_MSC_IREG REG16(MSC_IREG) 1529#define REG_MSC_IREG REG16(MSC_IREG)
1530#define REG_MSC_CMD REG8(MSC_CMD) 1530#define REG_MSC_CMD REG8(MSC_CMD)
1531#define REG_MSC_ARG REG32(MSC_ARG) 1531#define REG_MSC_ARG REG32(MSC_ARG)
1532#define REG_MSC_RES REG16(MSC_RES) 1532#define REG_MSC_RES REG16(MSC_RES)
1533#define REG_MSC_RXFIFO REG32(MSC_RXFIFO) 1533#define REG_MSC_RXFIFO REG32(MSC_RXFIFO)
1534#define REG_MSC_TXFIFO REG32(MSC_TXFIFO) 1534#define REG_MSC_TXFIFO REG32(MSC_TXFIFO)
1535 1535
1536/* MSC Clock and Control Register (MSC_STRPCL) */ 1536/* MSC Clock and Control Register (MSC_STRPCL) */
1537 1537
1538#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) 1538#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7)
1539#define MSC_STRPCL_EXIT_TRANSFER (1 << 6) 1539#define MSC_STRPCL_EXIT_TRANSFER (1 << 6)
1540#define MSC_STRPCL_START_READWAIT (1 << 5) 1540#define MSC_STRPCL_START_READWAIT (1 << 5)
1541#define MSC_STRPCL_STOP_READWAIT (1 << 4) 1541#define MSC_STRPCL_STOP_READWAIT (1 << 4)
1542#define MSC_STRPCL_RESET (1 << 3) 1542#define MSC_STRPCL_RESET (1 << 3)
1543#define MSC_STRPCL_START_OP (1 << 2) 1543#define MSC_STRPCL_START_OP (1 << 2)
1544#define MSC_STRPCL_CLOCK_CONTROL_BIT 0 1544#define MSC_STRPCL_CLOCK_CONTROL_BIT 0
1545#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) 1545#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
1546 #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */ 1546 #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */
1547 #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */ 1547 #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */
1548 1548
1549/* MSC Status Register (MSC_STAT) */ 1549/* MSC Status Register (MSC_STAT) */
1550 1550
1551#define MSC_STAT_IS_RESETTING (1 << 15) 1551#define MSC_STAT_IS_RESETTING (1 << 15)
1552#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) 1552#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14)
1553#define MSC_STAT_PRG_DONE (1 << 13) 1553#define MSC_STAT_PRG_DONE (1 << 13)
1554#define MSC_STAT_DATA_TRAN_DONE (1 << 12) 1554#define MSC_STAT_DATA_TRAN_DONE (1 << 12)
1555#define MSC_STAT_END_CMD_RES (1 << 11) 1555#define MSC_STAT_END_CMD_RES (1 << 11)
1556#define MSC_STAT_DATA_FIFO_AFULL (1 << 10) 1556#define MSC_STAT_DATA_FIFO_AFULL (1 << 10)
1557#define MSC_STAT_IS_READWAIT (1 << 9) 1557#define MSC_STAT_IS_READWAIT (1 << 9)
1558#define MSC_STAT_CLK_EN (1 << 8) 1558#define MSC_STAT_CLK_EN (1 << 8)
1559#define MSC_STAT_DATA_FIFO_FULL (1 << 7) 1559#define MSC_STAT_DATA_FIFO_FULL (1 << 7)
1560#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) 1560#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6)
1561#define MSC_STAT_CRC_RES_ERR (1 << 5) 1561#define MSC_STAT_CRC_RES_ERR (1 << 5)
1562#define MSC_STAT_CRC_READ_ERROR (1 << 4) 1562#define MSC_STAT_CRC_READ_ERROR (1 << 4)
1563#define MSC_STAT_CRC_WRITE_ERROR_BIT 2 1563#define MSC_STAT_CRC_WRITE_ERROR_BIT 2
1564#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) 1564#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
1565 #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */ 1565 #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */
1566 #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */ 1566 #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */
1567 #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */ 1567 #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */
1568#define MSC_STAT_TIME_OUT_RES (1 << 1) 1568#define MSC_STAT_TIME_OUT_RES (1 << 1)
1569#define MSC_STAT_TIME_OUT_READ (1 << 0) 1569#define MSC_STAT_TIME_OUT_READ (1 << 0)
1570 1570
1571/* MSC Bus Clock Control Register (MSC_CLKRT) */ 1571/* MSC Bus Clock Control Register (MSC_CLKRT) */
1572 1572
1573#define MSC_CLKRT_CLK_RATE_BIT 0 1573#define MSC_CLKRT_CLK_RATE_BIT 0
1574#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT) 1574#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT)
1575 #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */ 1575 #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */
1576 #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */ 1576 #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */
1577 #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */ 1577 #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */
1578 #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */ 1578 #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */
1579 #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */ 1579 #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */
1580 #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */ 1580 #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */
1581 #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */ 1581 #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */
1582 #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */ 1582 #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */
1583 1583
1584/* MSC Command Sequence Control Register (MSC_CMDAT) */ 1584/* MSC Command Sequence Control Register (MSC_CMDAT) */
1585 1585
1586#define MSC_CMDAT_IO_ABORT (1 << 11) 1586#define MSC_CMDAT_IO_ABORT (1 << 11)
1587#define MSC_CMDAT_BUS_WIDTH_BIT 9 1587#define MSC_CMDAT_BUS_WIDTH_BIT 9
1588#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) 1588#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
1589 #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */ 1589 #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */
1590 #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */ 1590 #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */
1591 #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) 1591 #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
1592 #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) 1592 #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
1593#define MSC_CMDAT_DMA_EN (1 << 8) 1593#define MSC_CMDAT_DMA_EN (1 << 8)
1594#define MSC_CMDAT_INIT (1 << 7) 1594#define MSC_CMDAT_INIT (1 << 7)
1595#define MSC_CMDAT_BUSY (1 << 6) 1595#define MSC_CMDAT_BUSY (1 << 6)
1596#define MSC_CMDAT_STREAM_BLOCK (1 << 5) 1596#define MSC_CMDAT_STREAM_BLOCK (1 << 5)
1597#define MSC_CMDAT_WRITE (1 << 4) 1597#define MSC_CMDAT_WRITE (1 << 4)
1598#define MSC_CMDAT_READ (0 << 4) 1598#define MSC_CMDAT_READ (0 << 4)
1599#define MSC_CMDAT_DATA_EN (1 << 3) 1599#define MSC_CMDAT_DATA_EN (1 << 3)
1600#define MSC_CMDAT_RESPONSE_BIT 0 1600#define MSC_CMDAT_RESPONSE_BIT 0
1601#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT) 1601#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
1602 #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */ 1602 #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */
1603 #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */ 1603 #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */
1604 #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */ 1604 #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */
1605 #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */ 1605 #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */
1606 #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */ 1606 #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */
1607 #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */ 1607 #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */
1608 #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */ 1608 #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */
1609 1609
1610#define CMDAT_DMA_EN (1 << 8) 1610#define CMDAT_DMA_EN (1 << 8)
1611#define CMDAT_INIT (1 << 7) 1611#define CMDAT_INIT (1 << 7)
1612#define CMDAT_BUSY (1 << 6) 1612#define CMDAT_BUSY (1 << 6)
1613#define CMDAT_STREAM (1 << 5) 1613#define CMDAT_STREAM (1 << 5)
1614#define CMDAT_WRITE (1 << 4) 1614#define CMDAT_WRITE (1 << 4)
1615#define CMDAT_DATA_EN (1 << 3) 1615#define CMDAT_DATA_EN (1 << 3)
1616 1616
1617/* MSC Interrupts Mask Register (MSC_IMASK) */ 1617/* MSC Interrupts Mask Register (MSC_IMASK) */
1618 1618
1619#define MSC_IMASK_SDIO (1 << 7) 1619#define MSC_IMASK_SDIO (1 << 7)
1620#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) 1620#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6)
1621#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) 1621#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5)
1622#define MSC_IMASK_END_CMD_RES (1 << 2) 1622#define MSC_IMASK_END_CMD_RES (1 << 2)
1623#define MSC_IMASK_PRG_DONE (1 << 1) 1623#define MSC_IMASK_PRG_DONE (1 << 1)
1624#define MSC_IMASK_DATA_TRAN_DONE (1 << 0) 1624#define MSC_IMASK_DATA_TRAN_DONE (1 << 0)
1625 1625
1626 1626
1627/* MSC Interrupts Status Register (MSC_IREG) */ 1627/* MSC Interrupts Status Register (MSC_IREG) */
1628 1628
1629#define MSC_IREG_SDIO (1 << 7) 1629#define MSC_IREG_SDIO (1 << 7)
1630#define MSC_IREG_TXFIFO_WR_REQ (1 << 6) 1630#define MSC_IREG_TXFIFO_WR_REQ (1 << 6)
1631#define MSC_IREG_RXFIFO_RD_REQ (1 << 5) 1631#define MSC_IREG_RXFIFO_RD_REQ (1 << 5)
1632#define MSC_IREG_END_CMD_RES (1 << 2) 1632#define MSC_IREG_END_CMD_RES (1 << 2)
1633#define MSC_IREG_PRG_DONE (1 << 1) 1633#define MSC_IREG_PRG_DONE (1 << 1)
1634#define MSC_IREG_DATA_TRAN_DONE (1 << 0) 1634#define MSC_IREG_DATA_TRAN_DONE (1 << 0)
1635 1635
1636 1636
1637/************************************************************************* 1637/*************************************************************************
1638 * EMC (External Memory Controller) 1638 * EMC (External Memory Controller)
1639 *************************************************************************/ 1639 *************************************************************************/
1640#define EMC_BCR (EMC_BASE + 0x0) /* BCR */ 1640#define EMC_BCR (EMC_BASE + 0x0) /* BCR */
1641 1641
1642#define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */ 1642#define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */
1643#define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */ 1643#define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */
1644#define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */ 1644#define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */
1645#define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */ 1645#define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */
1646#define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */ 1646#define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */
1647#define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */ 1647#define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */
1648#define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */ 1648#define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */
1649#define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */ 1649#define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */
1650#define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */ 1650#define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */
1651#define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */ 1651#define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */
1652 1652
1653#define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */ 1653#define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */
1654#define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */ 1654#define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */
1655#define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */ 1655#define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */
1656#define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */ 1656#define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */
1657#define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */ 1657#define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */
1658#define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */ 1658#define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */
1659#define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */ 1659#define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */
1660#define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */ 1660#define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */
1661#define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */ 1661#define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */
1662#define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */ 1662#define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */
1663#define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */ 1663#define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */
1664#define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */ 1664#define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */
1665 1665
1666#define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */ 1666#define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */
1667#define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */ 1667#define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */
1668#define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */ 1668#define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */
1669#define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */ 1669#define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */
1670#define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */ 1670#define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */
1671#define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */ 1671#define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */
1672 1672
1673#define REG_EMC_BCR REG32(EMC_BCR) 1673#define REG_EMC_BCR REG32(EMC_BCR)
1674 1674
1675#define REG_EMC_SMCR0 REG32(EMC_SMCR0) 1675#define REG_EMC_SMCR0 REG32(EMC_SMCR0)
1676#define REG_EMC_SMCR1 REG32(EMC_SMCR1) 1676#define REG_EMC_SMCR1 REG32(EMC_SMCR1)
1677#define REG_EMC_SMCR2 REG32(EMC_SMCR2) 1677#define REG_EMC_SMCR2 REG32(EMC_SMCR2)
1678#define REG_EMC_SMCR3 REG32(EMC_SMCR3) 1678#define REG_EMC_SMCR3 REG32(EMC_SMCR3)
1679#define REG_EMC_SMCR4 REG32(EMC_SMCR4) 1679#define REG_EMC_SMCR4 REG32(EMC_SMCR4)
1680#define REG_EMC_SACR0 REG32(EMC_SACR0) 1680#define REG_EMC_SACR0 REG32(EMC_SACR0)
1681#define REG_EMC_SACR1 REG32(EMC_SACR1) 1681#define REG_EMC_SACR1 REG32(EMC_SACR1)
1682#define REG_EMC_SACR2 REG32(EMC_SACR2) 1682#define REG_EMC_SACR2 REG32(EMC_SACR2)
1683#define REG_EMC_SACR3 REG32(EMC_SACR3) 1683#define REG_EMC_SACR3 REG32(EMC_SACR3)
1684#define REG_EMC_SACR4 REG32(EMC_SACR4) 1684#define REG_EMC_SACR4 REG32(EMC_SACR4)
1685 1685
1686#define REG_EMC_NFCSR REG32(EMC_NFCSR) 1686#define REG_EMC_NFCSR REG32(EMC_NFCSR)
1687#define REG_EMC_NFECR REG32(EMC_NFECR) 1687#define REG_EMC_NFECR REG32(EMC_NFECR)
1688#define REG_EMC_NFECC REG32(EMC_NFECC) 1688#define REG_EMC_NFECC REG32(EMC_NFECC)
1689#define REG_EMC_NFPAR0 REG32(EMC_NFPAR0) 1689#define REG_EMC_NFPAR0 REG32(EMC_NFPAR0)
1690#define REG_EMC_NFPAR1 REG32(EMC_NFPAR1) 1690#define REG_EMC_NFPAR1 REG32(EMC_NFPAR1)
1691#define REG_EMC_NFPAR2 REG32(EMC_NFPAR2) 1691#define REG_EMC_NFPAR2 REG32(EMC_NFPAR2)
1692#define REG_EMC_NFINTS REG32(EMC_NFINTS) 1692#define REG_EMC_NFINTS REG32(EMC_NFINTS)
1693#define REG_EMC_NFINTE REG32(EMC_NFINTE) 1693#define REG_EMC_NFINTE REG32(EMC_NFINTE)
1694#define REG_EMC_NFERR0 REG32(EMC_NFERR0) 1694#define REG_EMC_NFERR0 REG32(EMC_NFERR0)
1695#define REG_EMC_NFERR1 REG32(EMC_NFERR1) 1695#define REG_EMC_NFERR1 REG32(EMC_NFERR1)
1696#define REG_EMC_NFERR2 REG32(EMC_NFERR2) 1696#define REG_EMC_NFERR2 REG32(EMC_NFERR2)
1697#define REG_EMC_NFERR3 REG32(EMC_NFERR3) 1697#define REG_EMC_NFERR3 REG32(EMC_NFERR3)
1698 1698
1699#define REG_EMC_DMCR REG32(EMC_DMCR) 1699#define REG_EMC_DMCR REG32(EMC_DMCR)
1700#define REG_EMC_RTCSR REG16(EMC_RTCSR) 1700#define REG_EMC_RTCSR REG16(EMC_RTCSR)
1701#define REG_EMC_RTCNT REG16(EMC_RTCNT) 1701#define REG_EMC_RTCNT REG16(EMC_RTCNT)
1702#define REG_EMC_RTCOR REG16(EMC_RTCOR) 1702#define REG_EMC_RTCOR REG16(EMC_RTCOR)
1703#define REG_EMC_DMAR0 REG32(EMC_DMAR0) 1703#define REG_EMC_DMAR0 REG32(EMC_DMAR0)
1704 1704
1705/* Static Memory Control Register */ 1705/* Static Memory Control Register */
1706#define EMC_SMCR_STRV_BIT 24 1706#define EMC_SMCR_STRV_BIT 24
1707#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) 1707#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT)
1708#define EMC_SMCR_TAW_BIT 20 1708#define EMC_SMCR_TAW_BIT 20
1709#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) 1709#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT)
1710#define EMC_SMCR_TBP_BIT 16 1710#define EMC_SMCR_TBP_BIT 16
1711#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) 1711#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT)
1712#define EMC_SMCR_TAH_BIT 12 1712#define EMC_SMCR_TAH_BIT 12
1713#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) 1713#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT)
1714#define EMC_SMCR_TAS_BIT 8 1714#define EMC_SMCR_TAS_BIT 8
1715#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) 1715#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT)
1716#define EMC_SMCR_BW_BIT 6 1716#define EMC_SMCR_BW_BIT 6
1717#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) 1717#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT)
1718 #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) 1718 #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT)
1719 #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) 1719 #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT)
1720 #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) 1720 #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT)
1721#define EMC_SMCR_BCM (1 << 3) 1721#define EMC_SMCR_BCM (1 << 3)
1722#define EMC_SMCR_BL_BIT 1 1722#define EMC_SMCR_BL_BIT 1
1723#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) 1723#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT)
1724 #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) 1724 #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT)
1725 #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) 1725 #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT)
1726 #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) 1726 #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT)
1727 #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) 1727 #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT)
1728#define EMC_SMCR_SMT (1 << 0) 1728#define EMC_SMCR_SMT (1 << 0)
1729 1729
1730/* Static Memory Bank Addr Config Reg */ 1730/* Static Memory Bank Addr Config Reg */
1731#define EMC_SACR_BASE_BIT 8 1731#define EMC_SACR_BASE_BIT 8
1732#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) 1732#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT)
1733#define EMC_SACR_MASK_BIT 0 1733#define EMC_SACR_MASK_BIT 0
1734#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) 1734#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT)
1735 1735
1736/* NAND Flash Control/Status Register */ 1736/* NAND Flash Control/Status Register */
1737#define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */ 1737#define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */
1738#define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */ 1738#define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */
1739#define EMC_NFCSR_NFCE3 (1 << 5) 1739#define EMC_NFCSR_NFCE3 (1 << 5)
1740#define EMC_NFCSR_NFE3 (1 << 4) 1740#define EMC_NFCSR_NFE3 (1 << 4)
1741#define EMC_NFCSR_NFCE2 (1 << 3) 1741#define EMC_NFCSR_NFCE2 (1 << 3)
1742#define EMC_NFCSR_NFE2 (1 << 2) 1742#define EMC_NFCSR_NFE2 (1 << 2)
1743#define EMC_NFCSR_NFCE1 (1 << 1) 1743#define EMC_NFCSR_NFCE1 (1 << 1)
1744#define EMC_NFCSR_NFE1 (1 << 0) 1744#define EMC_NFCSR_NFE1 (1 << 0)
1745 1745
1746/* NAND Flash ECC Control Register */ 1746/* NAND Flash ECC Control Register */
1747#define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */ 1747#define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */
1748#define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */ 1748#define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */
1749#define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */ 1749#define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */
1750#define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */ 1750#define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */
1751#define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */ 1751#define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */
1752#define EMC_NFECR_ERST (1 << 1) /* ECC Reset */ 1752#define EMC_NFECR_ERST (1 << 1) /* ECC Reset */
1753#define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */ 1753#define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */
1754 1754
1755/* NAND Flash ECC Data Register */ 1755/* NAND Flash ECC Data Register */
1756#define EMC_NFECC_ECC2_BIT 16 1756#define EMC_NFECC_ECC2_BIT 16
1757#define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT) 1757#define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT)
1758#define EMC_NFECC_ECC1_BIT 8 1758#define EMC_NFECC_ECC1_BIT 8
1759#define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT) 1759#define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT)
1760#define EMC_NFECC_ECC0_BIT 0 1760#define EMC_NFECC_ECC0_BIT 0
1761#define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT) 1761#define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT)
1762 1762
1763/* NAND Flash Interrupt Status Register */ 1763/* NAND Flash Interrupt Status Register */
1764#define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */ 1764#define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */
1765#define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT) 1765#define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT)
1766#define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */ 1766#define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */
1767#define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */ 1767#define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */
1768#define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */ 1768#define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */
1769#define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */ 1769#define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */
1770#define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */ 1770#define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */
1771 1771
1772/* NAND Flash Interrupt Enable Register */ 1772/* NAND Flash Interrupt Enable Register */
1773#define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */ 1773#define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */
1774#define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */ 1774#define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */
1775#define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */ 1775#define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */
1776#define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */ 1776#define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */
1777#define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */ 1777#define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */
1778 1778
1779/* NAND Flash RS Error Report Register */ 1779/* NAND Flash RS Error Report Register */
1780#define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */ 1780#define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */
1781#define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT) 1781#define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT)
1782#define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */ 1782#define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */
1783#define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT) 1783#define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT)
1784 1784
1785 1785
1786/* DRAM Control Register */ 1786/* DRAM Control Register */
1787#define EMC_DMCR_BW_BIT 31 1787#define EMC_DMCR_BW_BIT 31
1788#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) 1788#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT)
1789#define EMC_DMCR_CA_BIT 26 1789#define EMC_DMCR_CA_BIT 26
1790#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) 1790#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT)
1791 #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) 1791 #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT)
1792 #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) 1792 #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT)
1793 #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) 1793 #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT)
1794 #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) 1794 #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT)
1795 #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) 1795 #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT)
1796#define EMC_DMCR_RMODE (1 << 25) 1796#define EMC_DMCR_RMODE (1 << 25)
1797#define EMC_DMCR_RFSH (1 << 24) 1797#define EMC_DMCR_RFSH (1 << 24)
1798#define EMC_DMCR_MRSET (1 << 23) 1798#define EMC_DMCR_MRSET (1 << 23)
1799#define EMC_DMCR_RA_BIT 20 1799#define EMC_DMCR_RA_BIT 20
1800#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) 1800#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT)
1801 #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) 1801 #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT)
1802 #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) 1802 #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT)
1803 #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) 1803 #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT)
1804#define EMC_DMCR_BA_BIT 19 1804#define EMC_DMCR_BA_BIT 19
1805#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) 1805#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT)
1806#define EMC_DMCR_PDM (1 << 18) 1806#define EMC_DMCR_PDM (1 << 18)
1807#define EMC_DMCR_EPIN (1 << 17) 1807#define EMC_DMCR_EPIN (1 << 17)
1808#define EMC_DMCR_TRAS_BIT 13 1808#define EMC_DMCR_TRAS_BIT 13
1809#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) 1809#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT)
1810#define EMC_DMCR_RCD_BIT 11 1810#define EMC_DMCR_RCD_BIT 11
1811#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) 1811#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT)
1812#define EMC_DMCR_TPC_BIT 8 1812#define EMC_DMCR_TPC_BIT 8
1813#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) 1813#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT)
1814#define EMC_DMCR_TRWL_BIT 5 1814#define EMC_DMCR_TRWL_BIT 5
1815#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) 1815#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT)
1816#define EMC_DMCR_TRC_BIT 2 1816#define EMC_DMCR_TRC_BIT 2
1817#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) 1817#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT)
1818#define EMC_DMCR_TCL_BIT 0 1818#define EMC_DMCR_TCL_BIT 0
1819#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) 1819#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT)
1820 1820
1821/* Refresh Time Control/Status Register */ 1821/* Refresh Time Control/Status Register */
1822#define EMC_RTCSR_CMF (1 << 7) 1822#define EMC_RTCSR_CMF (1 << 7)
1823#define EMC_RTCSR_CKS_BIT 0 1823#define EMC_RTCSR_CKS_BIT 0
1824#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) 1824#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT)
1825 #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) 1825 #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT)
1826 #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) 1826 #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT)
1827 #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) 1827 #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT)
1828 #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) 1828 #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT)
1829 #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) 1829 #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT)
1830 #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) 1830 #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT)
1831 #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) 1831 #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT)
1832 #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) 1832 #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT)
1833 1833
1834/* SDRAM Bank Address Configuration Register */ 1834/* SDRAM Bank Address Configuration Register */
1835#define EMC_DMAR_BASE_BIT 8 1835#define EMC_DMAR_BASE_BIT 8
1836#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) 1836#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
1837#define EMC_DMAR_MASK_BIT 0 1837#define EMC_DMAR_MASK_BIT 0
1838#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) 1838#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
1839 1839
1840/* Mode Register of SDRAM bank 0 */ 1840/* Mode Register of SDRAM bank 0 */
1841#define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */ 1841#define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */
1842#define EMC_SDMR_OM_BIT 7 /* Operating Mode */ 1842#define EMC_SDMR_OM_BIT 7 /* Operating Mode */
1843#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) 1843#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT)
1844 #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) 1844 #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT)
1845#define EMC_SDMR_CAS_BIT 4 /* CAS Latency */ 1845#define EMC_SDMR_CAS_BIT 4 /* CAS Latency */
1846#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) 1846#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT)
1847 #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) 1847 #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT)
1848 #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) 1848 #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT)
1849 #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) 1849 #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT)
1850#define EMC_SDMR_BT_BIT 3 /* Burst Type */ 1850#define EMC_SDMR_BT_BIT 3 /* Burst Type */
1851#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) 1851#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT)
1852 #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */ 1852 #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */
1853 #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */ 1853 #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */
1854#define EMC_SDMR_BL_BIT 0 /* Burst Length */ 1854#define EMC_SDMR_BL_BIT 0 /* Burst Length */
1855#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) 1855#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT)
1856 #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) 1856 #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT)
1857 #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) 1857 #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT)
1858 #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) 1858 #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT)
1859 #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) 1859 #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT)
1860 1860
1861#define EMC_SDMR_CAS2_16BIT \ 1861#define EMC_SDMR_CAS2_16BIT \
1862 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) 1862 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
1863#define EMC_SDMR_CAS2_32BIT \ 1863#define EMC_SDMR_CAS2_32BIT \
1864 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) 1864 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1865#define EMC_SDMR_CAS3_16BIT \ 1865#define EMC_SDMR_CAS3_16BIT \
1866 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) 1866 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
1867#define EMC_SDMR_CAS3_32BIT \ 1867#define EMC_SDMR_CAS3_32BIT \
1868 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) 1868 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1869 1869
1870 1870
1871/************************************************************************* 1871/*************************************************************************
1872 * CIM 1872 * CIM
1873 *************************************************************************/ 1873 *************************************************************************/
1874#define CIM_CFG (CIM_BASE + 0x0000) 1874#define CIM_CFG (CIM_BASE + 0x0000)
1875#define CIM_CTRL (CIM_BASE + 0x0004) 1875#define CIM_CTRL (CIM_BASE + 0x0004)
1876#define CIM_STATE (CIM_BASE + 0x0008) 1876#define CIM_STATE (CIM_BASE + 0x0008)
1877#define CIM_IID (CIM_BASE + 0x000C) 1877#define CIM_IID (CIM_BASE + 0x000C)
1878#define CIM_RXFIFO (CIM_BASE + 0x0010) 1878#define CIM_RXFIFO (CIM_BASE + 0x0010)
1879#define CIM_DA (CIM_BASE + 0x0020) 1879#define CIM_DA (CIM_BASE + 0x0020)
1880#define CIM_FA (CIM_BASE + 0x0024) 1880#define CIM_FA (CIM_BASE + 0x0024)
1881#define CIM_FID (CIM_BASE + 0x0028) 1881#define CIM_FID (CIM_BASE + 0x0028)
1882#define CIM_CMD (CIM_BASE + 0x002C) 1882#define CIM_CMD (CIM_BASE + 0x002C)
1883 1883
1884#define REG_CIM_CFG REG32(CIM_CFG) 1884#define REG_CIM_CFG REG32(CIM_CFG)
1885#define REG_CIM_CTRL REG32(CIM_CTRL) 1885#define REG_CIM_CTRL REG32(CIM_CTRL)
1886#define REG_CIM_STATE REG32(CIM_STATE) 1886#define REG_CIM_STATE REG32(CIM_STATE)
1887#define REG_CIM_IID REG32(CIM_IID) 1887#define REG_CIM_IID REG32(CIM_IID)
1888#define REG_CIM_RXFIFO REG32(CIM_RXFIFO) 1888#define REG_CIM_RXFIFO REG32(CIM_RXFIFO)
1889#define REG_CIM_DA REG32(CIM_DA) 1889#define REG_CIM_DA REG32(CIM_DA)
1890#define REG_CIM_FA REG32(CIM_FA) 1890#define REG_CIM_FA REG32(CIM_FA)
1891#define REG_CIM_FID REG32(CIM_FID) 1891#define REG_CIM_FID REG32(CIM_FID)
1892#define REG_CIM_CMD REG32(CIM_CMD) 1892#define REG_CIM_CMD REG32(CIM_CMD)
1893 1893
1894/* CIM Configuration Register (CIM_CFG) */ 1894/* CIM Configuration Register (CIM_CFG) */
1895 1895
1896#define CIM_CFG_INV_DAT (1 << 15) 1896#define CIM_CFG_INV_DAT (1 << 15)
1897#define CIM_CFG_VSP (1 << 14) 1897#define CIM_CFG_VSP (1 << 14)
1898#define CIM_CFG_HSP (1 << 13) 1898#define CIM_CFG_HSP (1 << 13)
1899#define CIM_CFG_PCP (1 << 12) 1899#define CIM_CFG_PCP (1 << 12)
1900#define CIM_CFG_DUMMY_ZERO (1 << 9) 1900#define CIM_CFG_DUMMY_ZERO (1 << 9)
1901#define CIM_CFG_EXT_VSYNC (1 << 8) 1901#define CIM_CFG_EXT_VSYNC (1 << 8)
1902#define CIM_CFG_PACK_BIT 4 1902#define CIM_CFG_PACK_BIT 4
1903#define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT) 1903#define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT)
1904 #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT) 1904 #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT)
1905 #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT) 1905 #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT)
1906 #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT) 1906 #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT)
1907 #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT) 1907 #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT)
1908 #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT) 1908 #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT)
1909 #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT) 1909 #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT)
1910 #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT) 1910 #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT)
1911 #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT) 1911 #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT)
1912#define CIM_CFG_DSM_BIT 0 1912#define CIM_CFG_DSM_BIT 0
1913#define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT) 1913#define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT)
1914 #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */ 1914 #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */
1915 #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */ 1915 #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */
1916 #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */ 1916 #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */
1917 #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */ 1917 #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */
1918 1918
1919/* CIM Control Register (CIM_CTRL) */ 1919/* CIM Control Register (CIM_CTRL) */
1920 1920
1921#define CIM_CTRL_MCLKDIV_BIT 24 1921#define CIM_CTRL_MCLKDIV_BIT 24
1922#define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT) 1922#define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT)
1923#define CIM_CTRL_FRC_BIT 16 1923#define CIM_CTRL_FRC_BIT 16
1924#define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT) 1924#define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT)
1925 #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */ 1925 #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */
1926 #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */ 1926 #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */
1927 #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */ 1927 #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */
1928 #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */ 1928 #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */
1929 #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */ 1929 #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */
1930 #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */ 1930 #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */
1931 #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */ 1931 #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */
1932 #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */ 1932 #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */
1933 #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */ 1933 #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */
1934 #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */ 1934 #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */
1935 #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */ 1935 #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */
1936 #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */ 1936 #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */
1937 #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */ 1937 #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */
1938 #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */ 1938 #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */
1939 #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */ 1939 #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */
1940 #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */ 1940 #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */
1941#define CIM_CTRL_VDDM (1 << 13) 1941#define CIM_CTRL_VDDM (1 << 13)
1942#define CIM_CTRL_DMA_SOFM (1 << 12) 1942#define CIM_CTRL_DMA_SOFM (1 << 12)
1943#define CIM_CTRL_DMA_EOFM (1 << 11) 1943#define CIM_CTRL_DMA_EOFM (1 << 11)
1944#define CIM_CTRL_DMA_STOPM (1 << 10) 1944#define CIM_CTRL_DMA_STOPM (1 << 10)
1945#define CIM_CTRL_RXF_TRIGM (1 << 9) 1945#define CIM_CTRL_RXF_TRIGM (1 << 9)
1946#define CIM_CTRL_RXF_OFM (1 << 8) 1946#define CIM_CTRL_RXF_OFM (1 << 8)
1947#define CIM_CTRL_RXF_TRIG_BIT 4 1947#define CIM_CTRL_RXF_TRIG_BIT 4
1948#define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT) 1948#define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT)
1949 #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */ 1949 #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */
1950 #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */ 1950 #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */
1951 #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */ 1951 #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */
1952 #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */ 1952 #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */
1953 #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */ 1953 #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */
1954 #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */ 1954 #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */
1955 #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */ 1955 #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */
1956 #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */ 1956 #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */
1957#define CIM_CTRL_DMA_EN (1 << 2) 1957#define CIM_CTRL_DMA_EN (1 << 2)
1958#define CIM_CTRL_RXF_RST (1 << 1) 1958#define CIM_CTRL_RXF_RST (1 << 1)
1959#define CIM_CTRL_ENA (1 << 0) 1959#define CIM_CTRL_ENA (1 << 0)
1960 1960
1961/* CIM State Register (CIM_STATE) */ 1961/* CIM State Register (CIM_STATE) */
1962 1962
1963#define CIM_STATE_DMA_SOF (1 << 6) 1963#define CIM_STATE_DMA_SOF (1 << 6)
1964#define CIM_STATE_DMA_EOF (1 << 5) 1964#define CIM_STATE_DMA_EOF (1 << 5)
1965#define CIM_STATE_DMA_STOP (1 << 4) 1965#define CIM_STATE_DMA_STOP (1 << 4)
1966#define CIM_STATE_RXF_OF (1 << 3) 1966#define CIM_STATE_RXF_OF (1 << 3)
1967#define CIM_STATE_RXF_TRIG (1 << 2) 1967#define CIM_STATE_RXF_TRIG (1 << 2)
1968#define CIM_STATE_RXF_EMPTY (1 << 1) 1968#define CIM_STATE_RXF_EMPTY (1 << 1)
1969#define CIM_STATE_VDD (1 << 0) 1969#define CIM_STATE_VDD (1 << 0)
1970 1970
1971/* CIM DMA Command Register (CIM_CMD) */ 1971/* CIM DMA Command Register (CIM_CMD) */
1972 1972
1973#define CIM_CMD_SOFINT (1 << 31) 1973#define CIM_CMD_SOFINT (1 << 31)
1974#define CIM_CMD_EOFINT (1 << 30) 1974#define CIM_CMD_EOFINT (1 << 30)
1975#define CIM_CMD_STOP (1 << 28) 1975#define CIM_CMD_STOP (1 << 28)
1976#define CIM_CMD_LEN_BIT 0 1976#define CIM_CMD_LEN_BIT 0
1977#define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT) 1977#define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT)
1978 1978
1979 1979
1980/************************************************************************* 1980/*************************************************************************
1981 * SADC (Smart A/D Controller) 1981 * SADC (Smart A/D Controller)
1982 *************************************************************************/ 1982 *************************************************************************/
1983 1983
1984#define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */ 1984#define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */
1985#define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */ 1985#define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */
1986#define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */ 1986#define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */
1987#define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/ 1987#define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/
1988#define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */ 1988#define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */
1989#define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */ 1989#define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */
1990#define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */ 1990#define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */
1991#define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */ 1991#define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */
1992#define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */ 1992#define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */
1993 1993
1994#define REG_SADC_ENA REG8(SADC_ENA) 1994#define REG_SADC_ENA REG8(SADC_ENA)
1995#define REG_SADC_CFG REG32(SADC_CFG) 1995#define REG_SADC_CFG REG32(SADC_CFG)
1996#define REG_SADC_CTRL REG8(SADC_CTRL) 1996#define REG_SADC_CTRL REG8(SADC_CTRL)
1997#define REG_SADC_STATE REG8(SADC_STATE) 1997#define REG_SADC_STATE REG8(SADC_STATE)
1998#define REG_SADC_SAMETIME REG16(SADC_SAMETIME) 1998#define REG_SADC_SAMETIME REG16(SADC_SAMETIME)
1999#define REG_SADC_WAITTIME REG16(SADC_WAITTIME) 1999#define REG_SADC_WAITTIME REG16(SADC_WAITTIME)
2000#define REG_SADC_TSDAT REG32(SADC_TSDAT) 2000#define REG_SADC_TSDAT REG32(SADC_TSDAT)
2001#define REG_SADC_BATDAT REG16(SADC_BATDAT) 2001#define REG_SADC_BATDAT REG16(SADC_BATDAT)
2002#define REG_SADC_SADDAT REG16(SADC_SADDAT) 2002#define REG_SADC_SADDAT REG16(SADC_SADDAT)
2003 2003
2004/* ADC Enable Register */ 2004/* ADC Enable Register */
2005#define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */ 2005#define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */
2006#define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */ 2006#define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */
2007#define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */ 2007#define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */
2008#define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */ 2008#define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */
2009 2009
2010/* ADC Configure Register */ 2010/* ADC Configure Register */
2011#define SADC_CFG_CLKOUT_NUM_BIT 16 2011#define SADC_CFG_CLKOUT_NUM_BIT 16
2012#define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT) 2012#define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT)
2013#define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */ 2013#define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */
2014#define SADC_CFG_XYZ_BIT 13 /* XYZ selection */ 2014#define SADC_CFG_XYZ_BIT 13 /* XYZ selection */
2015#define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT) 2015#define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT)
2016 #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT) 2016 #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT)
2017 #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT) 2017 #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT)
2018 #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT) 2018 #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT)
2019#define SADC_CFG_SNUM_BIT 10 /* Sample Number */ 2019#define SADC_CFG_SNUM_BIT 10 /* Sample Number */
2020#define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT) 2020#define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT)
2021 #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT) 2021 #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT)
2022 #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT) 2022 #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT)
2023 #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT) 2023 #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT)
2024 #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT) 2024 #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT)
2025 #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT) 2025 #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT)
2026 #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT) 2026 #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT)
2027 #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT) 2027 #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT)
2028 #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT) 2028 #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT)
2029#define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */ 2029#define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */
2030#define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT) 2030#define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT)
2031#define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */ 2031#define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */
2032#define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */ 2032#define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */
2033#define SADC_CFG_CMD_BIT 0 /* ADC Command */ 2033#define SADC_CFG_CMD_BIT 0 /* ADC Command */
2034#define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT) 2034#define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT)
2035 #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */ 2035 #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */
2036 #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */ 2036 #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */
2037 #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */ 2037 #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */
2038 #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */ 2038 #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */
2039 #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */ 2039 #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */
2040 #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */ 2040 #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */
2041 #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */ 2041 #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */
2042 #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */ 2042 #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */
2043 #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */ 2043 #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */
2044 #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */ 2044 #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */
2045 #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */ 2045 #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */
2046 #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */ 2046 #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */
2047 #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */ 2047 #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */
2048 2048
2049/* ADC Control Register */ 2049/* ADC Control Register */
2050#define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */ 2050#define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */
2051#define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */ 2051#define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */
2052#define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */ 2052#define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */
2053#define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */ 2053#define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */
2054#define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */ 2054#define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */
2055 2055
2056/* ADC Status Register */ 2056/* ADC Status Register */
2057#define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */ 2057#define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */
2058#define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */ 2058#define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */
2059#define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */ 2059#define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */
2060#define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */ 2060#define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */
2061#define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */ 2061#define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */
2062#define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */ 2062#define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */
2063#define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */ 2063#define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */
2064#define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */ 2064#define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */
2065 2065
2066/* ADC Touch Screen Data Register */ 2066/* ADC Touch Screen Data Register */
2067#define SADC_TSDAT_DATA0_BIT 0 2067#define SADC_TSDAT_DATA0_BIT 0
2068#define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT) 2068#define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT)
2069#define SADC_TSDAT_TYPE0 (1 << 15) 2069#define SADC_TSDAT_TYPE0 (1 << 15)
2070#define SADC_TSDAT_DATA1_BIT 16 2070#define SADC_TSDAT_DATA1_BIT 16
2071#define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT) 2071#define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT)
2072#define SADC_TSDAT_TYPE1 (1 << 31) 2072#define SADC_TSDAT_TYPE1 (1 << 31)
2073 2073
2074 2074
2075/************************************************************************* 2075/*************************************************************************
2076 * SLCD (Smart LCD Controller) 2076 * SLCD (Smart LCD Controller)
2077 *************************************************************************/ 2077 *************************************************************************/
2078 2078
2079#define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */ 2079#define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */
2080#define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */ 2080#define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */
2081#define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */ 2081#define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */
2082#define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */ 2082#define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */
2083#define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */ 2083#define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */
2084 2084
2085#define REG_SLCD_CFG REG32(SLCD_CFG) 2085#define REG_SLCD_CFG REG32(SLCD_CFG)
2086#define REG_SLCD_CTRL REG8(SLCD_CTRL) 2086#define REG_SLCD_CTRL REG8(SLCD_CTRL)
2087#define REG_SLCD_STATE REG8(SLCD_STATE) 2087#define REG_SLCD_STATE REG8(SLCD_STATE)
2088#define REG_SLCD_DATA REG32(SLCD_DATA) 2088#define REG_SLCD_DATA REG32(SLCD_DATA)
2089#define REG_SLCD_FIFO REG32(SLCD_FIFO) 2089#define REG_SLCD_FIFO REG32(SLCD_FIFO)
2090 2090
2091/* SLCD Configure Register */ 2091/* SLCD Configure Register */
2092#define SLCD_CFG_BURST_BIT 14 2092#define SLCD_CFG_BURST_BIT 14
2093#define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT) 2093#define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT)
2094 #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT) 2094 #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT)
2095 #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT) 2095 #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT)
2096#define SLCD_CFG_DWIDTH_BIT 10 2096#define SLCD_CFG_DWIDTH_BIT 10
2097#define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT) 2097#define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT)
2098 #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT) 2098 #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT)
2099 #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT) 2099 #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT)
2100 #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT) 2100 #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT)
2101 #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT) 2101 #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT)
2102 #define SLCD_CFG_DWIDTH_8_x1 (4 << SLCD_CFG_DWIDTH_BIT) 2102 #define SLCD_CFG_DWIDTH_8_x1 (4 << SLCD_CFG_DWIDTH_BIT)
2103 #define SLCD_CFG_DWIDTH_9_x2 (7 << SLCD_CFG_DWIDTH_BIT) 2103 #define SLCD_CFG_DWIDTH_9_x2 (7 << SLCD_CFG_DWIDTH_BIT)
2104#define SLCD_CFG_CWIDTH_BIT 8 2104#define SLCD_CFG_CWIDTH_BIT 8
2105#define SLCD_CFG_CWIDTH_MASK (0x3 << SLCD_CFG_CWIDTH_BIT) 2105#define SLCD_CFG_CWIDTH_MASK (0x3 << SLCD_CFG_CWIDTH_BIT)
2106 #define SLCD_CFG_CWIDTH_16BIT (0 << SLCD_CFG_CWIDTH_BIT) 2106 #define SLCD_CFG_CWIDTH_16BIT (0 << SLCD_CFG_CWIDTH_BIT)
2107 #define SLCD_CFG_CWIDTH_8BIT (1 << SLCD_CFG_CWIDTH_BIT) 2107 #define SLCD_CFG_CWIDTH_8BIT (1 << SLCD_CFG_CWIDTH_BIT)
2108 #define SLCD_CFG_CWIDTH_18BIT (2 << SLCD_CFG_CWIDTH_BIT) 2108 #define SLCD_CFG_CWIDTH_18BIT (2 << SLCD_CFG_CWIDTH_BIT)
2109#define SLCD_CFG_CS_ACTIVE_LOW (0 << 4) 2109#define SLCD_CFG_CS_ACTIVE_LOW (0 << 4)
2110#define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4) 2110#define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4)
2111#define SLCD_CFG_RS_CMD_LOW (0 << 3) 2111#define SLCD_CFG_RS_CMD_LOW (0 << 3)
2112#define SLCD_CFG_RS_CMD_HIGH (1 << 3) 2112#define SLCD_CFG_RS_CMD_HIGH (1 << 3)
2113#define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1) 2113#define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1)
2114#define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1) 2114#define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1)
2115#define SLCD_CFG_TYPE_PARALLEL (0 << 0) 2115#define SLCD_CFG_TYPE_PARALLEL (0 << 0)
2116#define SLCD_CFG_TYPE_SERIAL (1 << 0) 2116#define SLCD_CFG_TYPE_SERIAL (1 << 0)
2117 2117
2118/* SLCD Control Register */ 2118/* SLCD Control Register */
2119#define SLCD_CTRL_DMA_EN (1 << 0) 2119#define SLCD_CTRL_DMA_EN (1 << 0)
2120 2120
2121/* SLCD Status Register */ 2121/* SLCD Status Register */
2122#define SLCD_STATE_BUSY (1 << 0) 2122#define SLCD_STATE_BUSY (1 << 0)
2123 2123
2124/* SLCD Data Register */ 2124/* SLCD Data Register */
2125#define SLCD_DATA_RS_DATA (0 << 31) 2125#define SLCD_DATA_RS_DATA (0 << 31)
2126#define SLCD_DATA_RS_COMMAND (1 << 31) 2126#define SLCD_DATA_RS_COMMAND (1 << 31)
2127 2127
2128/* SLCD FIFO Register */ 2128/* SLCD FIFO Register */
2129#define SLCD_FIFO_RS_DATA (0 << 31) 2129#define SLCD_FIFO_RS_DATA (0 << 31)
2130#define SLCD_FIFO_RS_COMMAND (1 << 31) 2130#define SLCD_FIFO_RS_COMMAND (1 << 31)
2131 2131
2132 2132
2133/************************************************************************* 2133/*************************************************************************
2134 * LCD (LCD Controller) 2134 * LCD (LCD Controller)
2135 *************************************************************************/ 2135 *************************************************************************/
2136#define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */ 2136#define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */
2137#define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */ 2137#define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */
2138#define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */ 2138#define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */
2139#define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */ 2139#define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */
2140#define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */ 2140#define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */
2141#define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */ 2141#define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */
2142#define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */ 2142#define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */
2143#define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */ 2143#define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */
2144#define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */ 2144#define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */
2145#define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */ 2145#define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */
2146#define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */ 2146#define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */
2147#define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */ 2147#define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */
2148#define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */ 2148#define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */
2149#define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */ 2149#define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */
2150#define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */ 2150#define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */
2151#define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */ 2151#define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */
2152#define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */ 2152#define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */
2153#define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */ 2153#define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */
2154#define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */ 2154#define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */
2155#define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */ 2155#define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */
2156#define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */ 2156#define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */
2157 2157
2158#define REG_LCD_CFG REG32(LCD_CFG) 2158#define REG_LCD_CFG REG32(LCD_CFG)
2159#define REG_LCD_VSYNC REG32(LCD_VSYNC) 2159#define REG_LCD_VSYNC REG32(LCD_VSYNC)
2160#define REG_LCD_HSYNC REG32(LCD_HSYNC) 2160#define REG_LCD_HSYNC REG32(LCD_HSYNC)
2161#define REG_LCD_VAT REG32(LCD_VAT) 2161#define REG_LCD_VAT REG32(LCD_VAT)
2162#define REG_LCD_DAH REG32(LCD_DAH) 2162#define REG_LCD_DAH REG32(LCD_DAH)
2163#define REG_LCD_DAV REG32(LCD_DAV) 2163#define REG_LCD_DAV REG32(LCD_DAV)
2164#define REG_LCD_PS REG32(LCD_PS) 2164#define REG_LCD_PS REG32(LCD_PS)
2165#define REG_LCD_CLS REG32(LCD_CLS) 2165#define REG_LCD_CLS REG32(LCD_CLS)
2166#define REG_LCD_SPL REG32(LCD_SPL) 2166#define REG_LCD_SPL REG32(LCD_SPL)
2167#define REG_LCD_REV REG32(LCD_REV) 2167#define REG_LCD_REV REG32(LCD_REV)
2168#define REG_LCD_CTRL REG32(LCD_CTRL) 2168#define REG_LCD_CTRL REG32(LCD_CTRL)
2169#define REG_LCD_STATE REG32(LCD_STATE) 2169#define REG_LCD_STATE REG32(LCD_STATE)
2170#define REG_LCD_IID REG32(LCD_IID) 2170#define REG_LCD_IID REG32(LCD_IID)
2171#define REG_LCD_DA0 REG32(LCD_DA0) 2171#define REG_LCD_DA0 REG32(LCD_DA0)
2172#define REG_LCD_SA0 REG32(LCD_SA0) 2172#define REG_LCD_SA0 REG32(LCD_SA0)
2173#define REG_LCD_FID0 REG32(LCD_FID0) 2173#define REG_LCD_FID0 REG32(LCD_FID0)
2174#define REG_LCD_CMD0 REG32(LCD_CMD0) 2174#define REG_LCD_CMD0 REG32(LCD_CMD0)
2175#define REG_LCD_DA1 REG32(LCD_DA1) 2175#define REG_LCD_DA1 REG32(LCD_DA1)
2176#define REG_LCD_SA1 REG32(LCD_SA1) 2176#define REG_LCD_SA1 REG32(LCD_SA1)
2177#define REG_LCD_FID1 REG32(LCD_FID1) 2177#define REG_LCD_FID1 REG32(LCD_FID1)
2178#define REG_LCD_CMD1 REG32(LCD_CMD1) 2178#define REG_LCD_CMD1 REG32(LCD_CMD1)
2179 2179
2180/* LCD Configure Register */ 2180/* LCD Configure Register */
2181#define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */ 2181#define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */
2182#define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT) 2182#define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT)
2183 #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT) 2183 #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT)
2184 #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT) 2184 #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT)
2185#define LCD_CFG_PSM (1 << 23) /* PS signal mode */ 2185#define LCD_CFG_PSM (1 << 23) /* PS signal mode */
2186#define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */ 2186#define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */
2187#define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */ 2187#define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */
2188#define LCD_CFG_REVM (1 << 20) /* REV signal mode */ 2188#define LCD_CFG_REVM (1 << 20) /* REV signal mode */
2189#define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */ 2189#define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */
2190#define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */ 2190#define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */
2191#define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */ 2191#define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */
2192#define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */ 2192#define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */
2193#define LCD_CFG_PSP (1 << 15) /* PS pin reset state */ 2193#define LCD_CFG_PSP (1 << 15) /* PS pin reset state */
2194#define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */ 2194#define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */
2195#define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */ 2195#define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */
2196#define LCD_CFG_REVP (1 << 12) /* REV pin reset state */ 2196#define LCD_CFG_REVP (1 << 12) /* REV pin reset state */
2197#define LCD_CFG_HSP (1 << 11) /* HSYNC pority:0-active high,1-active low */ 2197#define LCD_CFG_HSP (1 << 11) /* HSYNC pority:0-active high,1-active low */
2198#define LCD_CFG_PCP (1 << 10) /* PCLK pority:0-rising,1-falling */ 2198#define LCD_CFG_PCP (1 << 10) /* PCLK pority:0-rising,1-falling */
2199#define LCD_CFG_DEP (1 << 9) /* DE pority:0-active high,1-active low */ 2199#define LCD_CFG_DEP (1 << 9) /* DE pority:0-active high,1-active low */
2200#define LCD_CFG_VSP (1 << 8) /* VSYNC pority:0-rising,1-falling */ 2200#define LCD_CFG_VSP (1 << 8) /* VSYNC pority:0-rising,1-falling */
2201#define LCD_CFG_PDW_BIT 4 /* STN pins utilization */ 2201#define LCD_CFG_PDW_BIT 4 /* STN pins utilization */
2202#define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT) 2202#define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT)
2203#define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */ 2203#define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */
2204 #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */ 2204 #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */
2205 #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */ 2205 #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */
2206 #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */ 2206 #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */
2207#define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */ 2207#define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */
2208#define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT) 2208#define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT)
2209 #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */ 2209 #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */
2210 #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT) 2210 #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT)
2211 #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT) 2211 #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT)
2212 #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT) 2212 #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT)
2213 #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT) 2213 #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT)
2214 #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_CFG_MODE_BIT) 2214 #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_CFG_MODE_BIT)
2215 #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT) 2215 #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT)
2216 #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT) 2216 #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT)
2217 #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT) 2217 #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT)
2218 #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT) 2218 #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT)
2219 #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT) 2219 #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT)
2220 #define LCD_CFG_MODE_GENERIC_18BIT_TFT (13 << LCD_CFG_MODE_BIT) 2220 #define LCD_CFG_MODE_GENERIC_18BIT_TFT (13 << LCD_CFG_MODE_BIT)
2221 /* JZ47XX defines */ 2221 /* JZ47XX defines */
2222 #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT) 2222 #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT)
2223 #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT) 2223 #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT)
2224 #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT) 2224 #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT)
2225 2225
2226 2226
2227 2227
2228/* Vertical Synchronize Register */ 2228/* Vertical Synchronize Register */
2229#define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */ 2229#define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */
2230#define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT) 2230#define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT)
2231#define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */ 2231#define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */
2232#define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT) 2232#define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT)
2233 2233
2234/* Horizontal Synchronize Register */ 2234/* Horizontal Synchronize Register */
2235#define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */ 2235#define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */
2236#define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT) 2236#define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT)
2237#define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */ 2237#define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */
2238#define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT) 2238#define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT)
2239 2239
2240/* Virtual Area Setting Register */ 2240/* Virtual Area Setting Register */
2241#define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */ 2241#define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */
2242#define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT) 2242#define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT)
2243#define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */ 2243#define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */
2244#define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT) 2244#define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT)
2245 2245
2246/* Display Area Horizontal Start/End Point Register */ 2246/* Display Area Horizontal Start/End Point Register */
2247#define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */ 2247#define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */
2248#define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT) 2248#define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT)
2249#define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */ 2249#define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */
2250#define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT) 2250#define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT)
2251 2251
2252/* Display Area Vertical Start/End Point Register */ 2252/* Display Area Vertical Start/End Point Register */
2253#define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */ 2253#define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */
2254#define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT) 2254#define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT)
2255#define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */ 2255#define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */
2256#define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT) 2256#define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT)
2257 2257
2258/* PS Signal Setting */ 2258/* PS Signal Setting */
2259#define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */ 2259#define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */
2260#define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT) 2260#define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT)
2261#define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */ 2261#define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */
2262#define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT) 2262#define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT)
2263 2263
2264/* CLS Signal Setting */ 2264/* CLS Signal Setting */
2265#define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */ 2265#define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */
2266#define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT) 2266#define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT)
2267#define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */ 2267#define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */
2268#define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT) 2268#define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT)
2269 2269
2270/* SPL Signal Setting */ 2270/* SPL Signal Setting */
2271#define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */ 2271#define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */
2272#define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT) 2272#define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT)
2273#define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */ 2273#define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */
2274#define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT) 2274#define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT)
2275 2275
2276/* REV Signal Setting */ 2276/* REV Signal Setting */
2277#define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */ 2277#define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */
2278#define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT) 2278#define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT)
2279 2279
2280/* LCD Control Register */ 2280/* LCD Control Register */
2281#define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */ 2281#define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */
2282#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT) 2282#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT)
2283 #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */ 2283 #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */
2284 #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */ 2284 #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */
2285 #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */ 2285 #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */
2286#define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */ 2286#define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */
2287#define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */ 2287#define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */
2288#define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */ 2288#define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */
2289#define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */ 2289#define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */
2290#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT) 2290#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT)
2291 #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */ 2291 #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */
2292 #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */ 2292 #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */
2293 #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */ 2293 #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */
2294#define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */ 2294#define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */
2295#define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT) 2295#define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT)
2296#define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */ 2296#define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */
2297#define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */ 2297#define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */
2298#define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */ 2298#define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */
2299#define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */ 2299#define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */
2300#define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */ 2300#define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */
2301#define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */ 2301#define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */
2302#define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */ 2302#define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */
2303#define LCD_CTRL_BEDN (1 << 6) /* Endian selection */ 2303#define LCD_CTRL_BEDN (1 << 6) /* Endian selection */
2304#define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */ 2304#define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */
2305#define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */ 2305#define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */
2306#define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */ 2306#define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */
2307#define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */ 2307#define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */
2308#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT) 2308#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT)
2309 #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */ 2309 #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */
2310 #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */ 2310 #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */
2311 #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */ 2311 #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */
2312 #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */ 2312 #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */
2313 #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */ 2313 #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */
2314 #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */ 2314 #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */
2315 2315
2316/* LCD Status Register */ 2316/* LCD Status Register */
2317#define LCD_STATE_QD (1 << 7) /* Quick Disable Done */ 2317#define LCD_STATE_QD (1 << 7) /* Quick Disable Done */
2318#define LCD_STATE_EOF (1 << 5) /* EOF Flag */ 2318#define LCD_STATE_EOF (1 << 5) /* EOF Flag */
2319#define LCD_STATE_SOF (1 << 4) /* SOF Flag */ 2319#define LCD_STATE_SOF (1 << 4) /* SOF Flag */
2320#define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */ 2320#define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */
2321#define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */ 2321#define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */
2322#define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */ 2322#define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */
2323#define LCD_STATE_LDD (1 << 0) /* LCD Disabled */ 2323#define LCD_STATE_LDD (1 << 0) /* LCD Disabled */
2324 2324
2325/* DMA Command Register */ 2325/* DMA Command Register */
2326#define LCD_CMD_SOFINT (1 << 31) 2326#define LCD_CMD_SOFINT (1 << 31)
2327#define LCD_CMD_EOFINT (1 << 30) 2327#define LCD_CMD_EOFINT (1 << 30)
2328#define LCD_CMD_PAL (1 << 28) 2328#define LCD_CMD_PAL (1 << 28)
2329#define LCD_CMD_LEN_BIT 0 2329#define LCD_CMD_LEN_BIT 0
2330#define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT) 2330#define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT)
2331 2331
2332 2332
2333/************************************************************************* 2333/*************************************************************************
2334 * USB Device 2334 * USB Device
2335 *************************************************************************/ 2335 *************************************************************************/
2336#define USB_BASE UDC_BASE 2336#define USB_BASE UDC_BASE
2337 2337
2338#define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */ 2338#define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */
2339#define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */ 2339#define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */
2340#define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */ 2340#define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */
2341#define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */ 2341#define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */
2342#define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */ 2342#define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */
2343#define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */ 2343#define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */
2344#define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */ 2344#define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */
2345#define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */ 2345#define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */
2346#define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */ 2346#define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */
2347#define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */ 2347#define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */
2348#define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */ 2348#define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */
2349 2349
2350#define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */ 2350#define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */
2351#define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */ 2351#define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */
2352#define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */ 2352#define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */
2353#define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */ 2353#define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */
2354#define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */ 2354#define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */
2355#define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */ 2355#define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */
2356#define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */ 2356#define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */
2357#define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */ 2357#define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */
2358 2358
2359#define USB_FIFO_EP0 (USB_BASE + 0x20) 2359#define USB_FIFO_EP0 (USB_BASE + 0x20)
2360#define USB_FIFO_EP1 (USB_BASE + 0x24) 2360#define USB_FIFO_EP1 (USB_BASE + 0x24)
2361#define USB_FIFO_EP2 (USB_BASE + 0x28) 2361#define USB_FIFO_EP2 (USB_BASE + 0x28)
2362 2362
2363#define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */ 2363#define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */
2364#define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */ 2364#define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */
2365 2365
2366#define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts */ 2366#define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts */
2367#define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control */ 2367#define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control */
2368#define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */ 2368#define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */
2369#define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count */ 2369#define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count */
2370#define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control */ 2370#define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control */
2371#define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */ 2371#define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */
2372#define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count */ 2372#define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count */
2373 2373
2374 2374
2375/* Power register bit masks */ 2375/* Power register bit masks */
2376#define USB_POWER_SUSPENDM 0x01 2376#define USB_POWER_SUSPENDM 0x01
2377#define USB_POWER_RESUME 0x04 2377#define USB_POWER_RESUME 0x04
2378#define USB_POWER_HSMODE 0x10 2378#define USB_POWER_HSMODE 0x10
2379#define USB_POWER_HSENAB 0x20 2379#define USB_POWER_HSENAB 0x20
2380#define USB_POWER_SOFTCONN 0x40 2380#define USB_POWER_SOFTCONN 0x40
2381 2381
2382/* Interrupt register bit masks */ 2382/* Interrupt register bit masks */
2383#define USB_INTR_SUSPEND 0x01 2383#define USB_INTR_SUSPEND 0x01
2384#define USB_INTR_RESUME 0x02 2384#define USB_INTR_RESUME 0x02
2385#define USB_INTR_RESET 0x04 2385#define USB_INTR_RESET 0x04
2386 2386
2387#define USB_INTR_EP0 0x0001 2387#define USB_INTR_EP0 0x0001
2388#define USB_INTR_INEP1 0x0002 2388#define USB_INTR_INEP1 0x0002
2389#define USB_INTR_INEP2 0x0004 2389#define USB_INTR_INEP2 0x0004
2390#define USB_INTR_OUTEP1 0x0002 2390#define USB_INTR_OUTEP1 0x0002
2391 2391
2392/* CSR0 bit masks */ 2392/* CSR0 bit masks */
2393#define USB_CSR0_OUTPKTRDY 0x01 2393#define USB_CSR0_OUTPKTRDY 0x01
2394#define USB_CSR0_INPKTRDY 0x02 2394#define USB_CSR0_INPKTRDY 0x02
2395#define USB_CSR0_SENTSTALL 0x04 2395#define USB_CSR0_SENTSTALL 0x04
2396#define USB_CSR0_DATAEND 0x08 2396#define USB_CSR0_DATAEND 0x08
2397#define USB_CSR0_SETUPEND 0x10 2397#define USB_CSR0_SETUPEND 0x10
2398#define USB_CSR0_SENDSTALL 0x20 2398#define USB_CSR0_SENDSTALL 0x20
2399#define USB_CSR0_SVDOUTPKTRDY 0x40 2399#define USB_CSR0_SVDOUTPKTRDY 0x40
2400#define USB_CSR0_SVDSETUPEND 0x80 2400#define USB_CSR0_SVDSETUPEND 0x80
2401 2401
2402/* Endpoint CSR register bits */ 2402/* Endpoint CSR register bits */
2403#define USB_INCSRH_AUTOSET 0x80 2403#define USB_INCSRH_AUTOSET 0x80
2404#define USB_INCSRH_ISO 0x40 2404#define USB_INCSRH_ISO 0x40
2405#define USB_INCSRH_MODE 0x20 2405#define USB_INCSRH_MODE 0x20
2406#define USB_INCSRH_DMAREQENAB 0x10 2406#define USB_INCSRH_DMAREQENAB 0x10
2407#define USB_INCSRH_DMAREQMODE 0x04 2407#define USB_INCSRH_DMAREQMODE 0x04
2408#define USB_INCSR_CDT 0x40 2408#define USB_INCSR_CDT 0x40
2409#define USB_INCSR_SENTSTALL 0x20 2409#define USB_INCSR_SENTSTALL 0x20
2410#define USB_INCSR_SENDSTALL 0x10 2410#define USB_INCSR_SENDSTALL 0x10
2411#define USB_INCSR_FF 0x08 2411#define USB_INCSR_FF 0x08
2412#define USB_INCSR_UNDERRUN 0x04 2412#define USB_INCSR_UNDERRUN 0x04
2413#define USB_INCSR_FFNOTEMPT 0x02 2413#define USB_INCSR_FFNOTEMPT 0x02
2414#define USB_INCSR_INPKTRDY 0x01 2414#define USB_INCSR_INPKTRDY 0x01
2415#define USB_OUTCSRH_AUTOCLR 0x80 2415#define USB_OUTCSRH_AUTOCLR 0x80
2416#define USB_OUTCSRH_ISO 0x40 2416#define USB_OUTCSRH_ISO 0x40
2417#define USB_OUTCSRH_DMAREQENAB 0x20 2417#define USB_OUTCSRH_DMAREQENAB 0x20
2418#define USB_OUTCSRH_DNYT 0x10 2418#define USB_OUTCSRH_DNYT 0x10
2419#define USB_OUTCSRH_DMAREQMODE 0x08 2419#define USB_OUTCSRH_DMAREQMODE 0x08
2420#define USB_OUTCSR_CDT 0x80 2420#define USB_OUTCSR_CDT 0x80
2421#define USB_OUTCSR_SENTSTALL 0x40 2421#define USB_OUTCSR_SENTSTALL 0x40
2422#define USB_OUTCSR_SENDSTALL 0x20 2422#define USB_OUTCSR_SENDSTALL 0x20
2423#define USB_OUTCSR_FF 0x10 2423#define USB_OUTCSR_FF 0x10
2424#define USB_OUTCSR_DATAERR 0x08 2424#define USB_OUTCSR_DATAERR 0x08
2425#define USB_OUTCSR_OVERRUN 0x04 2425#define USB_OUTCSR_OVERRUN 0x04
2426#define USB_OUTCSR_FFFULL 0x02 2426#define USB_OUTCSR_FFFULL 0x02
2427#define USB_OUTCSR_OUTPKTRDY 0x01 2427#define USB_OUTCSR_OUTPKTRDY 0x01
2428 2428
2429/* Testmode register bits */ 2429/* Testmode register bits */
2430#define USB_TEST_SE0NAK 0x01 2430#define USB_TEST_SE0NAK 0x01
2431#define USB_TEST_J 0x02 2431#define USB_TEST_J 0x02
2432#define USB_TEST_K 0x04 2432#define USB_TEST_K 0x04
2433#define USB_TEST_PACKET 0x08 2433#define USB_TEST_PACKET 0x08
2434 2434
2435/* DMA control bits */ 2435/* DMA control bits */
2436#define USB_CNTL_ENA 0x01 2436#define USB_CNTL_ENA 0x01
2437#define USB_CNTL_DIR_IN 0x02 2437#define USB_CNTL_DIR_IN 0x02
2438#define USB_CNTL_MODE_1 0x04 2438#define USB_CNTL_MODE_1 0x04
2439#define USB_CNTL_INTR_EN 0x08 2439#define USB_CNTL_INTR_EN 0x08
2440#define USB_CNTL_EP(n) ((n) << 4) 2440#define USB_CNTL_EP(n) ((n) << 4)
2441#define USB_CNTL_BURST_0 (0 << 9) 2441#define USB_CNTL_BURST_0 (0 << 9)
2442#define USB_CNTL_BURST_4 (1 << 9) 2442#define USB_CNTL_BURST_4 (1 << 9)
2443#define USB_CNTL_BURST_8 (2 << 9) 2443#define USB_CNTL_BURST_8 (2 << 9)
2444#define USB_CNTL_BURST_16 (3 << 9) 2444#define USB_CNTL_BURST_16 (3 << 9)
2445 2445
2446 2446
2447//---------------------------------------------------------------------- 2447//----------------------------------------------------------------------
2448// 2448//
2449// Module Operation Definitions 2449// Module Operation Definitions
2450// 2450//
2451//---------------------------------------------------------------------- 2451//----------------------------------------------------------------------
2452#ifndef __ASSEMBLY__ 2452#ifndef __ASSEMBLY__
2453 2453
2454/*************************************************************************** 2454/***************************************************************************
2455 * GPIO 2455 * GPIO
2456 ***************************************************************************/ 2456 ***************************************************************************/
2457 2457
2458//------------------------------------------------------ 2458//------------------------------------------------------
2459// GPIO Pins Description 2459// GPIO Pins Description
2460// 2460//
2461// PORT 0: 2461// PORT 0:
2462// 2462//
2463// PIN/BIT N FUNC0 FUNC1 2463// PIN/BIT N FUNC0 FUNC1
2464// 0 D0 - 2464// 0 D0 -
2465// 1 D1 - 2465// 1 D1 -
2466// 2 D2 - 2466// 2 D2 -
2467// 3 D3 - 2467// 3 D3 -
2468// 4 D4 - 2468// 4 D4 -
2469// 5 D5 - 2469// 5 D5 -
2470// 6 D6 - 2470// 6 D6 -
2471// 7 D7 - 2471// 7 D7 -
2472// 8 D8 - 2472// 8 D8 -
2473// 9 D9 - 2473// 9 D9 -
2474// 10 D10 - 2474// 10 D10 -
2475// 11 D11 - 2475// 11 D11 -
2476// 12 D12 - 2476// 12 D12 -
2477// 13 D13 - 2477// 13 D13 -
2478// 14 D14 - 2478// 14 D14 -
2479// 15 D15 - 2479// 15 D15 -
2480// 16 D16 - 2480// 16 D16 -
2481// 17 D17 - 2481// 17 D17 -
2482// 18 D18 - 2482// 18 D18 -
2483// 19 D19 - 2483// 19 D19 -
2484// 20 D20 - 2484// 20 D20 -
2485// 21 D21 - 2485// 21 D21 -
2486// 22 D22 - 2486// 22 D22 -
2487// 23 D23 - 2487// 23 D23 -
2488// 24 D24 - 2488// 24 D24 -
2489// 25 D25 - 2489// 25 D25 -
2490// 26 D26 - 2490// 26 D26 -
2491// 27 D27 - 2491// 27 D27 -
2492// 28 D28 - 2492// 28 D28 -
2493// 29 D29 - 2493// 29 D29 -
2494// 30 D30 - 2494// 30 D30 -
2495// 31 D31 - 2495// 31 D31 -
2496// 2496//
2497//------------------------------------------------------ 2497//------------------------------------------------------
2498// PORT 1: 2498// PORT 1:
2499// 2499//
2500// PIN/BIT N FUNC0 FUNC1 2500// PIN/BIT N FUNC0 FUNC1
2501// 0 A0 - 2501// 0 A0 -
2502// 1 A1 - 2502// 1 A1 -
2503// 2 A2 - 2503// 2 A2 -
2504// 3 A3 - 2504// 3 A3 -
2505// 4 A4 - 2505// 4 A4 -
2506// 5 A5 - 2506// 5 A5 -
2507// 6 A6 - 2507// 6 A6 -
2508// 7 A7 - 2508// 7 A7 -
2509// 8 A8 - 2509// 8 A8 -
2510// 9 A9 - 2510// 9 A9 -
2511// 10 A10 - 2511// 10 A10 -
2512// 11 A11 - 2512// 11 A11 -
2513// 12 A12 - 2513// 12 A12 -
2514// 13 A13 - 2514// 13 A13 -
2515// 14 A14 - 2515// 14 A14 -
2516// 15 A15/CL - 2516// 15 A15/CL -
2517// 16 A16/AL - 2517// 16 A16/AL -
2518// 17 LCD_CLS A21 2518// 17 LCD_CLS A21
2519// 18 LCD_SPL A22 2519// 18 LCD_SPL A22
2520// 19 DCS# - 2520// 19 DCS# -
2521// 20 RAS# - 2521// 20 RAS# -
2522// 21 CAS# - 2522// 21 CAS# -
2523// 22 RDWE#/BUFD# - 2523// 22 RDWE#/BUFD# -
2524// 23 CKE - 2524// 23 CKE -
2525// 24 CKO - 2525// 24 CKO -
2526// 25 CS1# - 2526// 25 CS1# -
2527// 26 CS2# - 2527// 26 CS2# -
2528// 27 CS3# - 2528// 27 CS3# -
2529// 28 CS4# - 2529// 28 CS4# -
2530// 29 RD# - 2530// 29 RD# -
2531// 30 WR# - 2531// 30 WR# -
2532// 31 WE0# - 2532// 31 WE0# -
2533// 2533//
2534// Note: PIN15&16 are CL&AL when connecting to NAND flash. 2534// Note: PIN15&16 are CL&AL when connecting to NAND flash.
2535//------------------------------------------------------ 2535//------------------------------------------------------
2536// PORT 2: 2536// PORT 2:
2537// 2537//
2538// PIN/BIT N FUNC0 FUNC1 2538// PIN/BIT N FUNC0 FUNC1
2539// 0 LCD_D0 - 2539// 0 LCD_D0 -
2540// 1 LCD_D1 - 2540// 1 LCD_D1 -
2541// 2 LCD_D2 - 2541// 2 LCD_D2 -
2542// 3 LCD_D3 - 2542// 3 LCD_D3 -
2543// 4 LCD_D4 - 2543// 4 LCD_D4 -
2544// 5 LCD_D5 - 2544// 5 LCD_D5 -
2545// 6 LCD_D6 - 2545// 6 LCD_D6 -
2546// 7 LCD_D7 - 2546// 7 LCD_D7 -
2547// 8 LCD_D8 - 2547// 8 LCD_D8 -
2548// 9 LCD_D9 - 2548// 9 LCD_D9 -
2549// 10 LCD_D10 - 2549// 10 LCD_D10 -
2550// 11 LCD_D11 - 2550// 11 LCD_D11 -
2551// 12 LCD_D12 - 2551// 12 LCD_D12 -
2552// 13 LCD_D13 - 2552// 13 LCD_D13 -
2553// 14 LCD_D14 - 2553// 14 LCD_D14 -
2554// 15 LCD_D15 - 2554// 15 LCD_D15 -
2555// 16 LCD_D16 - 2555// 16 LCD_D16 -
2556// 17 LCD_D17 - 2556// 17 LCD_D17 -
2557// 18 LCD_PCLK - 2557// 18 LCD_PCLK -
2558// 19 LCD_HSYNC - 2558// 19 LCD_HSYNC -
2559// 20 LCD_VSYNC - 2559// 20 LCD_VSYNC -
2560// 21 LCD_DE - 2560// 21 LCD_DE -
2561// 22 LCD_PS A19 2561// 22 LCD_PS A19
2562// 23 LCD_REV A20 2562// 23 LCD_REV A20
2563// 24 WE1# - 2563// 24 WE1# -
2564// 25 WE2# - 2564// 25 WE2# -
2565// 26 WE3# - 2565// 26 WE3# -
2566// 27 WAIT# - 2566// 27 WAIT# -
2567// 28 FRE# - 2567// 28 FRE# -
2568// 29 FWE# - 2568// 29 FWE# -
2569// 30(NOTE:FRB#) - - 2569// 30(NOTE:FRB#) - -
2570// 31 - - 2570// 31 - -
2571// 2571//
2572// NOTE(1): PIN30 is used for FRB# when connecting to NAND flash. 2572// NOTE(1): PIN30 is used for FRB# when connecting to NAND flash.
2573//------------------------------------------------------ 2573//------------------------------------------------------
2574// PORT 3: 2574// PORT 3:
2575// 2575//
2576// PIN/BIT N FUNC0 FUNC1 2576// PIN/BIT N FUNC0 FUNC1
2577// 0 CIM_D0 - 2577// 0 CIM_D0 -
2578// 1 CIM_D1 - 2578// 1 CIM_D1 -
2579// 2 CIM_D2 - 2579// 2 CIM_D2 -
2580// 3 CIM_D3 - 2580// 3 CIM_D3 -
2581// 4 CIM_D4 - 2581// 4 CIM_D4 -
2582// 5 CIM_D5 - 2582// 5 CIM_D5 -
2583// 6 CIM_D6 - 2583// 6 CIM_D6 -
2584// 7 CIM_D7 - 2584// 7 CIM_D7 -
2585// 8 MSC_CMD - 2585// 8 MSC_CMD -
2586// 9 MSC_CLK - 2586// 9 MSC_CLK -
2587// 10 MSC_D0 - 2587// 10 MSC_D0 -
2588// 11 MSC_D1 - 2588// 11 MSC_D1 -
2589// 12 MSC_D2 - 2589// 12 MSC_D2 -
2590// 13 MSC_D3 - 2590// 13 MSC_D3 -
2591// 14 CIM_MCLK - 2591// 14 CIM_MCLK -
2592// 15 CIM_PCLK - 2592// 15 CIM_PCLK -
2593// 16 CIM_VSYNC - 2593// 16 CIM_VSYNC -
2594// 17 CIM_HSYNC - 2594// 17 CIM_HSYNC -
2595// 18 SSI_CLK SCLK_RSTN 2595// 18 SSI_CLK SCLK_RSTN
2596// 19 SSI_CE0# BIT_CLK(AIC) 2596// 19 SSI_CE0# BIT_CLK(AIC)
2597// 20 SSI_DT SDATA_OUT(AIC) 2597// 20 SSI_DT SDATA_OUT(AIC)
2598// 21 SSI_DR SDATA_IN(AIC) 2598// 21 SSI_DR SDATA_IN(AIC)
2599// 22 SSI_CE1#&GPC SYNC(AIC) 2599// 22 SSI_CE1#&GPC SYNC(AIC)
2600// 23 PWM0 I2C_SDA 2600// 23 PWM0 I2C_SDA
2601// 24 PWM1 I2C_SCK 2601// 24 PWM1 I2C_SCK
2602// 25 PWM2 UART0_TxD 2602// 25 PWM2 UART0_TxD
2603// 26 PWM3 UART0_RxD 2603// 26 PWM3 UART0_RxD
2604// 27 PWM4 A17 2604// 27 PWM4 A17
2605// 28 PWM5 A18 2605// 28 PWM5 A18
2606// 29 - - 2606// 29 - -
2607// 30 PWM6 UART0_CTS/UART1_RxD 2607// 30 PWM6 UART0_CTS/UART1_RxD
2608// 31 PWM7 UART0_RTS/UART1_TxD 2608// 31 PWM7 UART0_RTS/UART1_TxD
2609// 2609//
2610////////////////////////////////////////////////////////// 2610//////////////////////////////////////////////////////////
2611 2611
2612/* 2612/*
2613 * p is the port number (0,1,2,3) 2613 * p is the port number (0,1,2,3)
2614 * o is the pin offset (0-31) inside the port 2614 * o is the pin offset (0-31) inside the port
2615 * n is the absolute number of a pin (0-127), regardless of the port 2615 * n is the absolute number of a pin (0-127), regardless of the port
2616 */ 2616 */
2617 2617
2618//------------------------------------------- 2618//-------------------------------------------
2619// Function Pins Mode 2619// Function Pins Mode
2620 2620
2621#define __gpio_as_func0(n) \ 2621#define __gpio_as_func0(n) \
2622do { \ 2622do { \
2623 unsigned int p, o; \ 2623 unsigned int p, o; \
2624 p = (n) / 32; \ 2624 p = (n) / 32; \
2625 o = (n) % 32; \ 2625 o = (n) % 32; \
2626 REG_GPIO_PXFUNS(p) = (1 << o); \ 2626 REG_GPIO_PXFUNS(p) = (1 << o); \
2627 REG_GPIO_PXSELC(p) = (1 << o); \ 2627 REG_GPIO_PXSELC(p) = (1 << o); \
2628} while (0) 2628} while (0)
2629 2629
2630#define __gpio_as_func1(n) \ 2630#define __gpio_as_func1(n) \
2631do { \ 2631do { \
2632 unsigned int p, o; \ 2632 unsigned int p, o; \
2633 p = (n) / 32; \ 2633 p = (n) / 32; \
2634 o = (n) % 32; \ 2634 o = (n) % 32; \
2635 REG_GPIO_PXFUNS(p) = (1 << o); \ 2635 REG_GPIO_PXFUNS(p) = (1 << o); \
2636 REG_GPIO_PXSELS(p) = (1 << o); \ 2636 REG_GPIO_PXSELS(p) = (1 << o); \
2637} while (0) 2637} while (0)
2638 2638
2639/* 2639/*
2640 * D0 ~ D31, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, 2640 * D0 ~ D31, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
2641 * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3# 2641 * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3#
2642 */ 2642 */
2643#define __gpio_as_sdram_32bit() \ 2643#define __gpio_as_sdram_32bit() \
2644do { \ 2644do { \
2645 REG_GPIO_PXFUNS(0) = 0xffffffff; \ 2645 REG_GPIO_PXFUNS(0) = 0xffffffff; \
2646 REG_GPIO_PXSELC(0) = 0xffffffff; \ 2646 REG_GPIO_PXSELC(0) = 0xffffffff; \
2647 REG_GPIO_PXPES(0) = 0xffffffff; \ 2647 REG_GPIO_PXPES(0) = 0xffffffff; \
2648 REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ 2648 REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
2649 REG_GPIO_PXSELC(1) = 0x81f9ffff; \ 2649 REG_GPIO_PXSELC(1) = 0x81f9ffff; \
2650 REG_GPIO_PXPES(1) = 0x81f9ffff; \ 2650 REG_GPIO_PXPES(1) = 0x81f9ffff; \
2651 REG_GPIO_PXFUNS(2) = 0x07000000; \ 2651 REG_GPIO_PXFUNS(2) = 0x07000000; \
2652 REG_GPIO_PXSELC(2) = 0x07000000; \ 2652 REG_GPIO_PXSELC(2) = 0x07000000; \
2653 REG_GPIO_PXPES(2) = 0x07000000; \ 2653 REG_GPIO_PXPES(2) = 0x07000000; \
2654} while (0) 2654} while (0)
2655 2655
2656//#ifdef JZ4740_PAVO 2656//#ifdef JZ4740_PAVO
2657#ifdef JZ4740_4740 2657#ifdef JZ4740_4740
2658/* 2658/*
2659 * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, 2659 * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
2660 * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3# 2660 * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3#
2661 */ 2661 */
2662#define __gpio_as_sdram_16bit() \ 2662#define __gpio_as_sdram_16bit() \
2663do { \ 2663do { \
2664 REG_GPIO_PXFUNS(0) = 0x0000ffff; \ 2664 REG_GPIO_PXFUNS(0) = 0x0000ffff; \
2665 REG_GPIO_PXFUNS(0) = 0x0000ffff; \ 2665 REG_GPIO_PXFUNS(0) = 0x0000ffff; \
2666 REG_GPIO_PXPES(0) = 0x0000ffff; \ 2666 REG_GPIO_PXPES(0) = 0x0000ffff; \
2667 REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ 2667 REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
2668 REG_GPIO_PXSELC(1) = 0x81f9ffff; \ 2668 REG_GPIO_PXSELC(1) = 0x81f9ffff; \
2669 REG_GPIO_PXPES(1) = 0x81f9ffff; \ 2669 REG_GPIO_PXPES(1) = 0x81f9ffff; \
2670 REG_GPIO_PXFUNS(2) = 0x07000000; \ 2670 REG_GPIO_PXFUNS(2) = 0x07000000; \
2671 REG_GPIO_PXSELC(2) = 0x07000000; \ 2671 REG_GPIO_PXSELC(2) = 0x07000000; \
2672 REG_GPIO_PXPES(2) = 0x07000000; \ 2672 REG_GPIO_PXPES(2) = 0x07000000; \
2673} while (0) 2673} while (0)
2674 2674
2675#endif 2675#endif
2676 2676
2677//#ifdef JZ4740_VIRGO 2677//#ifdef JZ4740_VIRGO
2678#ifdef JZ4740_4720 2678#ifdef JZ4740_4720
2679/* 2679/*
2680 * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, 2680 * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
2681 * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3# 2681 * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3#
2682 */ 2682 */
2683#define __gpio_as_sdram_16bit() \ 2683#define __gpio_as_sdram_16bit() \
2684do { \ 2684do { \
2685 REG_GPIO_PXFUNS(0) = 0x5442bfaa; \ 2685 REG_GPIO_PXFUNS(0) = 0x5442bfaa; \
2686 REG_GPIO_PXSELC(0) = 0x5442bfaa; \ 2686 REG_GPIO_PXSELC(0) = 0x5442bfaa; \
2687 REG_GPIO_PXPES(0) = 0x5442bfaa; \ 2687 REG_GPIO_PXPES(0) = 0x5442bfaa; \
2688 REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ 2688 REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
2689 REG_GPIO_PXSELC(1) = 0x81f9ffff; \ 2689 REG_GPIO_PXSELC(1) = 0x81f9ffff; \
2690 REG_GPIO_PXPES(1) = 0x81f9ffff; \ 2690 REG_GPIO_PXPES(1) = 0x81f9ffff; \
2691 REG_GPIO_PXFUNS(2) = 0x01000000; \ 2691 REG_GPIO_PXFUNS(2) = 0x01000000; \
2692 REG_GPIO_PXSELC(2) = 0x01000000; \ 2692 REG_GPIO_PXSELC(2) = 0x01000000; \
2693 REG_GPIO_PXPES(2) = 0x01000000; \ 2693 REG_GPIO_PXPES(2) = 0x01000000; \
2694} while (0) 2694} while (0)
2695#endif 2695#endif
2696 2696
2697 2697
2698#ifdef JZ4740_4725 2698#ifdef JZ4740_4725
2699/* 2699/*
2700 * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, 2700 * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
2701 * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3# 2701 * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3#
2702 */ 2702 */
2703#define __jz4725__gpio_as_sdram_16bit() \ 2703#define __jz4725__gpio_as_sdram_16bit() \
2704do { \ 2704do { \
2705 REG_GPIO_PXFUNS(0) = 0x0000ffff; \ 2705 REG_GPIO_PXFUNS(0) = 0x0000ffff; \
2706 REG_GPIO_PXSELC(0) = 0x0000ffff; \ 2706 REG_GPIO_PXSELC(0) = 0x0000ffff; \
2707 REG_GPIO_PXPES(0) = 0x0000ffff; \ 2707 REG_GPIO_PXPES(0) = 0x0000ffff; \
2708 REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ 2708 REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
2709 REG_GPIO_PXSELC(1) = 0x81f9ffff; \ 2709 REG_GPIO_PXSELC(1) = 0x81f9ffff; \
2710 REG_GPIO_PXPES(1) = 0x81f9ffff; \ 2710 REG_GPIO_PXPES(1) = 0x81f9ffff; \
2711 REG_GPIO_PXFUNS(2) = 0x07000000; \ 2711 REG_GPIO_PXFUNS(2) = 0x07000000; \
2712 REG_GPIO_PXSELC(2) = 0x07000000; \ 2712 REG_GPIO_PXSELC(2) = 0x07000000; \
2713 REG_GPIO_PXPES(2) = 0x07000000; \ 2713 REG_GPIO_PXPES(2) = 0x07000000; \
2714} while (0) 2714} while (0)
2715#endif 2715#endif
2716/* 2716/*
2717 * CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD# 2717 * CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD#
2718 */ 2718 */
2719#define __gpio_as_nand() \ 2719#define __gpio_as_nand() \
2720do { \ 2720do { \
2721 REG_GPIO_PXFUNS(1) = 0x02018000; \ 2721 REG_GPIO_PXFUNS(1) = 0x02018000; \
2722 REG_GPIO_PXSELC(1) = 0x02018000; \ 2722 REG_GPIO_PXSELC(1) = 0x02018000; \
2723 REG_GPIO_PXPES(1) = 0x02018000; \ 2723 REG_GPIO_PXPES(1) = 0x02018000; \
2724 REG_GPIO_PXFUNS(2) = 0x30000000; \ 2724 REG_GPIO_PXFUNS(2) = 0x30000000; \
2725 REG_GPIO_PXSELC(2) = 0x30000000; \ 2725 REG_GPIO_PXSELC(2) = 0x30000000; \
2726 REG_GPIO_PXPES(2) = 0x30000000; \ 2726 REG_GPIO_PXPES(2) = 0x30000000; \
2727 REG_GPIO_PXFUNC(2) = 0x40000000; \ 2727 REG_GPIO_PXFUNC(2) = 0x40000000; \
2728 REG_GPIO_PXSELC(2) = 0x40000000; \ 2728 REG_GPIO_PXSELC(2) = 0x40000000; \
2729 REG_GPIO_PXDIRC(2) = 0x40000000; \ 2729 REG_GPIO_PXDIRC(2) = 0x40000000; \
2730 REG_GPIO_PXPES(2) = 0x40000000; \ 2730 REG_GPIO_PXPES(2) = 0x40000000; \
2731 REG_GPIO_PXFUNS(1) = 0x00400000; \ 2731 REG_GPIO_PXFUNS(1) = 0x00400000; \
2732 REG_GPIO_PXSELC(1) = 0x00400000; \ 2732 REG_GPIO_PXSELC(1) = 0x00400000; \
2733} while (0) 2733} while (0)
2734 2734
2735/* 2735/*
2736 * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D7 2736 * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D7
2737 */ 2737 */
2738#define __gpio_as_nor_8bit() \ 2738#define __gpio_as_nor_8bit() \
2739do { \ 2739do { \
2740 REG_GPIO_PXFUNS(0) = 0x000000ff; \ 2740 REG_GPIO_PXFUNS(0) = 0x000000ff; \
2741 REG_GPIO_PXSELC(0) = 0x000000ff; \ 2741 REG_GPIO_PXSELC(0) = 0x000000ff; \
2742 REG_GPIO_PXPES(0) = 0x000000ff; \ 2742 REG_GPIO_PXPES(0) = 0x000000ff; \
2743 REG_GPIO_PXFUNS(1) = 0x7041ffff; \ 2743 REG_GPIO_PXFUNS(1) = 0x7041ffff; \
2744 REG_GPIO_PXSELC(1) = 0x7041ffff; \ 2744 REG_GPIO_PXSELC(1) = 0x7041ffff; \
2745 REG_GPIO_PXPES(1) = 0x7041ffff; \ 2745 REG_GPIO_PXPES(1) = 0x7041ffff; \
2746 REG_GPIO_PXFUNS(1) = 0x00060000; \ 2746 REG_GPIO_PXFUNS(1) = 0x00060000; \
2747 REG_GPIO_PXSELS(1) = 0x00060000; \ 2747 REG_GPIO_PXSELS(1) = 0x00060000; \
2748 REG_GPIO_PXPES(1) = 0x00060000; \ 2748 REG_GPIO_PXPES(1) = 0x00060000; \
2749 REG_GPIO_PXFUNS(2) = 0x08000000; \ 2749 REG_GPIO_PXFUNS(2) = 0x08000000; \
2750 REG_GPIO_PXSELC(2) = 0x08000000; \ 2750 REG_GPIO_PXSELC(2) = 0x08000000; \
2751 REG_GPIO_PXPES(2) = 0x08000000; \ 2751 REG_GPIO_PXPES(2) = 0x08000000; \
2752 REG_GPIO_PXFUNS(2) = 0x00c00000; \ 2752 REG_GPIO_PXFUNS(2) = 0x00c00000; \
2753 REG_GPIO_PXSELS(2) = 0x00c00000; \ 2753 REG_GPIO_PXSELS(2) = 0x00c00000; \
2754 REG_GPIO_PXPES(2) = 0x00c00000; \ 2754 REG_GPIO_PXPES(2) = 0x00c00000; \
2755 REG_GPIO_PXFUNS(3) = 0x18000000; \ 2755 REG_GPIO_PXFUNS(3) = 0x18000000; \
2756 REG_GPIO_PXSELS(3) = 0x18000000; \ 2756 REG_GPIO_PXSELS(3) = 0x18000000; \
2757 REG_GPIO_PXPES(3) = 0x18000000; \ 2757 REG_GPIO_PXPES(3) = 0x18000000; \
2758} while (0) 2758} while (0)
2759 2759
2760/* 2760/*
2761 * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D15 2761 * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D15
2762 */ 2762 */
2763#define __gpio_as_nor_16bit() \ 2763#define __gpio_as_nor_16bit() \
2764do { \ 2764do { \
2765 REG_GPIO_PXFUNS(0) = 0x0000ffff; \ 2765 REG_GPIO_PXFUNS(0) = 0x0000ffff; \
2766 REG_GPIO_PXSELC(0) = 0x0000ffff; \ 2766 REG_GPIO_PXSELC(0) = 0x0000ffff; \
2767 REG_GPIO_PXPES(0) = 0x0000ffff; \ 2767 REG_GPIO_PXPES(0) = 0x0000ffff; \
2768 REG_GPIO_PXFUNS(1) = 0x7041ffff; \ 2768 REG_GPIO_PXFUNS(1) = 0x7041ffff; \
2769 REG_GPIO_PXSELC(1) = 0x7041ffff; \ 2769 REG_GPIO_PXSELC(1) = 0x7041ffff; \
2770 REG_GPIO_PXPES(1) = 0x7041ffff; \ 2770 REG_GPIO_PXPES(1) = 0x7041ffff; \
2771 REG_GPIO_PXFUNS(1) = 0x00060000; \ 2771 REG_GPIO_PXFUNS(1) = 0x00060000; \
2772 REG_GPIO_PXSELS(1) = 0x00060000; \ 2772 REG_GPIO_PXSELS(1) = 0x00060000; \
2773 REG_GPIO_PXPES(1) = 0x00060000; \ 2773 REG_GPIO_PXPES(1) = 0x00060000; \
2774 REG_GPIO_PXFUNS(2) = 0x08000000; \ 2774 REG_GPIO_PXFUNS(2) = 0x08000000; \
2775 REG_GPIO_PXSELC(2) = 0x08000000; \ 2775 REG_GPIO_PXSELC(2) = 0x08000000; \
2776 REG_GPIO_PXPES(2) = 0x08000000; \ 2776 REG_GPIO_PXPES(2) = 0x08000000; \
2777 REG_GPIO_PXFUNS(2) = 0x00c00000; \ 2777 REG_GPIO_PXFUNS(2) = 0x00c00000; \
2778 REG_GPIO_PXSELS(2) = 0x00c00000; \ 2778 REG_GPIO_PXSELS(2) = 0x00c00000; \
2779 REG_GPIO_PXPES(2) = 0x00c00000; \ 2779 REG_GPIO_PXPES(2) = 0x00c00000; \
2780 REG_GPIO_PXFUNS(3) = 0x18000000; \ 2780 REG_GPIO_PXFUNS(3) = 0x18000000; \
2781 REG_GPIO_PXSELS(3) = 0x18000000; \ 2781 REG_GPIO_PXSELS(3) = 0x18000000; \
2782 REG_GPIO_PXPES(3) = 0x18000000; \ 2782 REG_GPIO_PXPES(3) = 0x18000000; \
2783} while (0) 2783} while (0)
2784 2784
2785/* 2785/*
2786 * UART0_TxD, UART_RxD0 2786 * UART0_TxD, UART_RxD0
2787 */ 2787 */
2788#define __gpio_as_uart0() \ 2788#define __gpio_as_uart0() \
2789do { \ 2789do { \
2790 REG_GPIO_PXFUNS(3) = 0x06000000; \ 2790 REG_GPIO_PXFUNS(3) = 0x06000000; \
2791 REG_GPIO_PXSELS(3) = 0x06000000; \ 2791 REG_GPIO_PXSELS(3) = 0x06000000; \
2792 REG_GPIO_PXPES(3) = 0x06000000; \ 2792 REG_GPIO_PXPES(3) = 0x06000000; \
2793} while (0) 2793} while (0)
2794 2794
2795/* 2795/*
2796 * UART1_TxD, UART1_RxD1 2796 * UART1_TxD, UART1_RxD1
2797 */ 2797 */
2798#define __gpio_as_uart1() \ 2798#define __gpio_as_uart1() \
2799do { \ 2799do { \
2800 REG_GPIO_PXFUNS(3) = 0xc0000000; \ 2800 REG_GPIO_PXFUNS(3) = 0xc0000000; \
2801 REG_GPIO_PXSELS(3) = 0xc0000000; \ 2801 REG_GPIO_PXSELS(3) = 0xc0000000; \
2802 REG_GPIO_PXPES(3) = 0xc0000000; \ 2802 REG_GPIO_PXPES(3) = 0xc0000000; \
2803} while (0) 2803} while (0)
2804 2804
2805/* 2805/*
2806 * LCD_D0~LCD_D15, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE 2806 * LCD_D0~LCD_D15, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
2807 */ 2807 */
2808#define __gpio_as_lcd_16bit() \ 2808#define __gpio_as_lcd_16bit() \
2809do { \ 2809do { \
2810 REG_GPIO_PXFUNS(2) = 0x003cffff; \ 2810 REG_GPIO_PXFUNS(2) = 0x003cffff; \
2811 REG_GPIO_PXSELC(2) = 0x003cffff; \ 2811 REG_GPIO_PXSELC(2) = 0x003cffff; \
2812 REG_GPIO_PXPES(2) = 0x003cffff; \ 2812 REG_GPIO_PXPES(2) = 0x003cffff; \
2813} while (0) 2813} while (0)
2814 2814
2815/* 2815/*
2816 * LCD_D0~LCD_D17, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE 2816 * LCD_D0~LCD_D17, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
2817 */ 2817 */
2818#define __gpio_as_lcd_18bit() \ 2818#define __gpio_as_lcd_18bit() \
2819do { \ 2819do { \
2820 REG_GPIO_PXFUNS(2) = 0x003fffff; \ 2820 REG_GPIO_PXFUNS(2) = 0x003fffff; \
2821 REG_GPIO_PXSELC(2) = 0x003fffff; \ 2821 REG_GPIO_PXSELC(2) = 0x003fffff; \
2822 REG_GPIO_PXPES(2) = 0x003fffff; \ 2822 REG_GPIO_PXPES(2) = 0x003fffff; \
2823} while (0) 2823} while (0)
2824 2824
2825 2825
2826/* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */ 2826/* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */
2827#define __gpio_as_slcd_8bit() \ 2827#define __gpio_as_slcd_8bit() \
2828do { \ 2828do { \
2829 REG_GPIO_PXFUNS(2) = 0x001800ff; \ 2829 REG_GPIO_PXFUNS(2) = 0x001800ff; \
2830 REG_GPIO_PXSELC(2) = 0x001800ff; \ 2830 REG_GPIO_PXSELC(2) = 0x001800ff; \
2831} while (0) 2831} while (0)
2832 2832
2833/* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */ 2833/* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */
2834#define __gpio_as_slcd_9bit() \ 2834#define __gpio_as_slcd_9bit() \
2835do { \ 2835do { \
2836 REG_GPIO_PXFUNS(2) = 0x001801ff; \ 2836 REG_GPIO_PXFUNS(2) = 0x001801ff; \
2837 REG_GPIO_PXSELC(2) = 0x001801ff; \ 2837 REG_GPIO_PXSELC(2) = 0x001801ff; \
2838} while (0) 2838} while (0)
2839 2839
2840/* LCD_D0~LCD_D15, SLCD_RS, SLCD_CS */ 2840/* LCD_D0~LCD_D15, SLCD_RS, SLCD_CS */
2841#define __gpio_as_slcd_16bit() \ 2841#define __gpio_as_slcd_16bit() \
2842do { \ 2842do { \
2843 REG_GPIO_PXFUNS(2) = 0x0018ffff; \ 2843 REG_GPIO_PXFUNS(2) = 0x0018ffff; \
2844 REG_GPIO_PXSELC(2) = 0x0018ffff; \ 2844 REG_GPIO_PXSELC(2) = 0x0018ffff; \
2845} while (0) 2845} while (0)
2846 2846
2847/* LCD_D0~LCD_D17, SLCD_RS, SLCD_CS */ 2847/* LCD_D0~LCD_D17, SLCD_RS, SLCD_CS */
2848#define __gpio_as_slcd_18bit() \ 2848#define __gpio_as_slcd_18bit() \
2849do { \ 2849do { \
2850 REG_GPIO_PXFUNS(2) = 0x001bffff; \ 2850 REG_GPIO_PXFUNS(2) = 0x001bffff; \
2851 REG_GPIO_PXSELC(2) = 0x001bffff; \ 2851 REG_GPIO_PXSELC(2) = 0x001bffff; \
2852} while (0) 2852} while (0)
2853 2853
2854/* 2854/*
2855 * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC 2855 * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC
2856 */ 2856 */
2857#define __gpio_as_cim() \ 2857#define __gpio_as_cim() \
2858do { \ 2858do { \
2859 REG_GPIO_PXFUNS(3) = 0x0003c0ff; \ 2859 REG_GPIO_PXFUNS(3) = 0x0003c0ff; \
2860 REG_GPIO_PXSELC(3) = 0x0003c0ff; \ 2860 REG_GPIO_PXSELC(3) = 0x0003c0ff; \
2861 REG_GPIO_PXPES(3) = 0x0003c0ff; \ 2861 REG_GPIO_PXPES(3) = 0x0003c0ff; \
2862} while (0) 2862} while (0)
2863 2863
2864/* 2864/*
2865 * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET 2865 * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET
2866 */ 2866 */
2867#define __gpio_as_aic() \ 2867#define __gpio_as_aic() \
2868do { \ 2868do { \
2869 REG_GPIO_PXFUNS(3) = 0x007c0000; \ 2869 REG_GPIO_PXFUNS(3) = 0x007c0000; \
2870 REG_GPIO_PXSELS(3) = 0x007c0000; \ 2870 REG_GPIO_PXSELS(3) = 0x007c0000; \
2871 REG_GPIO_PXPES(3) = 0x007c0000; \ 2871 REG_GPIO_PXPES(3) = 0x007c0000; \
2872} while (0) 2872} while (0)
2873 2873
2874/* 2874/*
2875 * MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3 2875 * MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3
2876 */ 2876 */
2877#define __gpio_as_msc() \ 2877#define __gpio_as_msc() \
2878do { \ 2878do { \
2879 REG_GPIO_PXFUNS(3) = 0x00003f00; \ 2879 REG_GPIO_PXFUNS(3) = 0x00003f00; \
2880 REG_GPIO_PXSELC(3) = 0x00003f00; \ 2880 REG_GPIO_PXSELC(3) = 0x00003f00; \
2881 REG_GPIO_PXPES(3) = 0x00003f00; \ 2881 REG_GPIO_PXPES(3) = 0x00003f00; \
2882} while (0) 2882} while (0)
2883 2883
2884/* 2884/*
2885 * SSI_CS0, SSI_CLK, SSI_DT, SSI_DR 2885 * SSI_CS0, SSI_CLK, SSI_DT, SSI_DR
2886 */ 2886 */
2887#define __gpio_as_ssi() \ 2887#define __gpio_as_ssi() \
2888do { \ 2888do { \
2889 REG_GPIO_PXFUNS(3) = 0x003c0000; \ 2889 REG_GPIO_PXFUNS(3) = 0x003c0000; \
2890 REG_GPIO_PXSELC(3) = 0x003c0000; \ 2890 REG_GPIO_PXSELC(3) = 0x003c0000; \
2891 REG_GPIO_PXPES(3) = 0x003c0000; \ 2891 REG_GPIO_PXPES(3) = 0x003c0000; \
2892} while (0) 2892} while (0)
2893 2893
2894/* 2894/*
2895 * I2C_SCK, I2C_SDA 2895 * I2C_SCK, I2C_SDA
2896 */ 2896 */
2897#define __gpio_as_i2c() \ 2897#define __gpio_as_i2c() \
2898do { \ 2898do { \
2899 REG_GPIO_PXFUNS(3) = 0x01800000; \ 2899 REG_GPIO_PXFUNS(3) = 0x01800000; \
2900 REG_GPIO_PXSELS(3) = 0x01800000; \ 2900 REG_GPIO_PXSELS(3) = 0x01800000; \
2901 REG_GPIO_PXPES(3) = 0x01800000; \ 2901 REG_GPIO_PXPES(3) = 0x01800000; \
2902} while (0) 2902} while (0)
2903 2903
2904/* 2904/*
2905 * PWM0 2905 * PWM0
2906 */ 2906 */
2907#define __gpio_as_pwm0() \ 2907#define __gpio_as_pwm0() \
2908do { \ 2908do { \
2909 REG_GPIO_PXFUNS(3) = 0x00800000; \ 2909 REG_GPIO_PXFUNS(3) = 0x00800000; \
2910 REG_GPIO_PXSELC(3) = 0x00800000; \ 2910 REG_GPIO_PXSELC(3) = 0x00800000; \
2911 REG_GPIO_PXPES(3) = 0x00800000; \ 2911 REG_GPIO_PXPES(3) = 0x00800000; \
2912} while (0) 2912} while (0)
2913 2913
2914/* 2914/*
2915 * PWM1 2915 * PWM1
2916 */ 2916 */
2917#define __gpio_as_pwm1() \ 2917#define __gpio_as_pwm1() \
2918do { \ 2918do { \
2919 REG_GPIO_PXFUNS(3) = 0x01000000; \ 2919 REG_GPIO_PXFUNS(3) = 0x01000000; \
2920 REG_GPIO_PXSELC(3) = 0x01000000; \ 2920 REG_GPIO_PXSELC(3) = 0x01000000; \
2921 REG_GPIO_PXPES(3) = 0x01000000; \ 2921 REG_GPIO_PXPES(3) = 0x01000000; \
2922} while (0) 2922} while (0)
2923 2923
2924/* 2924/*
2925 * PWM2 2925 * PWM2
2926 */ 2926 */
2927#define __gpio_as_pwm2() \ 2927#define __gpio_as_pwm2() \
2928do { \ 2928do { \
2929 REG_GPIO_PXFUNS(3) = 0x02000000; \ 2929 REG_GPIO_PXFUNS(3) = 0x02000000; \
2930 REG_GPIO_PXSELC(3) = 0x02000000; \ 2930 REG_GPIO_PXSELC(3) = 0x02000000; \
2931 REG_GPIO_PXPES(3) = 0x02000000; \ 2931 REG_GPIO_PXPES(3) = 0x02000000; \
2932} while (0) 2932} while (0)
2933 2933
2934/* 2934/*
2935 * PWM3 2935 * PWM3
2936 */ 2936 */
2937#define __gpio_as_pwm3() \ 2937#define __gpio_as_pwm3() \
2938do { \ 2938do { \
2939 REG_GPIO_PXFUNS(3) = 0x04000000; \ 2939 REG_GPIO_PXFUNS(3) = 0x04000000; \
2940 REG_GPIO_PXSELC(3) = 0x04000000; \ 2940 REG_GPIO_PXSELC(3) = 0x04000000; \
2941 REG_GPIO_PXPES(3) = 0x04000000; \ 2941 REG_GPIO_PXPES(3) = 0x04000000; \
2942} while (0) 2942} while (0)
2943 2943
2944/* 2944/*
2945 * PWM4 2945 * PWM4
2946 */ 2946 */
2947#define __gpio_as_pwm4() \ 2947#define __gpio_as_pwm4() \
2948do { \ 2948do { \
2949 REG_GPIO_PXFUNS(3) = 0x08000000; \ 2949 REG_GPIO_PXFUNS(3) = 0x08000000; \
2950 REG_GPIO_PXSELC(3) = 0x08000000; \ 2950 REG_GPIO_PXSELC(3) = 0x08000000; \
2951 REG_GPIO_PXPES(3) = 0x08000000; \ 2951 REG_GPIO_PXPES(3) = 0x08000000; \
2952} while (0) 2952} while (0)
2953 2953
2954/* 2954/*
2955 * PWM5 2955 * PWM5
2956 */ 2956 */
2957#define __gpio_as_pwm5() \ 2957#define __gpio_as_pwm5() \
2958do { \ 2958do { \
2959 REG_GPIO_PXFUNS(3) = 0x10000000; \ 2959 REG_GPIO_PXFUNS(3) = 0x10000000; \
2960 REG_GPIO_PXSELC(3) = 0x10000000; \ 2960 REG_GPIO_PXSELC(3) = 0x10000000; \
2961 REG_GPIO_PXPES(3) = 0x10000000; \ 2961 REG_GPIO_PXPES(3) = 0x10000000; \
2962} while (0) 2962} while (0)
2963 2963
2964/* 2964/*
2965 * PWM6 2965 * PWM6
2966 */ 2966 */
2967#define __gpio_as_pwm6() \ 2967#define __gpio_as_pwm6() \
2968do { \ 2968do { \
2969 REG_GPIO_PXFUNS(3) = 0x40000000; \ 2969 REG_GPIO_PXFUNS(3) = 0x40000000; \
2970 REG_GPIO_PXSELC(3) = 0x40000000; \ 2970 REG_GPIO_PXSELC(3) = 0x40000000; \
2971 REG_GPIO_PXPES(3) = 0x40000000; \ 2971 REG_GPIO_PXPES(3) = 0x40000000; \
2972} while (0) 2972} while (0)
2973 2973
2974/* 2974/*
2975 * PWM7 2975 * PWM7
2976 */ 2976 */
2977#define __gpio_as_pwm7() \ 2977#define __gpio_as_pwm7() \
2978do { \ 2978do { \
2979 REG_GPIO_PXFUNS(3) = 0x80000000; \ 2979 REG_GPIO_PXFUNS(3) = 0x80000000; \
2980 REG_GPIO_PXSELC(3) = 0x80000000; \ 2980 REG_GPIO_PXSELC(3) = 0x80000000; \
2981 REG_GPIO_PXPES(3) = 0x80000000; \ 2981 REG_GPIO_PXPES(3) = 0x80000000; \
2982} while (0) 2982} while (0)
2983 2983
2984/* 2984/*
2985 * n = 0 ~ 7 2985 * n = 0 ~ 7
2986 */ 2986 */
2987#define __gpio_as_pwm(n) __gpio_as_pwm##n() 2987#define __gpio_as_pwm(n) __gpio_as_pwm##n()
2988 2988
2989//------------------------------------------- 2989//-------------------------------------------
2990// GPIO or Interrupt Mode 2990// GPIO or Interrupt Mode
2991 2991
2992#define __gpio_get_port(p) (REG_GPIO_PXPIN(p)) 2992#define __gpio_get_port(p) (REG_GPIO_PXPIN(p))
2993 2993
2994#define __gpio_port_as_output(p, o) \ 2994#define __gpio_port_as_output(p, o) \
2995do { \ 2995do { \
2996 REG_GPIO_PXFUNC(p) = (1 << (o)); \ 2996 REG_GPIO_PXFUNC(p) = (1 << (o)); \
2997 REG_GPIO_PXSELC(p) = (1 << (o)); \ 2997 REG_GPIO_PXSELC(p) = (1 << (o)); \
2998 REG_GPIO_PXDIRS(p) = (1 << (o)); \ 2998 REG_GPIO_PXDIRS(p) = (1 << (o)); \
2999} while (0) 2999} while (0)
3000 3000
3001#define __gpio_port_as_input(p, o) \ 3001#define __gpio_port_as_input(p, o) \
3002do { \ 3002do { \
3003 REG_GPIO_PXFUNC(p) = (1 << (o)); \ 3003 REG_GPIO_PXFUNC(p) = (1 << (o)); \
3004 REG_GPIO_PXSELC(p) = (1 << (o)); \ 3004 REG_GPIO_PXSELC(p) = (1 << (o)); \
3005 REG_GPIO_PXDIRC(p) = (1 << (o)); \ 3005 REG_GPIO_PXDIRC(p) = (1 << (o)); \
3006} while (0) 3006} while (0)
3007 3007
3008#define __gpio_as_output(n) \ 3008#define __gpio_as_output(n) \
3009do { \ 3009do { \
3010 unsigned int p, o; \ 3010 unsigned int p, o; \
3011 p = (n) / 32; \ 3011 p = (n) / 32; \
3012 o = (n) % 32; \ 3012 o = (n) % 32; \
3013 __gpio_port_as_output(p, o); \ 3013 __gpio_port_as_output(p, o); \
3014} while (0) 3014} while (0)
3015 3015
3016#define __gpio_as_input(n) \ 3016#define __gpio_as_input(n) \
3017do { \ 3017do { \
3018 unsigned int p, o; \ 3018 unsigned int p, o; \
3019 p = (n) / 32; \ 3019 p = (n) / 32; \
3020 o = (n) % 32; \ 3020 o = (n) % 32; \
3021 __gpio_port_as_input(p, o); \ 3021 __gpio_port_as_input(p, o); \
3022} while (0) 3022} while (0)
3023 3023
3024#define __gpio_set_pin(n) \ 3024#define __gpio_set_pin(n) \
3025do { \ 3025do { \
3026 unsigned int p, o; \ 3026 unsigned int p, o; \
3027 p = (n) / 32; \ 3027 p = (n) / 32; \
3028 o = (n) % 32; \ 3028 o = (n) % 32; \
3029 REG_GPIO_PXDATS(p) = (1 << o); \ 3029 REG_GPIO_PXDATS(p) = (1 << o); \
3030} while (0) 3030} while (0)
3031 3031
3032#define __gpio_clear_pin(n) \ 3032#define __gpio_clear_pin(n) \
3033do { \ 3033do { \
3034 unsigned int p, o; \ 3034 unsigned int p, o; \
3035 p = (n) / 32; \ 3035 p = (n) / 32; \
3036 o = (n) % 32; \ 3036 o = (n) % 32; \
3037 REG_GPIO_PXDATC(p) = (1 << o); \ 3037 REG_GPIO_PXDATC(p) = (1 << o); \
3038} while (0) 3038} while (0)
3039 3039
3040#define __gpio_get_pin(n) \ 3040#define __gpio_get_pin(n) \
3041({ \ 3041({ \
3042 unsigned int p, o, v; \ 3042 unsigned int p, o, v; \
3043 p = (n) / 32; \ 3043 p = (n) / 32; \
3044 o = (n) % 32; \ 3044 o = (n) % 32; \
3045 if (__gpio_get_port(p) & (1 << o)) \ 3045 if (__gpio_get_port(p) & (1 << o)) \
3046 v = 1; \ 3046 v = 1; \
3047 else \ 3047 else \
3048 v = 0; \ 3048 v = 0; \
3049 v; \ 3049 v; \
3050}) 3050})
3051 3051
3052#define __gpio_as_irq_high_level(n) \ 3052#define __gpio_as_irq_high_level(n) \
3053do { \ 3053do { \
3054 unsigned int p, o; \ 3054 unsigned int p, o; \
3055 p = (n) / 32; \ 3055 p = (n) / 32; \
3056 o = (n) % 32; \ 3056 o = (n) % 32; \
3057 REG_GPIO_PXIMS(p) = (1 << o); \ 3057 REG_GPIO_PXIMS(p) = (1 << o); \
3058 REG_GPIO_PXTRGC(p) = (1 << o); \ 3058 REG_GPIO_PXTRGC(p) = (1 << o); \
3059 REG_GPIO_PXFUNC(p) = (1 << o); \ 3059 REG_GPIO_PXFUNC(p) = (1 << o); \
3060 REG_GPIO_PXSELS(p) = (1 << o); \ 3060 REG_GPIO_PXSELS(p) = (1 << o); \
3061 REG_GPIO_PXDIRS(p) = (1 << o); \ 3061 REG_GPIO_PXDIRS(p) = (1 << o); \
3062 REG_GPIO_PXFLGC(p) = (1 << o); \ 3062 REG_GPIO_PXFLGC(p) = (1 << o); \
3063 REG_GPIO_PXIMC(p) = (1 << o); \ 3063 REG_GPIO_PXIMC(p) = (1 << o); \
3064} while (0) 3064} while (0)
3065 3065
3066#define __gpio_as_irq_low_level(n) \ 3066#define __gpio_as_irq_low_level(n) \
3067do { \ 3067do { \
3068 unsigned int p, o; \ 3068 unsigned int p, o; \
3069 p = (n) / 32; \ 3069 p = (n) / 32; \
3070 o = (n) % 32; \ 3070 o = (n) % 32; \
3071 REG_GPIO_PXIMS(p) = (1 << o); \ 3071 REG_GPIO_PXIMS(p) = (1 << o); \
3072 REG_GPIO_PXTRGC(p) = (1 << o); \ 3072 REG_GPIO_PXTRGC(p) = (1 << o); \
3073 REG_GPIO_PXFUNC(p) = (1 << o); \ 3073 REG_GPIO_PXFUNC(p) = (1 << o); \
3074 REG_GPIO_PXSELS(p) = (1 << o); \ 3074 REG_GPIO_PXSELS(p) = (1 << o); \
3075 REG_GPIO_PXDIRC(p) = (1 << o); \ 3075 REG_GPIO_PXDIRC(p) = (1 << o); \
3076 REG_GPIO_PXFLGC(p) = (1 << o); \ 3076 REG_GPIO_PXFLGC(p) = (1 << o); \
3077 REG_GPIO_PXIMC(p) = (1 << o); \ 3077 REG_GPIO_PXIMC(p) = (1 << o); \
3078} while (0) 3078} while (0)
3079 3079
3080#define __gpio_as_irq_rise_edge(n) \ 3080#define __gpio_as_irq_rise_edge(n) \
3081do { \ 3081do { \
3082 unsigned int p, o; \ 3082 unsigned int p, o; \
3083 p = (n) / 32; \ 3083 p = (n) / 32; \
3084 o = (n) % 32; \ 3084 o = (n) % 32; \
3085 REG_GPIO_PXIMS(p) = (1 << o); \ 3085 REG_GPIO_PXIMS(p) = (1 << o); \
3086 REG_GPIO_PXTRGS(p) = (1 << o); \ 3086 REG_GPIO_PXTRGS(p) = (1 << o); \
3087 REG_GPIO_PXFUNC(p) = (1 << o); \ 3087 REG_GPIO_PXFUNC(p) = (1 << o); \
3088 REG_GPIO_PXSELS(p) = (1 << o); \ 3088 REG_GPIO_PXSELS(p) = (1 << o); \
3089 REG_GPIO_PXDIRS(p) = (1 << o); \ 3089 REG_GPIO_PXDIRS(p) = (1 << o); \
3090 REG_GPIO_PXFLGC(p) = (1 << o); \ 3090 REG_GPIO_PXFLGC(p) = (1 << o); \
3091 REG_GPIO_PXIMC(p) = (1 << o); \ 3091 REG_GPIO_PXIMC(p) = (1 << o); \
3092} while (0) 3092} while (0)
3093 3093
3094#define __gpio_as_irq_fall_edge(n) \ 3094#define __gpio_as_irq_fall_edge(n) \
3095do { \ 3095do { \
3096 unsigned int p, o; \ 3096 unsigned int p, o; \
3097 p = (n) / 32; \ 3097 p = (n) / 32; \
3098 o = (n) % 32; \ 3098 o = (n) % 32; \
3099 REG_GPIO_PXIMS(p) = (1 << o); \ 3099 REG_GPIO_PXIMS(p) = (1 << o); \
3100 REG_GPIO_PXTRGS(p) = (1 << o); \ 3100 REG_GPIO_PXTRGS(p) = (1 << o); \
3101 REG_GPIO_PXFUNC(p) = (1 << o); \ 3101 REG_GPIO_PXFUNC(p) = (1 << o); \
3102 REG_GPIO_PXSELS(p) = (1 << o); \ 3102 REG_GPIO_PXSELS(p) = (1 << o); \
3103 REG_GPIO_PXDIRC(p) = (1 << o); \ 3103 REG_GPIO_PXDIRC(p) = (1 << o); \
3104 REG_GPIO_PXFLGC(p) = (1 << o); \ 3104 REG_GPIO_PXFLGC(p) = (1 << o); \
3105 REG_GPIO_PXIMC(p) = (1 << o); \ 3105 REG_GPIO_PXIMC(p) = (1 << o); \
3106} while (0) 3106} while (0)
3107 3107
3108#define __gpio_mask_irq(n) \ 3108#define __gpio_mask_irq(n) \
3109do { \ 3109do { \
3110 unsigned int p, o; \ 3110 unsigned int p, o; \
3111 p = (n) / 32; \ 3111 p = (n) / 32; \
3112 o = (n) % 32; \ 3112 o = (n) % 32; \
3113 REG_GPIO_PXIMS(p) = (1 << o); \ 3113 REG_GPIO_PXIMS(p) = (1 << o); \
3114} while (0) 3114} while (0)
3115 3115
3116#define __gpio_unmask_irq(n) \ 3116#define __gpio_unmask_irq(n) \
3117do { \ 3117do { \
3118 unsigned int p, o; \ 3118 unsigned int p, o; \
3119 p = (n) / 32; \ 3119 p = (n) / 32; \
3120 o = (n) % 32; \ 3120 o = (n) % 32; \
3121 REG_GPIO_PXIMC(p) = (1 << o); \ 3121 REG_GPIO_PXIMC(p) = (1 << o); \
3122} while (0) 3122} while (0)
3123 3123
3124#define __gpio_ack_irq(n) \ 3124#define __gpio_ack_irq(n) \
3125do { \ 3125do { \
3126 unsigned int p, o; \ 3126 unsigned int p, o; \
3127 p = (n) / 32; \ 3127 p = (n) / 32; \
3128 o = (n) % 32; \ 3128 o = (n) % 32; \
3129 REG_GPIO_PXFLGC(p) = (1 << o); \ 3129 REG_GPIO_PXFLGC(p) = (1 << o); \
3130} while (0) 3130} while (0)
3131 3131
3132#define __gpio_get_irq() \ 3132#define __gpio_get_irq() \
3133({ \ 3133({ \
3134 unsigned int p, i, tmp, v = 0; \ 3134 unsigned int p, i, tmp, v = 0; \
3135 for (p = 3; p >= 0; p--) { \ 3135 for (p = 3; p >= 0; p--) { \
3136 tmp = REG_GPIO_PXFLG(p); \ 3136 tmp = REG_GPIO_PXFLG(p); \
3137 for (i = 0; i < 32; i++) \ 3137 for (i = 0; i < 32; i++) \
3138 if (tmp & (1 << i)) \ 3138 if (tmp & (1 << i)) \
3139 v = (32*p + i); \ 3139 v = (32*p + i); \
3140 } \ 3140 } \
3141 v; \ 3141 v; \
3142}) 3142})
3143 3143
3144#define __gpio_group_irq(n) \ 3144#define __gpio_group_irq(n) \
3145({ \ 3145({ \
3146 register int tmp, i; \ 3146 register int tmp, i; \
3147 tmp = REG_GPIO_PXFLG((n)); \ 3147 tmp = REG_GPIO_PXFLG((n)); \
3148 for (i=31;i>=0;i--) \ 3148 for (i=31;i>=0;i--) \
3149 if (tmp & (1 << i)) \ 3149 if (tmp & (1 << i)) \
3150 break; \ 3150 break; \
3151 i; \ 3151 i; \
3152}) 3152})
3153 3153
3154#define __gpio_enable_pull(n) \ 3154#define __gpio_enable_pull(n) \
3155do { \ 3155do { \
3156 unsigned int p, o; \ 3156 unsigned int p, o; \
3157 p = (n) / 32; \ 3157 p = (n) / 32; \
3158 o = (n) % 32; \ 3158 o = (n) % 32; \
3159 REG_GPIO_PXPEC(p) = (1 << o); \ 3159 REG_GPIO_PXPEC(p) = (1 << o); \
3160} while (0) 3160} while (0)
3161 3161
3162#define __gpio_disable_pull(n) \ 3162#define __gpio_disable_pull(n) \
3163do { \ 3163do { \
3164 unsigned int p, o; \ 3164 unsigned int p, o; \
3165 p = (n) / 32; \ 3165 p = (n) / 32; \
3166 o = (n) % 32; \ 3166 o = (n) % 32; \
3167 REG_GPIO_PXPES(p) = (1 << o); \ 3167 REG_GPIO_PXPES(p) = (1 << o); \
3168} while (0) 3168} while (0)
3169 3169
3170 3170
3171/*************************************************************************** 3171/***************************************************************************
3172 * CPM 3172 * CPM
3173 ***************************************************************************/ 3173 ***************************************************************************/
3174#define __cpm_get_pllm() \ 3174#define __cpm_get_pllm() \
3175 ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT) 3175 ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT)
3176#define __cpm_get_plln() \ 3176#define __cpm_get_plln() \
3177 ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT) 3177 ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT)
3178#define __cpm_get_pllod() \ 3178#define __cpm_get_pllod() \
3179 ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT) 3179 ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT)
3180 3180
3181#define __cpm_get_cdiv() \ 3181#define __cpm_get_cdiv() \
3182 ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT) 3182 ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT)
3183#define __cpm_get_hdiv() \ 3183#define __cpm_get_hdiv() \
3184 ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT) 3184 ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT)
3185#define __cpm_get_pdiv() \ 3185#define __cpm_get_pdiv() \
3186 ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT) 3186 ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT)
3187#define __cpm_get_mdiv() \ 3187#define __cpm_get_mdiv() \
3188 ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT) 3188 ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT)
3189#define __cpm_get_ldiv() \ 3189#define __cpm_get_ldiv() \
3190 ((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT) 3190 ((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT)
3191#define __cpm_get_udiv() \ 3191#define __cpm_get_udiv() \
3192 ((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT) 3192 ((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT)
3193#define __cpm_get_i2sdiv() \ 3193#define __cpm_get_i2sdiv() \
3194 ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT) 3194 ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT)
3195#define __cpm_get_pixdiv() \ 3195#define __cpm_get_pixdiv() \
3196 ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT) 3196 ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT)
3197#define __cpm_get_mscdiv() \ 3197#define __cpm_get_mscdiv() \
3198 ((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT) 3198 ((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT)
3199 3199
3200#define __cpm_set_cdiv(v) \ 3200#define __cpm_set_cdiv(v) \
3201 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT))) 3201 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT)))
3202#define __cpm_set_hdiv(v) \ 3202#define __cpm_set_hdiv(v) \
3203 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT))) 3203 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT)))
3204#define __cpm_set_pdiv(v) \ 3204#define __cpm_set_pdiv(v) \
3205 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT))) 3205 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT)))
3206#define __cpm_set_mdiv(v) \ 3206#define __cpm_set_mdiv(v) \
3207 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT))) 3207 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT)))
3208#define __cpm_set_ldiv(v) \ 3208#define __cpm_set_ldiv(v) \
3209 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT))) 3209 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT)))
3210#define __cpm_set_udiv(v) \ 3210#define __cpm_set_udiv(v) \
3211 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT))) 3211 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT)))
3212#define __cpm_set_i2sdiv(v) \ 3212#define __cpm_set_i2sdiv(v) \
3213 (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT))) 3213 (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT)))
3214#define __cpm_set_pixdiv(v) \ 3214#define __cpm_set_pixdiv(v) \
3215 (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT))) 3215 (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT)))
3216#define __cpm_set_mscdiv(v) \ 3216#define __cpm_set_mscdiv(v) \
3217 (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT))) 3217 (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT)))
3218 3218
3219#define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS) 3219#define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS)
3220#define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS) 3220#define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS)
3221#define __cpm_enable_cko() (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN) 3221#define __cpm_enable_cko() (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN)
3222#define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS) 3222#define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS)
3223#define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS) 3223#define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS)
3224#define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE) 3224#define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE)
3225#define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS) 3225#define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS)
3226#define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS) 3226#define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS)
3227 3227
3228#define __cpm_pll_is_on() (REG_CPM_CPPCR & CPM_CPPCR_PLLS) 3228#define __cpm_pll_is_on() (REG_CPM_CPPCR & CPM_CPPCR_PLLS)
3229#define __cpm_pll_bypass() (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP) 3229#define __cpm_pll_bypass() (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP)
3230#define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN) 3230#define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN)
3231 3231
3232#define __cpm_get_cclk_doze_duty() \ 3232#define __cpm_get_cclk_doze_duty() \
3233 ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT) 3233 ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT)
3234#define __cpm_set_cclk_doze_duty(v) \ 3234#define __cpm_set_cclk_doze_duty(v) \
3235 (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT))) 3235 (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT)))
3236 3236
3237#define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON) 3237#define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON)
3238#define __cpm_idle_mode() \ 3238#define __cpm_idle_mode() \
3239 (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE) 3239 (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE)
3240#define __cpm_sleep_mode() \ 3240#define __cpm_sleep_mode() \
3241 (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP) 3241 (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP)
3242 3242
3243#define __cpm_stop_all() (REG_CPM_CLKGR = 0x7fff) 3243#define __cpm_stop_all() (REG_CPM_CLKGR = 0x7fff)
3244#define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1) 3244#define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1)
3245#define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC) 3245#define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC)
3246#define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU) 3246#define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU)
3247#define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC) 3247#define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC)
3248#define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC) 3248#define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC)
3249#define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD) 3249#define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD)
3250#define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM) 3250#define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM)
3251#define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC) 3251#define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC)
3252#define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC) 3252#define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC)
3253#define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1) 3253#define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1)
3254#define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2) 3254#define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2)
3255#define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI) 3255#define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI)
3256#define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C) 3256#define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C)
3257#define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC) 3257#define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC)
3258#define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU) 3258#define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU)
3259#define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0) 3259#define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0)
3260 3260
3261#define __cpm_start_all() (REG_CPM_CLKGR = 0x0) 3261#define __cpm_start_all() (REG_CPM_CLKGR = 0x0)
3262#define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1) 3262#define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1)
3263#define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC) 3263#define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC)
3264#define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU) 3264#define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU)
3265#define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC) 3265#define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC)
3266#define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC) 3266#define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC)
3267#define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD) 3267#define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD)
3268#define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM) 3268#define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM)
3269#define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC) 3269#define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC)
3270#define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC) 3270#define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC)
3271#define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1) 3271#define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1)
3272#define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2) 3272#define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2)
3273#define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI) 3273#define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI)
3274#define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C) 3274#define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C)
3275#define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC) 3275#define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC)
3276#define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU) 3276#define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU)
3277#define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0) 3277#define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0)
3278 3278
3279#define __cpm_get_o1st() \ 3279#define __cpm_get_o1st() \
3280 ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT) 3280 ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT)
3281#define __cpm_set_o1st(v) \ 3281#define __cpm_set_o1st(v) \
3282 (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT))) 3282 (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT)))
3283#define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_SUSPEND) 3283#define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_SUSPEND)
3284#define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE) 3284#define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE)
3285 3285
3286 3286
3287#ifdef CFG_EXTAL 3287#ifdef CFG_EXTAL
3288#define JZ_EXTAL CFG_EXTAL 3288#define JZ_EXTAL CFG_EXTAL
3289#else 3289#else
3290#define JZ_EXTAL 3686400 3290#define JZ_EXTAL 3686400
3291#endif 3291#endif
3292#define JZ_EXTAL2 32768 /* RTC clock */ 3292#define JZ_EXTAL2 32768 /* RTC clock */
3293 3293
3294/* PLL output frequency */ 3294/* PLL output frequency */
3295static __inline__ unsigned int __cpm_get_pllout(void) 3295static __inline__ unsigned int __cpm_get_pllout(void)
3296{ 3296{
3297 unsigned long m, n, no, pllout; 3297 unsigned long m, n, no, pllout;
3298 unsigned long cppcr = REG_CPM_CPPCR; 3298 unsigned long cppcr = REG_CPM_CPPCR;
3299 unsigned long od[4] = {1, 2, 2, 4}; 3299 unsigned long od[4] = {1, 2, 2, 4};
3300 if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) { 3300 if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) {
3301 m = __cpm_get_pllm() + 2; 3301 m = __cpm_get_pllm() + 2;
3302 n = __cpm_get_plln() + 2; 3302 n = __cpm_get_plln() + 2;
3303 no = od[__cpm_get_pllod()]; 3303 no = od[__cpm_get_pllod()];
3304 pllout = ((JZ_EXTAL) / (n * no)) * m; 3304 pllout = ((JZ_EXTAL) / (n * no)) * m;
3305 } else 3305 } else
3306 pllout = JZ_EXTAL; 3306 pllout = JZ_EXTAL;
3307 return pllout; 3307 return pllout;
3308} 3308}
3309 3309
3310/* PLL output frequency for MSC/I2S/LCD/USB */ 3310/* PLL output frequency for MSC/I2S/LCD/USB */
3311static __inline__ unsigned int __cpm_get_pllout2(void) 3311static __inline__ unsigned int __cpm_get_pllout2(void)
3312{ 3312{
3313 if (REG_CPM_CPCCR & CPM_CPCCR_PCS) 3313 if (REG_CPM_CPCCR & CPM_CPCCR_PCS)
3314 return __cpm_get_pllout(); 3314 return __cpm_get_pllout();
3315 else 3315 else
3316 return __cpm_get_pllout()/2; 3316 return __cpm_get_pllout()/2;
3317} 3317}
3318 3318
3319/* CPU core clock */ 3319/* CPU core clock */
3320static __inline__ unsigned int __cpm_get_cclk(void) 3320static __inline__ unsigned int __cpm_get_cclk(void)
3321{ 3321{
3322 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 3322 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3323 3323
3324 return __cpm_get_pllout() / div[__cpm_get_cdiv()]; 3324 return __cpm_get_pllout() / div[__cpm_get_cdiv()];
3325} 3325}
3326 3326
3327/* AHB system bus clock */ 3327/* AHB system bus clock */
3328static __inline__ unsigned int __cpm_get_hclk(void) 3328static __inline__ unsigned int __cpm_get_hclk(void)
3329{ 3329{
3330 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 3330 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3331 3331
3332 return __cpm_get_pllout() / div[__cpm_get_hdiv()]; 3332 return __cpm_get_pllout() / div[__cpm_get_hdiv()];
3333} 3333}
3334 3334
3335/* Memory bus clock */ 3335/* Memory bus clock */
3336static __inline__ unsigned int __cpm_get_mclk(void) 3336static __inline__ unsigned int __cpm_get_mclk(void)
3337{ 3337{
3338 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 3338 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3339 3339
3340 return __cpm_get_pllout() / div[__cpm_get_mdiv()]; 3340 return __cpm_get_pllout() / div[__cpm_get_mdiv()];
3341} 3341}
3342 3342
3343/* APB peripheral bus clock */ 3343/* APB peripheral bus clock */
3344static __inline__ unsigned int __cpm_get_pclk(void) 3344static __inline__ unsigned int __cpm_get_pclk(void)
3345{ 3345{
3346 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 3346 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3347 3347
3348 return __cpm_get_pllout() / div[__cpm_get_pdiv()]; 3348 return __cpm_get_pllout() / div[__cpm_get_pdiv()];
3349} 3349}
3350 3350
3351/* LCDC module clock */ 3351/* LCDC module clock */
3352static __inline__ unsigned int __cpm_get_lcdclk(void) 3352static __inline__ unsigned int __cpm_get_lcdclk(void)
3353{ 3353{
3354 return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1); 3354 return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1);
3355} 3355}
3356 3356
3357/* LCD pixel clock */ 3357/* LCD pixel clock */
3358static __inline__ unsigned int __cpm_get_pixclk(void) 3358static __inline__ unsigned int __cpm_get_pixclk(void)
3359{ 3359{
3360 return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1); 3360 return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1);
3361} 3361}
3362 3362
3363/* I2S clock */ 3363/* I2S clock */
3364static __inline__ unsigned int __cpm_get_i2sclk(void) 3364static __inline__ unsigned int __cpm_get_i2sclk(void)
3365{ 3365{
3366 if (REG_CPM_CPCCR & CPM_CPCCR_I2CS) { 3366 if (REG_CPM_CPCCR & CPM_CPCCR_I2CS) {
3367 return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1); 3367 return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1);
3368 } 3368 }
3369 else { 3369 else {
3370 return JZ_EXTAL; 3370 return JZ_EXTAL;
3371 } 3371 }
3372} 3372}
3373 3373
3374/* USB clock */ 3374/* USB clock */
3375static __inline__ unsigned int __cpm_get_usbclk(void) 3375static __inline__ unsigned int __cpm_get_usbclk(void)
3376{ 3376{
3377 if (REG_CPM_CPCCR & CPM_CPCCR_UCS) { 3377 if (REG_CPM_CPCCR & CPM_CPCCR_UCS) {
3378 return __cpm_get_pllout2() / (__cpm_get_udiv() + 1); 3378 return __cpm_get_pllout2() / (__cpm_get_udiv() + 1);
3379 } 3379 }
3380 else { 3380 else {
3381 return JZ_EXTAL; 3381 return JZ_EXTAL;
3382 } 3382 }
3383} 3383}
3384 3384
3385/* MSC clock */ 3385/* MSC clock */
3386static __inline__ unsigned int __cpm_get_mscclk(void) 3386static __inline__ unsigned int __cpm_get_mscclk(void)
3387{ 3387{
3388 return __cpm_get_pllout2() / (__cpm_get_mscdiv() + 1); 3388 return __cpm_get_pllout2() / (__cpm_get_mscdiv() + 1);
3389} 3389}
3390 3390
3391/* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */ 3391/* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */
3392static __inline__ unsigned int __cpm_get_extalclk(void) 3392static __inline__ unsigned int __cpm_get_extalclk(void)
3393{ 3393{
3394 return JZ_EXTAL; 3394 return JZ_EXTAL;
3395} 3395}
3396 3396
3397/* RTC clock for CPM,INTC,RTC,TCU,WDT */ 3397/* RTC clock for CPM,INTC,RTC,TCU,WDT */
3398static __inline__ unsigned int __cpm_get_rtcclk(void) 3398static __inline__ unsigned int __cpm_get_rtcclk(void)
3399{ 3399{
3400 return JZ_EXTAL2; 3400 return JZ_EXTAL2;
3401} 3401}
3402 3402
3403/* 3403/*
3404 * Output 24MHz for SD and 16MHz for MMC. 3404 * Output 24MHz for SD and 16MHz for MMC.
3405 */ 3405 */
3406static inline void __cpm_select_msc_clk(int sd) 3406static inline void __cpm_select_msc_clk(int sd)
3407{ 3407{
3408 unsigned int pllout2 = __cpm_get_pllout2(); 3408 unsigned int pllout2 = __cpm_get_pllout2();
3409 unsigned int div = 0; 3409 unsigned int div = 0;
3410 3410
3411 if (sd) { 3411 if (sd) {
3412 div = pllout2 / 24000000; 3412 div = pllout2 / 24000000;
3413 } 3413 }
3414 else { 3414 else {
3415 div = pllout2 / 16000000; 3415 div = pllout2 / 16000000;
3416 } 3416 }
3417 3417
3418 REG_CPM_MSCCDR = div - 1; 3418 REG_CPM_MSCCDR = div - 1;
3419} 3419}
3420 3420
3421/* 3421/*
3422 * Output 48MHz for SD and 16MHz for MMC. 3422 * Output 48MHz for SD and 16MHz for MMC.
3423 */ 3423 */
3424static inline void __cpm_select_msc_hs_clk(int sd) 3424static inline void __cpm_select_msc_hs_clk(int sd)
3425{ 3425{
3426 unsigned int pllout2 = __cpm_get_pllout2(); 3426 unsigned int pllout2 = __cpm_get_pllout2();
3427 unsigned int div = 0; 3427 unsigned int div = 0;
3428 3428
3429 if (sd) { 3429 if (sd) {
3430 div = pllout2 / 48000000; 3430 div = pllout2 / 48000000;
3431 } 3431 }
3432 else { 3432 else {
3433 div = pllout2 / 16000000; 3433 div = pllout2 / 16000000;
3434 } 3434 }
3435 REG_CPM_MSCCDR = div - 1; 3435 REG_CPM_MSCCDR = div - 1;
3436} 3436}
3437 3437
3438/*************************************************************************** 3438/***************************************************************************
3439 * TCU 3439 * TCU
3440 ***************************************************************************/ 3440 ***************************************************************************/
3441// where 'n' is the TCU channel 3441// where 'n' is the TCU channel
3442#define __tcu_select_extalclk(n) \ 3442#define __tcu_select_extalclk(n) \
3443 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN) 3443 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN)
3444#define __tcu_select_rtcclk(n) \ 3444#define __tcu_select_rtcclk(n) \
3445 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN) 3445 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN)
3446#define __tcu_select_pclk(n) \ 3446#define __tcu_select_pclk(n) \
3447 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN) 3447 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN)
3448 3448
3449#define __tcu_select_clk_div1(n) \ 3449#define __tcu_select_clk_div1(n) \
3450 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1) 3450 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1)
3451#define __tcu_select_clk_div4(n) \ 3451#define __tcu_select_clk_div4(n) \
3452 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4) 3452 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4)
3453#define __tcu_select_clk_div16(n) \ 3453#define __tcu_select_clk_div16(n) \
3454 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16) 3454 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16)
3455#define __tcu_select_clk_div64(n) \ 3455#define __tcu_select_clk_div64(n) \
3456 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64) 3456 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64)
3457#define __tcu_select_clk_div256(n) \ 3457#define __tcu_select_clk_div256(n) \
3458 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256) 3458 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256)
3459#define __tcu_select_clk_div1024(n) \ 3459#define __tcu_select_clk_div1024(n) \
3460 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024) 3460 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024)
3461 3461
3462#define __tcu_enable_pwm_output(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN ) 3462#define __tcu_enable_pwm_output(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN )
3463#define __tcu_disable_pwm_output(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN ) 3463#define __tcu_disable_pwm_output(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN )
3464 3464
3465#define __tcu_init_pwm_output_high(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH ) 3465#define __tcu_init_pwm_output_high(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH )
3466#define __tcu_init_pwm_output_low(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH ) 3466#define __tcu_init_pwm_output_low(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH )
3467 3467
3468#define __tcu_set_pwm_output_shutdown_graceful(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD ) 3468#define __tcu_set_pwm_output_shutdown_graceful(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD )
3469#define __tcu_set_pwm_output_shutdown_abrupt(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD ) 3469#define __tcu_set_pwm_output_shutdown_abrupt(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD )
3470 3470
3471#define __tcu_start_counter(n) ( REG_TCU_TESR |= (1 << (n)) ) 3471#define __tcu_start_counter(n) ( REG_TCU_TESR |= (1 << (n)) )
3472#define __tcu_stop_counter(n) ( REG_TCU_TECR |= (1 << (n)) ) 3472#define __tcu_stop_counter(n) ( REG_TCU_TECR |= (1 << (n)) )
3473 3473
3474#define __tcu_half_match_flag(n) ( REG_TCU_TFR & (1 << ((n) + 16)) ) 3474#define __tcu_half_match_flag(n) ( REG_TCU_TFR & (1 << ((n) + 16)) )
3475#define __tcu_full_match_flag(n) ( REG_TCU_TFR & (1 << (n)) ) 3475#define __tcu_full_match_flag(n) ( REG_TCU_TFR & (1 << (n)) )
3476#define __tcu_set_half_match_flag(n) ( REG_TCU_TFSR = (1 << ((n) + 16)) ) 3476#define __tcu_set_half_match_flag(n) ( REG_TCU_TFSR = (1 << ((n) + 16)) )
3477#define __tcu_set_full_match_flag(n) ( REG_TCU_TFSR = (1 << (n)) ) 3477#define __tcu_set_full_match_flag(n) ( REG_TCU_TFSR = (1 << (n)) )
3478#define __tcu_clear_half_match_flag(n) ( REG_TCU_TFCR = (1 << ((n) + 16)) ) 3478#define __tcu_clear_half_match_flag(n) ( REG_TCU_TFCR = (1 << ((n) + 16)) )
3479#define __tcu_clear_full_match_flag(n) ( REG_TCU_TFCR = (1 << (n)) ) 3479#define __tcu_clear_full_match_flag(n) ( REG_TCU_TFCR = (1 << (n)) )
3480#define __tcu_mask_half_match_irq(n) ( REG_TCU_TMSR = (1 << ((n) + 16)) ) 3480#define __tcu_mask_half_match_irq(n) ( REG_TCU_TMSR = (1 << ((n) + 16)) )
3481#define __tcu_mask_full_match_irq(n) ( REG_TCU_TMSR = (1 << (n)) ) 3481#define __tcu_mask_full_match_irq(n) ( REG_TCU_TMSR = (1 << (n)) )
3482#define __tcu_unmask_half_match_irq(n) ( REG_TCU_TMCR = (1 << ((n) + 16)) ) 3482#define __tcu_unmask_half_match_irq(n) ( REG_TCU_TMCR = (1 << ((n) + 16)) )
3483#define __tcu_unmask_full_match_irq(n) ( REG_TCU_TMCR = (1 << (n)) ) 3483#define __tcu_unmask_full_match_irq(n) ( REG_TCU_TMCR = (1 << (n)) )
3484 3484
3485#define __tcu_wdt_clock_stopped() ( REG_TCU_TSR & TCU_TSSR_WDTSC ) 3485#define __tcu_wdt_clock_stopped() ( REG_TCU_TSR & TCU_TSSR_WDTSC )
3486#define __tcu_timer_clock_stopped(n) ( REG_TCU_TSR & (1 << (n)) ) 3486#define __tcu_timer_clock_stopped(n) ( REG_TCU_TSR & (1 << (n)) )
3487 3487
3488#define __tcu_start_wdt_clock() ( REG_TCU_TSCR = TCU_TSSR_WDTSC ) 3488#define __tcu_start_wdt_clock() ( REG_TCU_TSCR = TCU_TSSR_WDTSC )
3489#define __tcu_start_timer_clock(n) ( REG_TCU_TSCR = (1 << (n)) ) 3489#define __tcu_start_timer_clock(n) ( REG_TCU_TSCR = (1 << (n)) )
3490 3490
3491#define __tcu_stop_wdt_clock() ( REG_TCU_TSSR = TCU_TSSR_WDTSC ) 3491#define __tcu_stop_wdt_clock() ( REG_TCU_TSSR = TCU_TSSR_WDTSC )
3492#define __tcu_stop_timer_clock(n) ( REG_TCU_TSSR = (1 << (n)) ) 3492#define __tcu_stop_timer_clock(n) ( REG_TCU_TSSR = (1 << (n)) )
3493 3493
3494#define __tcu_get_count(n) ( REG_TCU_TCNT((n)) ) 3494#define __tcu_get_count(n) ( REG_TCU_TCNT((n)) )
3495#define __tcu_set_count(n,v) ( REG_TCU_TCNT((n)) = (v) ) 3495#define __tcu_set_count(n,v) ( REG_TCU_TCNT((n)) = (v) )
3496#define __tcu_set_full_data(n,v) ( REG_TCU_TDFR((n)) = (v) ) 3496#define __tcu_set_full_data(n,v) ( REG_TCU_TDFR((n)) = (v) )
3497#define __tcu_set_half_data(n,v) ( REG_TCU_TDHR((n)) = (v) ) 3497#define __tcu_set_half_data(n,v) ( REG_TCU_TDHR((n)) = (v) )
3498 3498
3499 3499
3500/*************************************************************************** 3500/***************************************************************************
3501 * WDT 3501 * WDT
3502 ***************************************************************************/ 3502 ***************************************************************************/
3503#define __wdt_start() ( REG_WDT_TCER |= WDT_TCER_TCEN ) 3503#define __wdt_start() ( REG_WDT_TCER |= WDT_TCER_TCEN )
3504#define __wdt_stop() ( REG_WDT_TCER &= ~WDT_TCER_TCEN ) 3504#define __wdt_stop() ( REG_WDT_TCER &= ~WDT_TCER_TCEN )
3505#define __wdt_set_count(v) ( REG_WDT_TCNT = (v) ) 3505#define __wdt_set_count(v) ( REG_WDT_TCNT = (v) )
3506#define __wdt_set_data(v) ( REG_WDT_TDR = (v) ) 3506#define __wdt_set_data(v) ( REG_WDT_TDR = (v) )
3507 3507
3508#define __wdt_select_extalclk() \ 3508#define __wdt_select_extalclk() \
3509 (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN) 3509 (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN)
3510#define __wdt_select_rtcclk() \ 3510#define __wdt_select_rtcclk() \
3511 (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN) 3511 (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN)
3512#define __wdt_select_pclk() \ 3512#define __wdt_select_pclk() \
3513 (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN) 3513 (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN)
3514 3514
3515#define __wdt_select_clk_div1() \ 3515#define __wdt_select_clk_div1() \
3516 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1) 3516 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1)
3517#define __wdt_select_clk_div4() \ 3517#define __wdt_select_clk_div4() \
3518 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4) 3518 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4)
3519#define __wdt_select_clk_div16() \ 3519#define __wdt_select_clk_div16() \
3520 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16) 3520 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16)
3521#define __wdt_select_clk_div64() \ 3521#define __wdt_select_clk_div64() \
3522 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64) 3522 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64)
3523#define __wdt_select_clk_div256() \ 3523#define __wdt_select_clk_div256() \
3524 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256) 3524 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256)
3525#define __wdt_select_clk_div1024() \ 3525#define __wdt_select_clk_div1024() \
3526 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024) 3526 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024)
3527 3527
3528 3528
3529/*************************************************************************** 3529/***************************************************************************
3530 * UART 3530 * UART
3531 ***************************************************************************/ 3531 ***************************************************************************/
3532 3532
3533#define __uart_enable() ( REG8(UART0_FCR) |= UARTFCR_UUE | UARTFCR_FE ) 3533#define __uart_enable() ( REG8(UART0_FCR) |= UARTFCR_UUE | UARTFCR_FE )
3534#define __uart_disable() ( REG8(UART0_FCR) = ~UARTFCR_UUE ) 3534#define __uart_disable() ( REG8(UART0_FCR) = ~UARTFCR_UUE )
3535 3535
3536#define __uart_enable_transmit_irq() ( REG8(UART0_IER) |= UARTIER_TIE ) 3536#define __uart_enable_transmit_irq() ( REG8(UART0_IER) |= UARTIER_TIE )
3537#define __uart_disable_transmit_irq() ( REG8(UART0_IER) &= ~UARTIER_TIE ) 3537#define __uart_disable_transmit_irq() ( REG8(UART0_IER) &= ~UARTIER_TIE )
3538 3538
3539#define __uart_enable_receive_irq() \ 3539#define __uart_enable_receive_irq() \
3540 ( REG8(UART0_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE ) 3540 ( REG8(UART0_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE )
3541#define __uart_disable_receive_irq() \ 3541#define __uart_disable_receive_irq() \
3542 ( REG8(UART0_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) ) 3542 ( REG8(UART0_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) )
3543 3543
3544#define __uart_enable_loopback() ( REG8(UART0_MCR) |= UARTMCR_LOOP ) 3544#define __uart_enable_loopback() ( REG8(UART0_MCR) |= UARTMCR_LOOP )
3545#define __uart_disable_loopback() ( REG8(UART0_MCR) &= ~UARTMCR_LOOP ) 3545#define __uart_disable_loopback() ( REG8(UART0_MCR) &= ~UARTMCR_LOOP )
3546 3546
3547#define __uart_set_8n1() ( REG8(UART0_LCR) = UARTLCR_WLEN_8 ) 3547#define __uart_set_8n1() ( REG8(UART0_LCR) = UARTLCR_WLEN_8 )
3548 3548
3549#define __uart_set_baud(devclk, baud) \ 3549#define __uart_set_baud(devclk, baud) \
3550 do { \ 3550 do { \
3551 REG8(UART0_LCR) |= UARTLCR_DLAB; \ 3551 REG8(UART0_LCR) |= UARTLCR_DLAB; \
3552 REG8(UART0_DLLR) = (devclk / 16 / baud) & 0xff; \ 3552 REG8(UART0_DLLR) = (devclk / 16 / baud) & 0xff; \
3553 REG8(UART0_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \ 3553 REG8(UART0_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \
3554 REG8(UART0_LCR) &= ~UARTLCR_DLAB; \ 3554 REG8(UART0_LCR) &= ~UARTLCR_DLAB; \
3555 } while (0) 3555 } while (0)
3556 3556
3557#define __uart_parity_error() ( (REG8(UART0_LSR) & UARTLSR_PER) != 0 ) 3557#define __uart_parity_error() ( (REG8(UART0_LSR) & UARTLSR_PER) != 0 )
3558#define __uart_clear_errors() \ 3558#define __uart_clear_errors() \
3559 ( REG8(UART0_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) ) 3559 ( REG8(UART0_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) )
3560 3560
3561#define __uart_transmit_fifo_empty() ( (REG8(UART0_LSR) & UARTLSR_TDRQ) != 0 ) 3561#define __uart_transmit_fifo_empty() ( (REG8(UART0_LSR) & UARTLSR_TDRQ) != 0 )
3562#define __uart_transmit_end() ( (REG8(UART0_LSR) & UARTLSR_TEMT) != 0 ) 3562#define __uart_transmit_end() ( (REG8(UART0_LSR) & UARTLSR_TEMT) != 0 )
3563#define __uart_transmit_char(ch) ( REG8(UART0_TDR) = (ch) ) 3563#define __uart_transmit_char(ch) ( REG8(UART0_TDR) = (ch) )
3564#define __uart_receive_fifo_full() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 ) 3564#define __uart_receive_fifo_full() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 )
3565#define __uart_receive_ready() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 ) 3565#define __uart_receive_ready() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 )
3566#define __uart_receive_char() REG8(UART0_RDR) 3566#define __uart_receive_char() REG8(UART0_RDR)
3567#define __uart_disable_irda() ( REG8(UART0_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) ) 3567#define __uart_disable_irda() ( REG8(UART0_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) )
3568#define __uart_enable_irda() \ 3568#define __uart_enable_irda() \
3569 /* Tx high pulse as 0, Rx low pulse as 0 */ \ 3569 /* Tx high pulse as 0, Rx low pulse as 0 */ \
3570 ( REG8(UART0_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS ) 3570 ( REG8(UART0_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS )
3571 3571
3572 3572
3573/*************************************************************************** 3573/***************************************************************************
3574 * DMAC 3574 * DMAC
3575 ***************************************************************************/ 3575 ***************************************************************************/
3576 3576
3577/* n is the DMA channel (0 - 5) */ 3577/* n is the DMA channel (0 - 5) */
3578 3578
3579#define __dmac_enable_module() \ 3579#define __dmac_enable_module() \
3580 ( REG_DMAC_DMACR |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_RR ) 3580 ( REG_DMAC_DMACR |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_RR )
3581#define __dmac_disable_module() \ 3581#define __dmac_disable_module() \
3582 ( REG_DMAC_DMACR &= ~DMAC_DMACR_DMAE ) 3582 ( REG_DMAC_DMACR &= ~DMAC_DMACR_DMAE )
3583 3583
3584/* p=0,1,2,3 */ 3584/* p=0,1,2,3 */
3585#define __dmac_set_priority(p) \ 3585#define __dmac_set_priority(p) \
3586do { \ 3586do { \
3587 REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \ 3587 REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \
3588 REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \ 3588 REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \
3589} while (0) 3589} while (0)
3590 3590
3591#define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HLT ) 3591#define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HLT )
3592#define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AR ) 3592#define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AR )
3593 3593
3594#define __dmac_enable_descriptor(n) \ 3594#define __dmac_enable_descriptor(n) \
3595 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES ) 3595 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )
3596#define __dmac_disable_descriptor(n) \ 3596#define __dmac_disable_descriptor(n) \
3597 ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES ) 3597 ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )
3598 3598
3599#define __dmac_enable_channel(n) \ 3599#define __dmac_enable_channel(n) \
3600 ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN ) 3600 ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN )
3601#define __dmac_disable_channel(n) \ 3601#define __dmac_disable_channel(n) \
3602 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN ) 3602 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN )
3603#define __dmac_channel_enabled(n) \ 3603#define __dmac_channel_enabled(n) \
3604 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN ) 3604 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN )
3605 3605
3606#define __dmac_channel_enable_irq(n) \ 3606#define __dmac_channel_enable_irq(n) \
3607 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE ) 3607 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE )
3608#define __dmac_channel_disable_irq(n) \ 3608#define __dmac_channel_disable_irq(n) \
3609 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE ) 3609 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )
3610 3610
3611#define __dmac_channel_transmit_halt_detected(n) \ 3611#define __dmac_channel_transmit_halt_detected(n) \
3612 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT ) 3612 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT )
3613#define __dmac_channel_transmit_end_detected(n) \ 3613#define __dmac_channel_transmit_end_detected(n) \
3614 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT ) 3614 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT )
3615#define __dmac_channel_address_error_detected(n) \ 3615#define __dmac_channel_address_error_detected(n) \
3616 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR ) 3616 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )
3617#define __dmac_channel_count_terminated_detected(n) \ 3617#define __dmac_channel_count_terminated_detected(n) \
3618 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT ) 3618 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT )
3619#define __dmac_channel_descriptor_invalid_detected(n) \ 3619#define __dmac_channel_descriptor_invalid_detected(n) \
3620 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV ) 3620 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV )
3621 3621
3622#define __dmac_channel_clear_transmit_halt(n) \ 3622#define __dmac_channel_clear_transmit_halt(n) \
3623 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT ) 3623 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT )
3624#define __dmac_channel_clear_transmit_end(n) \ 3624#define __dmac_channel_clear_transmit_end(n) \
3625 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT ) 3625 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )
3626#define __dmac_channel_clear_address_error(n) \ 3626#define __dmac_channel_clear_address_error(n) \
3627 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR ) 3627 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR )
3628#define __dmac_channel_clear_count_terminated(n) \ 3628#define __dmac_channel_clear_count_terminated(n) \
3629 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT ) 3629 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )
3630#define __dmac_channel_clear_descriptor_invalid(n) \ 3630#define __dmac_channel_clear_descriptor_invalid(n) \
3631 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV ) 3631 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )
3632 3632
3633#define __dmac_channel_set_single_mode(n) \ 3633#define __dmac_channel_set_single_mode(n) \
3634 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TM ) 3634 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TM )
3635#define __dmac_channel_set_block_mode(n) \ 3635#define __dmac_channel_set_block_mode(n) \
3636 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TM ) 3636 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TM )
3637 3637
3638#define __dmac_channel_set_transfer_unit_32bit(n) \ 3638#define __dmac_channel_set_transfer_unit_32bit(n) \
3639do { \ 3639do { \
3640 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 3640 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3641 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \ 3641 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \
3642} while (0) 3642} while (0)
3643 3643
3644#define __dmac_channel_set_transfer_unit_16bit(n) \ 3644#define __dmac_channel_set_transfer_unit_16bit(n) \
3645do { \ 3645do { \
3646 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 3646 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3647 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \ 3647 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \
3648} while (0) 3648} while (0)
3649 3649
3650#define __dmac_channel_set_transfer_unit_8bit(n) \ 3650#define __dmac_channel_set_transfer_unit_8bit(n) \
3651do { \ 3651do { \
3652 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 3652 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3653 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \ 3653 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \
3654} while (0) 3654} while (0)
3655 3655
3656#define __dmac_channel_set_transfer_unit_16byte(n) \ 3656#define __dmac_channel_set_transfer_unit_16byte(n) \
3657do { \ 3657do { \
3658 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 3658 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3659 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \ 3659 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \
3660} while (0) 3660} while (0)
3661 3661
3662#define __dmac_channel_set_transfer_unit_32byte(n) \ 3662#define __dmac_channel_set_transfer_unit_32byte(n) \
3663do { \ 3663do { \
3664 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 3664 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3665 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \ 3665 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \
3666} while (0) 3666} while (0)
3667 3667
3668/* w=8,16,32 */ 3668/* w=8,16,32 */
3669#define __dmac_channel_set_dest_port_width(n,w) \ 3669#define __dmac_channel_set_dest_port_width(n,w) \
3670do { \ 3670do { \
3671 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \ 3671 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \
3672 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \ 3672 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \
3673} while (0) 3673} while (0)
3674 3674
3675/* w=8,16,32 */ 3675/* w=8,16,32 */
3676#define __dmac_channel_set_src_port_width(n,w) \ 3676#define __dmac_channel_set_src_port_width(n,w) \
3677do { \ 3677do { \
3678 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \ 3678 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \
3679 REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \ 3679 REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \
3680} while (0) 3680} while (0)
3681 3681
3682/* v=0-15 */ 3682/* v=0-15 */
3683#define __dmac_channel_set_rdil(n,v) \ 3683#define __dmac_channel_set_rdil(n,v) \
3684do { \ 3684do { \
3685 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \ 3685 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \
3686 REG_DMAC_DCMD((n)) |= ((v) << DMAC_DCMD_RDIL_BIT); \ 3686 REG_DMAC_DCMD((n)) |= ((v) << DMAC_DCMD_RDIL_BIT); \
3687} while (0) 3687} while (0)
3688 3688
3689#define __dmac_channel_dest_addr_fixed(n) \ 3689#define __dmac_channel_dest_addr_fixed(n) \
3690 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI ) 3690 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI )
3691#define __dmac_channel_dest_addr_increment(n) \ 3691#define __dmac_channel_dest_addr_increment(n) \
3692 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI ) 3692 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI )
3693 3693
3694#define __dmac_channel_src_addr_fixed(n) \ 3694#define __dmac_channel_src_addr_fixed(n) \
3695 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI ) 3695 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI )
3696#define __dmac_channel_src_addr_increment(n) \ 3696#define __dmac_channel_src_addr_increment(n) \
3697 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI ) 3697 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI )
3698 3698
3699#define __dmac_channel_set_doorbell(n) \ 3699#define __dmac_channel_set_doorbell(n) \
3700 ( REG_DMAC_DMADBSR = (1 << (n)) ) 3700 ( REG_DMAC_DMADBSR = (1 << (n)) )
3701 3701
3702#define __dmac_channel_irq_detected(n) ( REG_DMAC_DMAIPR & (1 << (n)) ) 3702#define __dmac_channel_irq_detected(n) ( REG_DMAC_DMAIPR & (1 << (n)) )
3703#define __dmac_channel_ack_irq(n) ( REG_DMAC_DMAIPR &= ~(1 << (n)) ) 3703#define __dmac_channel_ack_irq(n) ( REG_DMAC_DMAIPR &= ~(1 << (n)) )
3704 3704
3705static __inline__ int __dmac_get_irq(void) 3705static __inline__ int __dmac_get_irq(void)
3706{ 3706{
3707 int i; 3707 int i;
3708 for (i = 0; i < MAX_DMA_NUM; i++) 3708 for (i = 0; i < MAX_DMA_NUM; i++)
3709 if (__dmac_channel_irq_detected(i)) 3709 if (__dmac_channel_irq_detected(i))
3710 return i; 3710 return i;
3711 return -1; 3711 return -1;
3712} 3712}
3713 3713
3714 3714
3715/*************************************************************************** 3715/***************************************************************************
3716 * AIC (AC'97 & I2S Controller) 3716 * AIC (AC'97 & I2S Controller)
3717 ***************************************************************************/ 3717 ***************************************************************************/
3718 3718
3719#define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB ) 3719#define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB )
3720#define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB ) 3720#define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB )
3721 3721
3722#define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL ) 3722#define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL )
3723#define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL ) 3723#define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL )
3724 3724
3725#define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD ) 3725#define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD )
3726#define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) ) 3726#define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) )
3727#define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST ) 3727#define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST )
3728 3728
3729#define __aic_reset() \ 3729#define __aic_reset() \
3730do { \ 3730do { \
3731 REG_AIC_FR |= AIC_FR_RST; \ 3731 REG_AIC_FR |= AIC_FR_RST; \
3732} while(0) 3732} while(0)
3733 3733
3734 3734
3735#define __aic_set_transmit_trigger(n) \ 3735#define __aic_set_transmit_trigger(n) \
3736do { \ 3736do { \
3737 REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \ 3737 REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \
3738 REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \ 3738 REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \
3739} while(0) 3739} while(0)
3740 3740
3741#define __aic_set_receive_trigger(n) \ 3741#define __aic_set_receive_trigger(n) \
3742do { \ 3742do { \
3743 REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \ 3743 REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \
3744 REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \ 3744 REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \
3745} while(0) 3745} while(0)
3746 3746
3747#define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC ) 3747#define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC )
3748#define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC ) 3748#define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC )
3749#define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL ) 3749#define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL )
3750#define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL ) 3750#define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL )
3751#define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF ) 3751#define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF )
3752#define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF ) 3752#define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF )
3753 3753
3754#define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH ) 3754#define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH )
3755#define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH ) 3755#define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH )
3756 3756
3757#define __aic_enable_transmit_intr() \ 3757#define __aic_enable_transmit_intr() \
3758 ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) ) 3758 ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) )
3759#define __aic_disable_transmit_intr() \ 3759#define __aic_disable_transmit_intr() \
3760 ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) ) 3760 ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) )
3761#define __aic_enable_receive_intr() \ 3761#define __aic_enable_receive_intr() \
3762 ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) ) 3762 ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) )
3763#define __aic_disable_receive_intr() \ 3763#define __aic_disable_receive_intr() \
3764 ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) ) 3764 ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) )
3765 3765
3766#define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS ) 3766#define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS )
3767#define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS ) 3767#define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS )
3768#define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS ) 3768#define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS )
3769#define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS ) 3769#define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS )
3770 3770
3771#define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S ) 3771#define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S )
3772#define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S ) 3772#define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S )
3773#define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW ) 3773#define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW )
3774#define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW ) 3774#define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW )
3775#define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU ) 3775#define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU )
3776#define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU ) 3776#define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU )
3777 3777
3778#define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3 3778#define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3
3779#define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4 3779#define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4
3780#define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6 3780#define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6
3781#define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7 3781#define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7
3782#define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8 3782#define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8
3783#define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9 3783#define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9
3784 3784
3785#define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3 3785#define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3
3786#define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4 3786#define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4
3787#define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6 3787#define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6
3788#define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7 3788#define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7
3789#define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8 3789#define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8
3790#define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9 3790#define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9
3791 3791
3792#define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK ) 3792#define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK )
3793#define __ac97_set_xs_mono() \ 3793#define __ac97_set_xs_mono() \
3794do { \ 3794do { \
3795 REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ 3795 REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
3796 REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \ 3796 REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \
3797} while(0) 3797} while(0)
3798#define __ac97_set_xs_stereo() \ 3798#define __ac97_set_xs_stereo() \
3799do { \ 3799do { \
3800 REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ 3800 REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
3801 REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \ 3801 REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \
3802} while(0) 3802} while(0)
3803 3803
3804/* In fact, only stereo is support now. */ 3804/* In fact, only stereo is support now. */
3805#define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK ) 3805#define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK )
3806#define __ac97_set_rs_mono() \ 3806#define __ac97_set_rs_mono() \
3807do { \ 3807do { \
3808 REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ 3808 REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
3809 REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \ 3809 REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \
3810} while(0) 3810} while(0)
3811#define __ac97_set_rs_stereo() \ 3811#define __ac97_set_rs_stereo() \
3812do { \ 3812do { \
3813 REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ 3813 REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
3814 REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \ 3814 REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \
3815} while(0) 3815} while(0)
3816 3816
3817#define __ac97_warm_reset_codec() \ 3817#define __ac97_warm_reset_codec() \
3818 do { \ 3818 do { \
3819 REG_AIC_ACCR2 |= AIC_ACCR2_SA; \ 3819 REG_AIC_ACCR2 |= AIC_ACCR2_SA; \
3820 REG_AIC_ACCR2 |= AIC_ACCR2_SS; \ 3820 REG_AIC_ACCR2 |= AIC_ACCR2_SS; \
3821 udelay(2); \ 3821 udelay(2); \
3822 REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \ 3822 REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \
3823 REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \ 3823 REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \
3824 } while (0) 3824 } while (0)
3825 3825
3826#define __ac97_cold_reset_codec() \ 3826#define __ac97_cold_reset_codec() \
3827 do { \ 3827 do { \
3828 REG_AIC_ACCR2 |= AIC_ACCR2_SR; \ 3828 REG_AIC_ACCR2 |= AIC_ACCR2_SR; \
3829 udelay(2); \ 3829 udelay(2); \
3830 REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \ 3830 REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \
3831 } while (0) 3831 } while (0)
3832 3832
3833/* n=8,16,18,20 */ 3833/* n=8,16,18,20 */
3834#define __ac97_set_iass(n) \ 3834#define __ac97_set_iass(n) \
3835 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT ) 3835 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT )
3836#define __ac97_set_oass(n) \ 3836#define __ac97_set_oass(n) \
3837 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT ) 3837 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT )
3838 3838
3839#define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL ) 3839#define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL )
3840#define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL ) 3840#define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL )
3841 3841
3842/* n=8,16,18,20,24 */ 3842/* n=8,16,18,20,24 */
3843/*#define __i2s_set_sample_size(n) \ 3843/*#define __i2s_set_sample_size(n) \
3844 ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/ 3844 ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/
3845 3845
3846#define __i2s_set_oss_sample_size(n) \ 3846#define __i2s_set_oss_sample_size(n) \
3847 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT ) 3847 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT )
3848#define __i2s_set_iss_sample_size(n) \ 3848#define __i2s_set_iss_sample_size(n) \
3849 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT ) 3849 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT )
3850 3850
3851#define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK ) 3851#define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK )
3852#define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK ) 3852#define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK )
3853 3853
3854#define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS ) 3854#define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS )
3855#define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS ) 3855#define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS )
3856#define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR ) 3856#define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR )
3857#define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR ) 3857#define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR )
3858 3858
3859#define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) ) 3859#define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) )
3860 3860
3861#define __aic_get_transmit_resident() \ 3861#define __aic_get_transmit_resident() \
3862 ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT ) 3862 ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT )
3863#define __aic_get_receive_count() \ 3863#define __aic_get_receive_count() \
3864 ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT ) 3864 ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT )
3865 3865
3866#define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT ) 3866#define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT )
3867#define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR ) 3867#define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR )
3868#define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO ) 3868#define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO )
3869#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM ) 3869#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM )
3870#define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY ) 3870#define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY )
3871#define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR ) 3871#define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR )
3872#define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR ) 3872#define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR )
3873 3873
3874#define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY ) 3874#define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY )
3875 3875
3876#define CODEC_READ_CMD (1 << 19) 3876#define CODEC_READ_CMD (1 << 19)
3877#define CODEC_WRITE_CMD (0 << 19) 3877#define CODEC_WRITE_CMD (0 << 19)
3878#define CODEC_REG_INDEX_BIT 12 3878#define CODEC_REG_INDEX_BIT 12
3879#define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */ 3879#define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */
3880#define CODEC_REG_DATA_BIT 4 3880#define CODEC_REG_DATA_BIT 4
3881#define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */ 3881#define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */
3882 3882
3883#define __ac97_out_rcmd_addr(reg) \ 3883#define __ac97_out_rcmd_addr(reg) \
3884do { \ 3884do { \
3885 REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ 3885 REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
3886} while (0) 3886} while (0)
3887 3887
3888#define __ac97_out_wcmd_addr(reg) \ 3888#define __ac97_out_wcmd_addr(reg) \
3889do { \ 3889do { \
3890 REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ 3890 REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
3891} while (0) 3891} while (0)
3892 3892
3893#define __ac97_out_data(value) \ 3893#define __ac97_out_data(value) \
3894do { \ 3894do { \
3895 REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \ 3895 REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \
3896} while (0) 3896} while (0)
3897 3897
3898#define __ac97_in_data() \ 3898#define __ac97_in_data() \
3899 ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT ) 3899 ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT )
3900 3900
3901#define __ac97_in_status_addr() \ 3901#define __ac97_in_status_addr() \
3902 ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT ) 3902 ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT )
3903 3903
3904#define __i2s_set_sample_rate(i2sclk, sync) \ 3904#define __i2s_set_sample_rate(i2sclk, sync) \
3905 ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) ) 3905 ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) )
3906 3906
3907#define __aic_write_tfifo(v) ( REG_AIC_DR = (v) ) 3907#define __aic_write_tfifo(v) ( REG_AIC_DR = (v) )
3908#define __aic_read_rfifo() ( REG_AIC_DR ) 3908#define __aic_read_rfifo() ( REG_AIC_DR )
3909 3909
3910#define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC ) 3910#define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC )
3911#define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC ) 3911#define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC )
3912 3912
3913#define AIC_FR_LSMP (1 << 6) 3913#define AIC_FR_LSMP (1 << 6)
3914#define __aic_play_lastsample() ( REG_AIC_FR |= AIC_FR_LSMP ) 3914#define __aic_play_lastsample() ( REG_AIC_FR |= AIC_FR_LSMP )
3915// 3915//
3916// Define next ops for AC97 compatible 3916// Define next ops for AC97 compatible
3917// 3917//
3918 3918
3919#define AC97_ACSR AIC_ACSR 3919#define AC97_ACSR AIC_ACSR
3920 3920
3921#define __ac97_enable() __aic_enable(); __aic_select_ac97() 3921#define __ac97_enable() __aic_enable(); __aic_select_ac97()
3922#define __ac97_disable() __aic_disable() 3922#define __ac97_disable() __aic_disable()
3923#define __ac97_reset() __aic_reset() 3923#define __ac97_reset() __aic_reset()
3924 3924
3925#define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n) 3925#define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
3926#define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n) 3926#define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n)
3927 3927
3928#define __ac97_enable_record() __aic_enable_record() 3928#define __ac97_enable_record() __aic_enable_record()
3929#define __ac97_disable_record() __aic_disable_record() 3929#define __ac97_disable_record() __aic_disable_record()
3930#define __ac97_enable_replay() __aic_enable_replay() 3930#define __ac97_enable_replay() __aic_enable_replay()
3931#define __ac97_disable_replay() __aic_disable_replay() 3931#define __ac97_disable_replay() __aic_disable_replay()
3932#define __ac97_enable_loopback() __aic_enable_loopback() 3932#define __ac97_enable_loopback() __aic_enable_loopback()
3933#define __ac97_disable_loopback() __aic_disable_loopback() 3933#define __ac97_disable_loopback() __aic_disable_loopback()
3934 3934
3935#define __ac97_enable_transmit_dma() __aic_enable_transmit_dma() 3935#define __ac97_enable_transmit_dma() __aic_enable_transmit_dma()
3936#define __ac97_disable_transmit_dma() __aic_disable_transmit_dma() 3936#define __ac97_disable_transmit_dma() __aic_disable_transmit_dma()
3937#define __ac97_enable_receive_dma() __aic_enable_receive_dma() 3937#define __ac97_enable_receive_dma() __aic_enable_receive_dma()
3938#define __ac97_disable_receive_dma() __aic_disable_receive_dma() 3938#define __ac97_disable_receive_dma() __aic_disable_receive_dma()
3939 3939
3940#define __ac97_transmit_request() __aic_transmit_request() 3940#define __ac97_transmit_request() __aic_transmit_request()
3941#define __ac97_receive_request() __aic_receive_request() 3941#define __ac97_receive_request() __aic_receive_request()
3942#define __ac97_transmit_underrun() __aic_transmit_underrun() 3942#define __ac97_transmit_underrun() __aic_transmit_underrun()
3943#define __ac97_receive_overrun() __aic_receive_overrun() 3943#define __ac97_receive_overrun() __aic_receive_overrun()
3944 3944
3945#define __ac97_clear_errors() __aic_clear_errors() 3945#define __ac97_clear_errors() __aic_clear_errors()
3946 3946
3947#define __ac97_get_transmit_resident() __aic_get_transmit_resident() 3947#define __ac97_get_transmit_resident() __aic_get_transmit_resident()
3948#define __ac97_get_receive_count() __aic_get_receive_count() 3948#define __ac97_get_receive_count() __aic_get_receive_count()
3949 3949
3950#define __ac97_enable_transmit_intr() __aic_enable_transmit_intr() 3950#define __ac97_enable_transmit_intr() __aic_enable_transmit_intr()
3951#define __ac97_disable_transmit_intr() __aic_disable_transmit_intr() 3951#define __ac97_disable_transmit_intr() __aic_disable_transmit_intr()
3952#define __ac97_enable_receive_intr() __aic_enable_receive_intr() 3952#define __ac97_enable_receive_intr() __aic_enable_receive_intr()
3953#define __ac97_disable_receive_intr() __aic_disable_receive_intr() 3953#define __ac97_disable_receive_intr() __aic_disable_receive_intr()
3954 3954
3955#define __ac97_write_tfifo(v) __aic_write_tfifo(v) 3955#define __ac97_write_tfifo(v) __aic_write_tfifo(v)
3956#define __ac97_read_rfifo() __aic_read_rfifo() 3956#define __ac97_read_rfifo() __aic_read_rfifo()
3957 3957
3958// 3958//
3959// Define next ops for I2S compatible 3959// Define next ops for I2S compatible
3960// 3960//
3961 3961
3962#define I2S_ACSR AIC_I2SSR 3962#define I2S_ACSR AIC_I2SSR
3963 3963
3964#define __i2s_enable() __aic_enable(); __aic_select_i2s() 3964#define __i2s_enable() __aic_enable(); __aic_select_i2s()
3965#define __i2s_disable() __aic_disable() 3965#define __i2s_disable() __aic_disable()
3966#define __i2s_reset() __aic_reset() 3966#define __i2s_reset() __aic_reset()
3967 3967
3968#define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n) 3968#define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
3969#define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n) 3969#define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n)
3970 3970
3971#define __i2s_enable_record() __aic_enable_record() 3971#define __i2s_enable_record() __aic_enable_record()
3972#define __i2s_disable_record() __aic_disable_record() 3972#define __i2s_disable_record() __aic_disable_record()
3973#define __i2s_enable_replay() __aic_enable_replay() 3973#define __i2s_enable_replay() __aic_enable_replay()
3974#define __i2s_disable_replay() __aic_disable_replay() 3974#define __i2s_disable_replay() __aic_disable_replay()
3975#define __i2s_enable_loopback() __aic_enable_loopback() 3975#define __i2s_enable_loopback() __aic_enable_loopback()
3976#define __i2s_disable_loopback() __aic_disable_loopback() 3976#define __i2s_disable_loopback() __aic_disable_loopback()
3977 3977
3978#define __i2s_enable_transmit_dma() __aic_enable_transmit_dma() 3978#define __i2s_enable_transmit_dma() __aic_enable_transmit_dma()
3979#define __i2s_disable_transmit_dma() __aic_disable_transmit_dma() 3979#define __i2s_disable_transmit_dma() __aic_disable_transmit_dma()
3980#define __i2s_enable_receive_dma() __aic_enable_receive_dma() 3980#define __i2s_enable_receive_dma() __aic_enable_receive_dma()
3981#define __i2s_disable_receive_dma() __aic_disable_receive_dma() 3981#define __i2s_disable_receive_dma() __aic_disable_receive_dma()
3982 3982
3983#define __i2s_transmit_request() __aic_transmit_request() 3983#define __i2s_transmit_request() __aic_transmit_request()
3984#define __i2s_receive_request() __aic_receive_request() 3984#define __i2s_receive_request() __aic_receive_request()
3985#define __i2s_transmit_underrun() __aic_transmit_underrun() 3985#define __i2s_transmit_underrun() __aic_transmit_underrun()
3986#define __i2s_receive_overrun() __aic_receive_overrun() 3986#define __i2s_receive_overrun() __aic_receive_overrun()
3987 3987
3988#define __i2s_clear_errors() __aic_clear_errors() 3988#define __i2s_clear_errors() __aic_clear_errors()
3989 3989
3990#define __i2s_get_transmit_resident() __aic_get_transmit_resident() 3990#define __i2s_get_transmit_resident() __aic_get_transmit_resident()
3991#define __i2s_get_receive_count() __aic_get_receive_count() 3991#define __i2s_get_receive_count() __aic_get_receive_count()
3992 3992
3993#define __i2s_enable_transmit_intr() __aic_enable_transmit_intr() 3993#define __i2s_enable_transmit_intr() __aic_enable_transmit_intr()
3994#define __i2s_disable_transmit_intr() __aic_disable_transmit_intr() 3994#define __i2s_disable_transmit_intr() __aic_disable_transmit_intr()
3995#define __i2s_enable_receive_intr() __aic_enable_receive_intr() 3995#define __i2s_enable_receive_intr() __aic_enable_receive_intr()
3996#define __i2s_disable_receive_intr() __aic_disable_receive_intr() 3996#define __i2s_disable_receive_intr() __aic_disable_receive_intr()
3997 3997
3998#define __i2s_write_tfifo(v) __aic_write_tfifo(v) 3998#define __i2s_write_tfifo(v) __aic_write_tfifo(v)
3999#define __i2s_read_rfifo() __aic_read_rfifo() 3999#define __i2s_read_rfifo() __aic_read_rfifo()
4000 4000
4001#define __i2s_reset_codec() \ 4001#define __i2s_reset_codec() \
4002 do { \ 4002 do { \
4003 } while (0) 4003 } while (0)
4004 4004
4005 4005
4006/*************************************************************************** 4006/***************************************************************************
4007 * ICDC 4007 * ICDC
4008 ***************************************************************************/ 4008 ***************************************************************************/
4009#define __i2s_internal_codec() __aic_internal_codec() 4009#define __i2s_internal_codec() __aic_internal_codec()
4010#define __i2s_external_codec() __aic_external_codec() 4010#define __i2s_external_codec() __aic_external_codec()
4011 4011
4012/*************************************************************************** 4012/***************************************************************************
4013 * INTC 4013 * INTC
4014 ***************************************************************************/ 4014 ***************************************************************************/
4015#define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) ) 4015#define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) )
4016#define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) ) 4016#define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) )
4017#define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) ) 4017#define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) )
4018 4018
4019 4019
4020/*************************************************************************** 4020/***************************************************************************
4021 * I2C 4021 * I2C
4022 ***************************************************************************/ 4022 ***************************************************************************/
4023 4023
4024#define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE ) 4024#define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE )
4025#define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE ) 4025#define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE )
4026 4026
4027#define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA ) 4027#define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA )
4028#define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO ) 4028#define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO )
4029#define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC ) 4029#define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC )
4030#define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC ) 4030#define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC )
4031 4031
4032#define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF ) 4032#define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF )
4033#define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF ) 4033#define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF )
4034#define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF ) 4034#define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF )
4035 4035
4036#define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) ) 4036#define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) )
4037#define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY ) 4037#define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY )
4038#define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND ) 4038#define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND )
4039 4039
4040#define __i2c_set_clk(dev_clk, i2c_clk) \ 4040#define __i2c_set_clk(dev_clk, i2c_clk) \
4041 ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 ) 4041 ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 )
4042 4042
4043#define __i2c_read() ( REG_I2C_DR ) 4043#define __i2c_read() ( REG_I2C_DR )
4044#define __i2c_write(val) ( REG_I2C_DR = (val) ) 4044#define __i2c_write(val) ( REG_I2C_DR = (val) )
4045 4045
4046 4046
4047/*************************************************************************** 4047/***************************************************************************
4048 * MSC 4048 * MSC
4049 ***************************************************************************/ 4049 ***************************************************************************/
4050 4050
4051#define __msc_start_op() \ 4051#define __msc_start_op() \
4052 ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START ) 4052 ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START )
4053 4053
4054#define __msc_set_resto(to) ( REG_MSC_RESTO = to ) 4054#define __msc_set_resto(to) ( REG_MSC_RESTO = to )
4055#define __msc_set_rdto(to) ( REG_MSC_RDTO = to ) 4055#define __msc_set_rdto(to) ( REG_MSC_RDTO = to )
4056#define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd ) 4056#define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd )
4057#define __msc_set_arg(arg) ( REG_MSC_ARG = arg ) 4057#define __msc_set_arg(arg) ( REG_MSC_ARG = arg )
4058#define __msc_set_nob(nob) ( REG_MSC_NOB = nob ) 4058#define __msc_set_nob(nob) ( REG_MSC_NOB = nob )
4059#define __msc_get_nob() ( REG_MSC_NOB ) 4059#define __msc_get_nob() ( REG_MSC_NOB )
4060#define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len ) 4060#define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len )
4061#define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat ) 4061#define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat )
4062#define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT ) 4062#define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT )
4063#define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT ) 4063#define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT )
4064 4064
4065#define __msc_set_cmdat_bus_width1() \ 4065#define __msc_set_cmdat_bus_width1() \
4066do { \ 4066do { \
4067 REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ 4067 REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
4068 REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \ 4068 REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \
4069} while(0) 4069} while(0)
4070 4070
4071#define __msc_set_cmdat_bus_width4() \ 4071#define __msc_set_cmdat_bus_width4() \
4072do { \ 4072do { \
4073 REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ 4073 REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
4074 REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \ 4074 REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \
4075} while(0) 4075} while(0)
4076 4076
4077#define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN ) 4077#define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN )
4078#define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT ) 4078#define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT )
4079#define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY ) 4079#define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY )
4080#define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK ) 4080#define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK )
4081#define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK ) 4081#define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK )
4082#define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ ) 4082#define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ )
4083#define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ ) 4083#define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ )
4084#define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN ) 4084#define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN )
4085 4085
4086/* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */ 4086/* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */
4087#define __msc_set_cmdat_res_format(r) \ 4087#define __msc_set_cmdat_res_format(r) \
4088do { \ 4088do { \
4089 REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \ 4089 REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \
4090 REG_MSC_CMDAT |= (r); \ 4090 REG_MSC_CMDAT |= (r); \
4091} while(0) 4091} while(0)
4092 4092
4093#define __msc_clear_cmdat() \ 4093#define __msc_clear_cmdat() \
4094 REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \ 4094 REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \
4095 MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \ 4095 MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \
4096 MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK ) 4096 MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK )
4097 4097
4098#define __msc_get_imask() ( REG_MSC_IMASK ) 4098#define __msc_get_imask() ( REG_MSC_IMASK )
4099#define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff ) 4099#define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff )
4100#define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 ) 4100#define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 )
4101#define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ ) 4101#define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ )
4102#define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ ) 4102#define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ )
4103#define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ ) 4103#define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ )
4104#define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ ) 4104#define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ )
4105#define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES ) 4105#define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES )
4106#define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES ) 4106#define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES )
4107#define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE ) 4107#define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE )
4108#define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE ) 4108#define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE )
4109#define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE ) 4109#define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE )
4110#define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE ) 4110#define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE )
4111 4111
4112/* n=0,1,2,3,4,5,6,7 */ 4112/* n=0,1,2,3,4,5,6,7 */
4113#define __msc_set_clkrt(n) \ 4113#define __msc_set_clkrt(n) \
4114do { \ 4114do { \
4115 REG_MSC_CLKRT = n; \ 4115 REG_MSC_CLKRT = n; \
4116} while(0) 4116} while(0)
4117 4117
4118#define __msc_get_ireg() ( REG_MSC_IREG ) 4118#define __msc_get_ireg() ( REG_MSC_IREG )
4119#define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ ) 4119#define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ )
4120#define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ ) 4120#define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ )
4121#define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES ) 4121#define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES )
4122#define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE ) 4122#define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE )
4123#define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE ) 4123#define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE )
4124#define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES ) 4124#define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES )
4125#define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE ) 4125#define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE )
4126#define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE ) 4126#define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE )
4127 4127
4128#define __msc_get_stat() ( REG_MSC_STAT ) 4128#define __msc_get_stat() ( REG_MSC_STAT )
4129#define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0) 4129#define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0)
4130#define __msc_stat_crc_err() \ 4130#define __msc_stat_crc_err() \
4131 ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) ) 4131 ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) )
4132#define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR ) 4132#define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR )
4133#define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR ) 4133#define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR )
4134#define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES ) 4134#define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES )
4135#define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES ) 4135#define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES )
4136#define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ ) 4136#define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ )
4137 4137
4138#define __msc_rd_resfifo() ( REG_MSC_RES ) 4138#define __msc_rd_resfifo() ( REG_MSC_RES )
4139#define __msc_rd_rxfifo() ( REG_MSC_RXFIFO ) 4139#define __msc_rd_rxfifo() ( REG_MSC_RXFIFO )
4140#define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v ) 4140#define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v )
4141 4141
4142#define __msc_reset() \ 4142#define __msc_reset() \
4143do { \ 4143do { \
4144 REG_MSC_STRPCL = MSC_STRPCL_RESET; \ 4144 REG_MSC_STRPCL = MSC_STRPCL_RESET; \
4145 while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \ 4145 while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \
4146} while (0) 4146} while (0)
4147 4147
4148#define __msc_start_clk() \ 4148#define __msc_start_clk() \
4149do { \ 4149do { \
4150 REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; \ 4150 REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; \
4151} while (0) 4151} while (0)
4152 4152
4153#define __msc_stop_clk() \ 4153#define __msc_stop_clk() \
4154do { \ 4154do { \
4155 REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \ 4155 REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \
4156} while (0) 4156} while (0)
4157 4157
4158#define MMC_CLK 19169200 4158#define MMC_CLK 19169200
4159#define SD_CLK 24576000 4159#define SD_CLK 24576000
4160 4160
4161/* msc_clk should little than pclk and little than clk retrieve from card */ 4161/* msc_clk should little than pclk and little than clk retrieve from card */
4162#define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \ 4162#define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \
4163do { \ 4163do { \
4164 unsigned int rate, pclk, i; \ 4164 unsigned int rate, pclk, i; \
4165 pclk = dev_clk; \ 4165 pclk = dev_clk; \
4166 rate = type?SD_CLK:MMC_CLK; \ 4166 rate = type?SD_CLK:MMC_CLK; \
4167 if (msc_clk && msc_clk < pclk) \ 4167 if (msc_clk && msc_clk < pclk) \
4168 pclk = msc_clk; \ 4168 pclk = msc_clk; \
4169 i = 0; \ 4169 i = 0; \
4170 while (pclk < rate) \ 4170 while (pclk < rate) \
4171 { \ 4171 { \
4172 i ++; \ 4172 i ++; \
4173 rate >>= 1; \ 4173 rate >>= 1; \
4174 } \ 4174 } \
4175 lv = i; \ 4175 lv = i; \
4176} while(0) 4176} while(0)
4177 4177
4178/* divide rate to little than or equal to 400kHz */ 4178/* divide rate to little than or equal to 400kHz */
4179#define __msc_calc_slow_clk_divisor(type, lv) \ 4179#define __msc_calc_slow_clk_divisor(type, lv) \
4180do { \ 4180do { \
4181 unsigned int rate, i; \ 4181 unsigned int rate, i; \
4182 rate = (type?SD_CLK:MMC_CLK)/1000/400; \ 4182 rate = (type?SD_CLK:MMC_CLK)/1000/400; \
4183 i = 0; \ 4183 i = 0; \
4184 while (rate > 0) \ 4184 while (rate > 0) \
4185 { \ 4185 { \
4186 rate >>= 1; \ 4186 rate >>= 1; \
4187 i ++; \ 4187 i ++; \
4188 } \ 4188 } \
4189 lv = i; \ 4189 lv = i; \
4190} while(0) 4190} while(0)
4191 4191
4192 4192
4193/*************************************************************************** 4193/***************************************************************************
4194 * SSI 4194 * SSI
4195 ***************************************************************************/ 4195 ***************************************************************************/
4196 4196
4197#define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE ) 4197#define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE )
4198#define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE ) 4198#define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE )
4199#define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL ) 4199#define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL )
4200 4200
4201#define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK ) 4201#define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK )
4202 4202
4203#define __ssi_select_ce2() \ 4203#define __ssi_select_ce2() \
4204do { \ 4204do { \
4205 REG_SSI_CR0 |= SSI_CR0_FSEL; \ 4205 REG_SSI_CR0 |= SSI_CR0_FSEL; \
4206 REG_SSI_CR1 &= ~SSI_CR1_MULTS; \ 4206 REG_SSI_CR1 &= ~SSI_CR1_MULTS; \
4207} while (0) 4207} while (0)
4208 4208
4209#define __ssi_select_gpc() \ 4209#define __ssi_select_gpc() \
4210do { \ 4210do { \
4211 REG_SSI_CR0 &= ~SSI_CR0_FSEL; \ 4211 REG_SSI_CR0 &= ~SSI_CR0_FSEL; \
4212 REG_SSI_CR1 |= SSI_CR1_MULTS; \ 4212 REG_SSI_CR1 |= SSI_CR1_MULTS; \
4213} while (0) 4213} while (0)
4214 4214
4215#define __ssi_enable_tx_intr() \ 4215#define __ssi_enable_tx_intr() \
4216 ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE ) 4216 ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE )
4217 4217
4218#define __ssi_disable_tx_intr() \ 4218#define __ssi_disable_tx_intr() \
4219 ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) ) 4219 ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) )
4220 4220
4221#define __ssi_enable_rx_intr() \ 4221#define __ssi_enable_rx_intr() \
4222 ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE ) 4222 ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE )
4223 4223
4224#define __ssi_disable_rx_intr() \ 4224#define __ssi_disable_rx_intr() \
4225 ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) ) 4225 ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) )
4226 4226
4227#define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP ) 4227#define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP )
4228#define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP ) 4228#define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP )
4229 4229
4230#define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV ) 4230#define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV )
4231#define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV ) 4231#define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV )
4232 4232
4233#define __ssi_finish_receive() \ 4233#define __ssi_finish_receive() \
4234 ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) ) 4234 ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) )
4235 4235
4236#define __ssi_disable_recvfinish() \ 4236#define __ssi_disable_recvfinish() \
4237 ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) ) 4237 ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) )
4238 4238
4239#define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH ) 4239#define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH )
4240#define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH ) 4240#define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH )
4241 4241
4242#define __ssi_flush_fifo() \ 4242#define __ssi_flush_fifo() \
4243 ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH ) 4243 ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH )
4244 4244
4245#define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN ) 4245#define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN )
4246 4246
4247#define __ssi_spi_format() \ 4247#define __ssi_spi_format() \
4248do { \ 4248do { \
4249 REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ 4249 REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \
4250 REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \ 4250 REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \
4251 REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ 4251 REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\
4252 REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \ 4252 REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \
4253} while (0) 4253} while (0)
4254 4254
4255/* TI's SSP format, must clear SSI_CR1.UNFIN */ 4255/* TI's SSP format, must clear SSI_CR1.UNFIN */
4256#define __ssi_ssp_format() \ 4256#define __ssi_ssp_format() \
4257do { \ 4257do { \
4258 REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \ 4258 REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \
4259 REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \ 4259 REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \
4260} while (0) 4260} while (0)
4261 4261
4262/* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */ 4262/* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */
4263#define __ssi_microwire_format() \ 4263#define __ssi_microwire_format() \
4264do { \ 4264do { \
4265 REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ 4265 REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \
4266 REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \ 4266 REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \
4267 REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ 4267 REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\
4268 REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \ 4268 REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \
4269 REG_SSI_CR0 &= ~SSI_CR0_RFINE; \ 4269 REG_SSI_CR0 &= ~SSI_CR0_RFINE; \
4270} while (0) 4270} while (0)
4271 4271
4272/* CE# level (FRMHL), CE# in interval time (ITFRM), 4272/* CE# level (FRMHL), CE# in interval time (ITFRM),
4273 clock phase and polarity (PHA POL), 4273 clock phase and polarity (PHA POL),
4274 interval time (SSIITR), interval characters/frame (SSIICR) */ 4274 interval time (SSIITR), interval characters/frame (SSIICR) */
4275 4275
4276 /* frmhl,endian,mcom,flen,pha,pol MASK */ 4276 /* frmhl,endian,mcom,flen,pha,pol MASK */
4277#define SSICR1_MISC_MASK \ 4277#define SSICR1_MISC_MASK \
4278 ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \ 4278 ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \
4279 | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \ 4279 | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \
4280 4280
4281#define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \ 4281#define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \
4282do { \ 4282do { \
4283 REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \ 4283 REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \
4284 REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \ 4284 REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \
4285 (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \ 4285 (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \
4286 ((pha) << 1) | (pol); \ 4286 ((pha) << 1) | (pol); \
4287} while(0) 4287} while(0)
4288 4288
4289/* Transfer with MSB or LSB first */ 4289/* Transfer with MSB or LSB first */
4290#define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST ) 4290#define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST )
4291#define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST ) 4291#define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST )
4292 4292
4293#define __ssi_set_frame_length(n) \ 4293#define __ssi_set_frame_length(n) \
4294 REG_SSI_CR1 = (REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | (((n) - 2) << 4) 4294 REG_SSI_CR1 = (REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | (((n) - 2) << 4)
4295 4295
4296/* n = 1 - 16 */ 4296/* n = 1 - 16 */
4297#define __ssi_set_microwire_command_length(n) \ 4297#define __ssi_set_microwire_command_length(n) \
4298 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) ) 4298 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) )
4299 4299
4300/* Set the clock phase for SPI */ 4300/* Set the clock phase for SPI */
4301#define __ssi_set_spi_clock_phase(n) \ 4301#define __ssi_set_spi_clock_phase(n) \
4302 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) ) 4302 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) )
4303 4303
4304/* Set the clock polarity for SPI */ 4304/* Set the clock polarity for SPI */
4305#define __ssi_set_spi_clock_polarity(n) \ 4305#define __ssi_set_spi_clock_polarity(n) \
4306 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) ) 4306 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) )
4307 4307
4308/* n = ix8 */ 4308/* n = ix8 */
4309#define __ssi_set_tx_trigger(n) \ 4309#define __ssi_set_tx_trigger(n) \
4310do { \ 4310do { \
4311 REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \ 4311 REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \
4312 REG_SSI_CR1 |= SSI_CR1_TTRG_##n; \ 4312 REG_SSI_CR1 |= SSI_CR1_TTRG_##n; \
4313} while (0) 4313} while (0)
4314 4314
4315/* n = ix8 */ 4315/* n = ix8 */
4316#define __ssi_set_rx_trigger(n) \ 4316#define __ssi_set_rx_trigger(n) \
4317do { \ 4317do { \
4318 REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \ 4318 REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \
4319 REG_SSI_CR1 |= SSI_CR1_RTRG_##n; \ 4319 REG_SSI_CR1 |= SSI_CR1_RTRG_##n; \
4320} while (0) 4320} while (0)
4321 4321
4322#define __ssi_get_txfifo_count() \ 4322#define __ssi_get_txfifo_count() \
4323 ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT ) 4323 ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT )
4324 4324
4325#define __ssi_get_rxfifo_count() \ 4325#define __ssi_get_rxfifo_count() \
4326 ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT ) 4326 ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT )
4327 4327
4328#define __ssi_clear_errors() \ 4328#define __ssi_clear_errors() \
4329 ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) ) 4329 ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) )
4330 4330
4331#define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END ) 4331#define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END )
4332#define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY ) 4332#define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY )
4333 4333
4334#define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF ) 4334#define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF )
4335#define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE ) 4335#define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE )
4336#define __ssi_rxfifo_noempty() ( REG_SSI_SR & SSI_SR_RFHF ) 4336#define __ssi_rxfifo_noempty() ( REG_SSI_SR & SSI_SR_RFHF )
4337 4337
4338#define __ssi_set_clk(dev_clk, ssi_clk) \ 4338#define __ssi_set_clk(dev_clk, ssi_clk) \
4339 ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 ) 4339 ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 )
4340 4340
4341#define __ssi_receive_data() REG_SSI_DR 4341#define __ssi_receive_data() REG_SSI_DR
4342#define __ssi_transmit_data(v) ( REG_SSI_DR = (v) ) 4342#define __ssi_transmit_data(v) ( REG_SSI_DR = (v) )
4343 4343
4344 4344
4345/*************************************************************************** 4345/***************************************************************************
4346 * CIM 4346 * CIM
4347 ***************************************************************************/ 4347 ***************************************************************************/
4348 4348
4349#define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA ) 4349#define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA )
4350#define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA ) 4350#define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA )
4351 4351
4352#define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT ) 4352#define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT )
4353#define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT ) 4353#define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT )
4354 4354
4355#define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP ) 4355#define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP )
4356#define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP ) 4356#define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP )
4357 4357
4358#define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP ) 4358#define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP )
4359#define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP ) 4359#define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP )
4360 4360
4361#define __cim_sample_data_at_pclk_falling_edge() \ 4361#define __cim_sample_data_at_pclk_falling_edge() \
4362 ( REG_CIM_CFG |= CIM_CFG_PCP ) 4362 ( REG_CIM_CFG |= CIM_CFG_PCP )
4363#define __cim_sample_data_at_pclk_rising_edge() \ 4363#define __cim_sample_data_at_pclk_rising_edge() \
4364 ( REG_CIM_CFG &= ~CIM_CFG_PCP ) 4364 ( REG_CIM_CFG &= ~CIM_CFG_PCP )
4365 4365
4366#define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO ) 4366#define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO )
4367#define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO ) 4367#define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO )
4368 4368
4369#define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC ) 4369#define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC )
4370#define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC ) 4370#define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC )
4371 4371
4372/* n=0-7 */ 4372/* n=0-7 */
4373#define __cim_set_data_packing_mode(n) \ 4373#define __cim_set_data_packing_mode(n) \
4374do { \ 4374do { \
4375 REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \ 4375 REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \
4376 REG_CIM_CFG |= (CIM_CFG_PACK_##n); \ 4376 REG_CIM_CFG |= (CIM_CFG_PACK_##n); \
4377} while (0) 4377} while (0)
4378 4378
4379#define __cim_enable_ccir656_progressive_mode() \ 4379#define __cim_enable_ccir656_progressive_mode() \
4380do { \ 4380do { \
4381 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 4381 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
4382 REG_CIM_CFG |= CIM_CFG_DSM_CPM; \ 4382 REG_CIM_CFG |= CIM_CFG_DSM_CPM; \
4383} while (0) 4383} while (0)
4384 4384
4385#define __cim_enable_ccir656_interlace_mode() \ 4385#define __cim_enable_ccir656_interlace_mode() \
4386do { \ 4386do { \
4387 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 4387 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
4388 REG_CIM_CFG |= CIM_CFG_DSM_CIM; \ 4388 REG_CIM_CFG |= CIM_CFG_DSM_CIM; \
4389} while (0) 4389} while (0)
4390 4390
4391#define __cim_enable_gated_clock_mode() \ 4391#define __cim_enable_gated_clock_mode() \
4392do { \ 4392do { \
4393 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 4393 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
4394 REG_CIM_CFG |= CIM_CFG_DSM_GCM; \ 4394 REG_CIM_CFG |= CIM_CFG_DSM_GCM; \
4395} while (0) 4395} while (0)
4396 4396
4397#define __cim_enable_nongated_clock_mode() \ 4397#define __cim_enable_nongated_clock_mode() \
4398do { \ 4398do { \
4399 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 4399 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
4400 REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \ 4400 REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \
4401} while (0) 4401} while (0)
4402 4402
4403/* sclk:system bus clock 4403/* sclk:system bus clock
4404 * mclk: CIM master clock 4404 * mclk: CIM master clock
4405 */ 4405 */
4406#define __cim_set_master_clk(sclk, mclk) \ 4406#define __cim_set_master_clk(sclk, mclk) \
4407do { \ 4407do { \
4408 REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \ 4408 REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \
4409 REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \ 4409 REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \
4410} while (0) 4410} while (0)
4411 4411
4412#define __cim_enable_sof_intr() \ 4412#define __cim_enable_sof_intr() \
4413 ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM ) 4413 ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM )
4414#define __cim_disable_sof_intr() \ 4414#define __cim_disable_sof_intr() \
4415 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM ) 4415 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM )
4416 4416
4417#define __cim_enable_eof_intr() \ 4417#define __cim_enable_eof_intr() \
4418 ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM ) 4418 ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM )
4419#define __cim_disable_eof_intr() \ 4419#define __cim_disable_eof_intr() \
4420 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM ) 4420 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM )
4421 4421
4422#define __cim_enable_stop_intr() \ 4422#define __cim_enable_stop_intr() \
4423 ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM ) 4423 ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM )
4424#define __cim_disable_stop_intr() \ 4424#define __cim_disable_stop_intr() \
4425 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM ) 4425 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM )
4426 4426
4427#define __cim_enable_trig_intr() \ 4427#define __cim_enable_trig_intr() \
4428 ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM ) 4428 ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM )
4429#define __cim_disable_trig_intr() \ 4429#define __cim_disable_trig_intr() \
4430 ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM ) 4430 ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM )
4431 4431
4432#define __cim_enable_rxfifo_overflow_intr() \ 4432#define __cim_enable_rxfifo_overflow_intr() \
4433 ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM ) 4433 ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM )
4434#define __cim_disable_rxfifo_overflow_intr() \ 4434#define __cim_disable_rxfifo_overflow_intr() \
4435 ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM ) 4435 ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM )
4436 4436
4437/* n=1-16 */ 4437/* n=1-16 */
4438#define __cim_set_frame_rate(n) \ 4438#define __cim_set_frame_rate(n) \
4439do { \ 4439do { \
4440 REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \ 4440 REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \
4441 REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \ 4441 REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \
4442} while (0) 4442} while (0)
4443 4443
4444#define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN ) 4444#define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN )
4445#define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN ) 4445#define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN )
4446 4446
4447#define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST ) 4447#define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST )
4448#define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST ) 4448#define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST )
4449 4449
4450/* n=4,8,12,16,20,24,28,32 */ 4450/* n=4,8,12,16,20,24,28,32 */
4451#define __cim_set_rxfifo_trigger(n) \ 4451#define __cim_set_rxfifo_trigger(n) \
4452do { \ 4452do { \
4453 REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \ 4453 REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \
4454 REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \ 4454 REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \
4455} while (0) 4455} while (0)
4456 4456
4457#define __cim_clear_state() ( REG_CIM_STATE = 0 ) 4457#define __cim_clear_state() ( REG_CIM_STATE = 0 )
4458 4458
4459#define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD ) 4459#define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD )
4460#define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY ) 4460#define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY )
4461#define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG ) 4461#define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG )
4462#define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF ) 4462#define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF )
4463#define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF ) 4463#define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF )
4464#define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP ) 4464#define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP )
4465#define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF ) 4465#define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF )
4466#define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF ) 4466#define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF )
4467 4467
4468#define __cim_get_iid() ( REG_CIM_IID ) 4468#define __cim_get_iid() ( REG_CIM_IID )
4469#define __cim_get_image_data() ( REG_CIM_RXFIFO ) 4469#define __cim_get_image_data() ( REG_CIM_RXFIFO )
4470#define __cim_get_dam_cmd() ( REG_CIM_CMD ) 4470#define __cim_get_dam_cmd() ( REG_CIM_CMD )
4471 4471
4472#define __cim_set_da(a) ( REG_CIM_DA = (a) ) 4472#define __cim_set_da(a) ( REG_CIM_DA = (a) )
4473 4473
4474/*************************************************************************** 4474/***************************************************************************
4475 * LCD 4475 * LCD
4476 ***************************************************************************/ 4476 ***************************************************************************/
4477#define __lcd_as_smart_lcd() ( REG_LCD_CFG |= (1<<LCD_CFG_LCDPIN_BIT) ) 4477#define __lcd_as_smart_lcd() ( REG_LCD_CFG |= (1<<LCD_CFG_LCDPIN_BIT) )
4478#define __lcd_as_general_lcd() ( REG_LCD_CFG &= ~(1<<LCD_CFG_LCDPIN_BIT) ) 4478#define __lcd_as_general_lcd() ( REG_LCD_CFG &= ~(1<<LCD_CFG_LCDPIN_BIT) )
4479 4479
4480#define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS ) 4480#define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS )
4481#define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS ) 4481#define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS )
4482 4482
4483#define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA ) 4483#define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA )
4484#define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA ) 4484#define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA )
4485 4485
4486/* n=1,2,4,8,16 */ 4486/* n=1,2,4,8,16 */
4487#define __lcd_set_bpp(n) \ 4487#define __lcd_set_bpp(n) \
4488 ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n ) 4488 ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n )
4489 4489
4490/* n=4,8,16 */ 4490/* n=4,8,16 */
4491#define __lcd_set_burst_length(n) \ 4491#define __lcd_set_burst_length(n) \
4492do { \ 4492do { \
4493 REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \ 4493 REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \
4494 REG_LCD_CTRL |= LCD_CTRL_BST_n##; \ 4494 REG_LCD_CTRL |= LCD_CTRL_BST_n##; \
4495} while (0) 4495} while (0)
4496 4496
4497#define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 ) 4497#define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 )
4498#define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 ) 4498#define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 )
4499 4499
4500#define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP ) 4500#define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP )
4501#define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP ) 4501#define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP )
4502 4502
4503/* n=2,4,16 */ 4503/* n=2,4,16 */
4504#define __lcd_set_stn_frc(n) \ 4504#define __lcd_set_stn_frc(n) \
4505do { \ 4505do { \
4506 REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \ 4506 REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \
4507 REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \ 4507 REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \
4508} while (0) 4508} while (0)
4509 4509
4510 4510
4511#define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN ) 4511#define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN )
4512#define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN ) 4512#define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN )
4513 4513
4514#define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN ) 4514#define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN )
4515#define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN ) 4515#define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN )
4516 4516
4517#define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM ) 4517#define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM )
4518#define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM ) 4518#define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM )
4519 4519
4520#define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM ) 4520#define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM )
4521#define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM ) 4521#define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM )
4522 4522
4523#define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM ) 4523#define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM )
4524#define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM ) 4524#define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM )
4525 4525
4526#define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 ) 4526#define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 )
4527#define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 ) 4527#define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 )
4528 4528
4529#define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 ) 4529#define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 )
4530#define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 ) 4530#define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 )
4531 4531
4532#define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM ) 4532#define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM )
4533#define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM ) 4533#define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM )
4534 4534
4535#define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM ) 4535#define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM )
4536#define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM ) 4536#define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM )
4537 4537
4538 4538
4539/* LCD status register indication */ 4539/* LCD status register indication */
4540 4540
4541#define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD ) 4541#define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD )
4542#define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD ) 4542#define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD )
4543#define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 ) 4543#define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 )
4544#define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 ) 4544#define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 )
4545#define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU ) 4545#define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU )
4546#define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF ) 4546#define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF )
4547#define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF ) 4547#define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF )
4548 4548
4549#define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU ) 4549#define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU )
4550#define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF ) 4550#define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF )
4551#define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF ) 4551#define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF )
4552 4552
4553#define __lcd_panel_white() ( REG_LCD_CFG |= LCD_CFG_WHITE ) 4553#define __lcd_panel_white() ( REG_LCD_CFG |= LCD_CFG_WHITE )
4554#define __lcd_panel_black() ( REG_LCD_CFG &= ~LCD_CFG_WHITE ) 4554#define __lcd_panel_black() ( REG_LCD_CFG &= ~LCD_CFG_WHITE )
4555 4555
4556/* n=1,2,4,8 for single mono-STN 4556/* n=1,2,4,8 for single mono-STN
4557 * n=4,8 for dual mono-STN 4557 * n=4,8 for dual mono-STN
4558 */ 4558 */
4559#define __lcd_set_panel_datawidth(n) \ 4559#define __lcd_set_panel_datawidth(n) \
4560do { \ 4560do { \
4561 REG_LCD_CFG &= ~LCD_CFG_PDW_MASK; \ 4561 REG_LCD_CFG &= ~LCD_CFG_PDW_MASK; \
4562 REG_LCD_CFG |= LCD_CFG_PDW_n##; \ 4562 REG_LCD_CFG |= LCD_CFG_PDW_n##; \
4563} while (0) 4563} while (0)
4564 4564
4565/* m=LCD_CFG_MODE_GENERUIC_TFT_xxx */ 4565/* m=LCD_CFG_MODE_GENERUIC_TFT_xxx */
4566#define __lcd_set_panel_mode(m) \ 4566#define __lcd_set_panel_mode(m) \
4567do { \ 4567do { \
4568 REG_LCD_CFG &= ~LCD_CFG_MODE_MASK; \ 4568 REG_LCD_CFG &= ~LCD_CFG_MODE_MASK; \
4569 REG_LCD_CFG |= (m); \ 4569 REG_LCD_CFG |= (m); \
4570} while(0) 4570} while(0)
4571 4571
4572/* n = 0-255 */ 4572/* n = 0-255 */
4573#define __lcd_disable_ac_bias() ( REG_LCD_IO = 0xff ) 4573#define __lcd_disable_ac_bias() ( REG_LCD_IO = 0xff )
4574#define __lcd_set_ac_bias(n) \ 4574#define __lcd_set_ac_bias(n) \
4575do { \ 4575do { \
4576 REG_LCD_IO &= ~LCD_IO_ACB_MASK; \ 4576 REG_LCD_IO &= ~LCD_IO_ACB_MASK; \
4577 REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT); \ 4577 REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT); \
4578} while(0) 4578} while(0)
4579 4579
4580#define __lcd_io_set_dir() ( REG_LCD_IO |= LCD_IO_DIR ) 4580#define __lcd_io_set_dir() ( REG_LCD_IO |= LCD_IO_DIR )
4581#define __lcd_io_clr_dir() ( REG_LCD_IO &= ~LCD_IO_DIR ) 4581#define __lcd_io_clr_dir() ( REG_LCD_IO &= ~LCD_IO_DIR )
4582 4582
4583#define __lcd_io_set_dep() ( REG_LCD_IO |= LCD_IO_DEP ) 4583#define __lcd_io_set_dep() ( REG_LCD_IO |= LCD_IO_DEP )
4584#define __lcd_io_clr_dep() ( REG_LCD_IO &= ~LCD_IO_DEP ) 4584#define __lcd_io_clr_dep() ( REG_LCD_IO &= ~LCD_IO_DEP )
4585 4585
4586#define __lcd_io_set_vsp() ( REG_LCD_IO |= LCD_IO_VSP ) 4586#define __lcd_io_set_vsp() ( REG_LCD_IO |= LCD_IO_VSP )
4587#define __lcd_io_clr_vsp() ( REG_LCD_IO &= ~LCD_IO_VSP ) 4587#define __lcd_io_clr_vsp() ( REG_LCD_IO &= ~LCD_IO_VSP )
4588 4588
4589#define __lcd_io_set_hsp() ( REG_LCD_IO |= LCD_IO_HSP ) 4589#define __lcd_io_set_hsp() ( REG_LCD_IO |= LCD_IO_HSP )
4590#define __lcd_io_clr_hsp() ( REG_LCD_IO &= ~LCD_IO_HSP ) 4590#define __lcd_io_clr_hsp() ( REG_LCD_IO &= ~LCD_IO_HSP )
4591 4591
4592#define __lcd_io_set_pcp() ( REG_LCD_IO |= LCD_IO_PCP ) 4592#define __lcd_io_set_pcp() ( REG_LCD_IO |= LCD_IO_PCP )
4593#define __lcd_io_clr_pcp() ( REG_LCD_IO &= ~LCD_IO_PCP ) 4593#define __lcd_io_clr_pcp() ( REG_LCD_IO &= ~LCD_IO_PCP )
4594 4594
4595#define __lcd_vsync_get_vps() \ 4595#define __lcd_vsync_get_vps() \
4596 ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT ) 4596 ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT )
4597 4597
4598#define __lcd_vsync_get_vpe() \ 4598#define __lcd_vsync_get_vpe() \
4599 ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT ) 4599 ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT )
4600#define __lcd_vsync_set_vpe(n) \ 4600#define __lcd_vsync_set_vpe(n) \
4601do { \ 4601do { \
4602 REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \ 4602 REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \
4603 REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \ 4603 REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \
4604} while (0) 4604} while (0)
4605 4605
4606#define __lcd_hsync_get_hps() \ 4606#define __lcd_hsync_get_hps() \
4607 ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT ) 4607 ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT )
4608#define __lcd_hsync_set_hps(n) \ 4608#define __lcd_hsync_set_hps(n) \
4609do { \ 4609do { \
4610 REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \ 4610 REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \
4611 REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \ 4611 REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \
4612} while (0) 4612} while (0)
4613 4613
4614#define __lcd_hsync_get_hpe() \ 4614#define __lcd_hsync_get_hpe() \
4615 ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT ) 4615 ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT )
4616#define __lcd_hsync_set_hpe(n) \ 4616#define __lcd_hsync_set_hpe(n) \
4617do { \ 4617do { \
4618 REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \ 4618 REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \
4619 REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \ 4619 REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \
4620} while (0) 4620} while (0)
4621 4621
4622#define __lcd_vat_get_ht() \ 4622#define __lcd_vat_get_ht() \
4623 ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT ) 4623 ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT )
4624#define __lcd_vat_set_ht(n) \ 4624#define __lcd_vat_set_ht(n) \
4625do { \ 4625do { \
4626 REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \ 4626 REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \
4627 REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \ 4627 REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \
4628} while (0) 4628} while (0)
4629 4629
4630#define __lcd_vat_get_vt() \ 4630#define __lcd_vat_get_vt() \
4631 ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT ) 4631 ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT )
4632#define __lcd_vat_set_vt(n) \ 4632#define __lcd_vat_set_vt(n) \
4633do { \ 4633do { \
4634 REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \ 4634 REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \
4635 REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \ 4635 REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \
4636} while (0) 4636} while (0)
4637 4637
4638#define __lcd_dah_get_hds() \ 4638#define __lcd_dah_get_hds() \
4639 ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT ) 4639 ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT )
4640#define __lcd_dah_set_hds(n) \ 4640#define __lcd_dah_set_hds(n) \
4641do { \ 4641do { \
4642 REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \ 4642 REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \
4643 REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \ 4643 REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \
4644} while (0) 4644} while (0)
4645 4645
4646#define __lcd_dah_get_hde() \ 4646#define __lcd_dah_get_hde() \
4647 ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT ) 4647 ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT )
4648#define __lcd_dah_set_hde(n) \ 4648#define __lcd_dah_set_hde(n) \
4649do { \ 4649do { \
4650 REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \ 4650 REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \
4651 REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \ 4651 REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \
4652} while (0) 4652} while (0)
4653 4653
4654#define __lcd_dav_get_vds() \ 4654#define __lcd_dav_get_vds() \
4655 ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT ) 4655 ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT )
4656#define __lcd_dav_set_vds(n) \ 4656#define __lcd_dav_set_vds(n) \
4657do { \ 4657do { \
4658 REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \ 4658 REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \
4659 REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \ 4659 REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \
4660} while (0) 4660} while (0)
4661 4661
4662#define __lcd_dav_get_vde() \ 4662#define __lcd_dav_get_vde() \
4663 ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT ) 4663 ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT )
4664#define __lcd_dav_set_vde(n) \ 4664#define __lcd_dav_set_vde(n) \
4665do { \ 4665do { \
4666 REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \ 4666 REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \
4667 REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \ 4667 REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \
4668} while (0) 4668} while (0)
4669 4669
4670#define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT ) 4670#define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT )
4671#define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT ) 4671#define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT )
4672#define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT ) 4672#define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT )
4673#define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT ) 4673#define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT )
4674 4674
4675#define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT ) 4675#define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT )
4676#define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT ) 4676#define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT )
4677#define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT ) 4677#define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT )
4678#define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT ) 4678#define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT )
4679 4679
4680#define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL ) 4680#define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL )
4681#define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL ) 4681#define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL )
4682 4682
4683#define __lcd_cmd0_get_len() \ 4683#define __lcd_cmd0_get_len() \
4684 ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) 4684 ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
4685#define __lcd_cmd1_get_len() \ 4685#define __lcd_cmd1_get_len() \
4686 ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) 4686 ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
4687 4687
4688/*************************************************************************** 4688/***************************************************************************
4689 * RTC ops 4689 * RTC ops
4690 ***************************************************************************/ 4690 ***************************************************************************/
4691 4691
4692#define __rtc_write_ready() ( REG_RTC_RCR & RTC_RCR_WRDY ) 4692#define __rtc_write_ready() ( REG_RTC_RCR & RTC_RCR_WRDY )
4693#define __rtc_enabled() \ 4693#define __rtc_enabled() \
4694do{ \ 4694do{ \
4695 while(!__rtc_write_ready()); \ 4695 while(!__rtc_write_ready()); \
4696 REG_RTC_RCR |= RTC_RCR_RTCE ; \ 4696 REG_RTC_RCR |= RTC_RCR_RTCE ; \
4697}while(0) \ 4697}while(0) \
4698 4698
4699#define __rtc_disabled() \ 4699#define __rtc_disabled() \
4700do{ \ 4700do{ \
4701 while(!__rtc_write_ready()); \ 4701 while(!__rtc_write_ready()); \
4702 REG_RTC_RCR &= ~RTC_RCR_RTCE; \ 4702 REG_RTC_RCR &= ~RTC_RCR_RTCE; \
4703}while(0) 4703}while(0)
4704#define __rtc_enable_alarm() \ 4704#define __rtc_enable_alarm() \
4705do{ \ 4705do{ \
4706 while(!__rtc_write_ready()); \ 4706 while(!__rtc_write_ready()); \
4707 REG_RTC_RCR |= RTC_RCR_AE; \ 4707 REG_RTC_RCR |= RTC_RCR_AE; \
4708}while(0) 4708}while(0)
4709 4709
4710#define __rtc_disable_alarm() \ 4710#define __rtc_disable_alarm() \
4711do{ \ 4711do{ \
4712 while(!__rtc_write_ready()); \ 4712 while(!__rtc_write_ready()); \
4713 REG_RTC_RCR &= ~RTC_RCR_AE; \ 4713 REG_RTC_RCR &= ~RTC_RCR_AE; \
4714}while(0) 4714}while(0)
4715 4715
4716#define __rtc_enable_alarm_irq() \ 4716#define __rtc_enable_alarm_irq() \
4717do{ \ 4717do{ \
4718 while(!__rtc_write_ready()); \ 4718 while(!__rtc_write_ready()); \
4719 REG_RTC_RCR |= RTC_RCR_AIE; \ 4719 REG_RTC_RCR |= RTC_RCR_AIE; \
4720}while(0) 4720}while(0)
4721 4721
4722#define __rtc_disable_alarm_irq() \ 4722#define __rtc_disable_alarm_irq() \
4723do{ \ 4723do{ \
4724 while(!__rtc_write_ready()); \ 4724 while(!__rtc_write_ready()); \
4725 REG_RTC_RCR &= ~RTC_RCR_AIE; \ 4725 REG_RTC_RCR &= ~RTC_RCR_AIE; \
4726}while(0) 4726}while(0)
4727#define __rtc_enable_Hz_irq() \ 4727#define __rtc_enable_Hz_irq() \
4728do{ \ 4728do{ \
4729 while(!__rtc_write_ready()); \ 4729 while(!__rtc_write_ready()); \
4730 REG_RTC_RCR |= RTC_RCR_HZIE; \ 4730 REG_RTC_RCR |= RTC_RCR_HZIE; \
4731}while(0) 4731}while(0)
4732 4732
4733#define __rtc_disable_Hz_irq() \ 4733#define __rtc_disable_Hz_irq() \
4734do{ \ 4734do{ \
4735 while(!__rtc_write_ready()); \ 4735 while(!__rtc_write_ready()); \
4736 REG_RTC_RCR &= ~RTC_RCR_HZIE; \ 4736 REG_RTC_RCR &= ~RTC_RCR_HZIE; \
4737}while(0) 4737}while(0)
4738#define __rtc_get_1Hz_flag() \ 4738#define __rtc_get_1Hz_flag() \
4739do{ \ 4739do{ \
4740 while(!__rtc_write_ready()); \ 4740 while(!__rtc_write_ready()); \
4741 ((REG_RTC_RCR >> RTC_RCR_HZ) & 0x1); \ 4741 ((REG_RTC_RCR >> RTC_RCR_HZ) & 0x1); \
4742}while(0) 4742}while(0)
4743#define __rtc_clear_1Hz_flag() \ 4743#define __rtc_clear_1Hz_flag() \
4744do{ \ 4744do{ \
4745 while(!__rtc_write_ready()); \ 4745 while(!__rtc_write_ready()); \
4746 REG_RTC_RCR &= ~RTC_RCR_HZ; \ 4746 REG_RTC_RCR &= ~RTC_RCR_HZ; \
4747}while(0) 4747}while(0)
4748#define __rtc_get_alarm_flag() \ 4748#define __rtc_get_alarm_flag() \
4749do{ \ 4749do{ \
4750 while(!__rtc_write_ready()); \ 4750 while(!__rtc_write_ready()); \
4751 ((REG_RTC_RCR >> RTC_RCR_AF) & 0x1); \ 4751 ((REG_RTC_RCR >> RTC_RCR_AF) & 0x1); \
4752while(0) 4752while(0)
4753 4753
4754///( (REG_RTC_RCR >> RTC_RCR_AF_BIT) & 0x1 ) 4754///( (REG_RTC_RCR >> RTC_RCR_AF_BIT) & 0x1 )
4755 4755
4756#define __rtc_clear_alarm_flag() \ 4756#define __rtc_clear_alarm_flag() \
4757do{ \ 4757do{ \
4758 while(!__rtc_write_ready()); \ 4758 while(!__rtc_write_ready()); \
4759 REG_RTC_RCR &= ~RTC_RCR_AF; \ 4759 REG_RTC_RCR &= ~RTC_RCR_AF; \
4760}while(0) 4760}while(0)
4761//do 4761//do
4762#define __rtc_get_second() \ 4762#define __rtc_get_second() \
4763({ \ 4763({ \
4764 while(!__rtc_write_ready());\ 4764 while(!__rtc_write_ready());\
4765 REG_RTC_RSR; \ 4765 REG_RTC_RSR; \
4766}) 4766})
4767//while(0) 4767//while(0)
4768 4768
4769#define __rtc_set_second(v) \ 4769#define __rtc_set_second(v) \
4770do{ \ 4770do{ \
4771 while(!__rtc_write_ready()); \ 4771 while(!__rtc_write_ready()); \
4772 REG_RTC_RSR = v; \ 4772 REG_RTC_RSR = v; \
4773 while(!__rtc_write_ready());\ 4773 while(!__rtc_write_ready());\
4774}while(0) 4774}while(0)
4775 4775
4776#define __rtc_get_alarm_second() \ 4776#define __rtc_get_alarm_second() \
4777do{ \ 4777do{ \
4778 while(!__rtc_write_ready()); \ 4778 while(!__rtc_write_ready()); \
4779 REG_RTC_RSAR; \ 4779 REG_RTC_RSAR; \
4780}while(0) 4780}while(0)
4781 4781
4782 4782
4783#define __rtc_set_alarm_second(v) \ 4783#define __rtc_set_alarm_second(v) \
4784do{ \ 4784do{ \
4785 while(!__rtc_write_ready()); \ 4785 while(!__rtc_write_ready()); \
4786 REG_RTC_RSAR = v; \ 4786 REG_RTC_RSAR = v; \
4787}while(0) 4787}while(0)
4788 4788
4789#define __rtc_RGR_is_locked() \ 4789#define __rtc_RGR_is_locked() \
4790({ \ 4790({ \
4791 while(!__rtc_write_ready()); \ 4791 while(!__rtc_write_ready()); \
4792 REG_RTC_RGR >> RTC_RGR_LOCK; \ 4792 REG_RTC_RGR >> RTC_RGR_LOCK; \
4793}) 4793})
4794#define __rtc_lock_RGR() \ 4794#define __rtc_lock_RGR() \
4795do{ \ 4795do{ \
4796 while(!__rtc_write_ready()); \ 4796 while(!__rtc_write_ready()); \
4797 REG_RTC_RGR |= RTC_RGR_LOCK; \ 4797 REG_RTC_RGR |= RTC_RGR_LOCK; \
4798}while(0) 4798}while(0)
4799 4799
4800#define __rtc_unlock_RGR() \ 4800#define __rtc_unlock_RGR() \
4801do{ \ 4801do{ \
4802 while(!__rtc_write_ready()); \ 4802 while(!__rtc_write_ready()); \
4803 REG_RTC_RGR &= ~RTC_RGR_LOCK; \ 4803 REG_RTC_RGR &= ~RTC_RGR_LOCK; \
4804}while(0) 4804}while(0)
4805 4805
4806#define __rtc_get_adjc_val() \ 4806#define __rtc_get_adjc_val() \
4807do{ \ 4807do{ \
4808 while(!__rtc_write_ready()); \ 4808 while(!__rtc_write_ready()); \
4809 ( (REG_RTC_RGR & RTC_RGR_ADJC_MASK) >> RTC_RGR_ADJC_BIT ); \ 4809 ( (REG_RTC_RGR & RTC_RGR_ADJC_MASK) >> RTC_RGR_ADJC_BIT ); \
4810}while(0) 4810}while(0)
4811#define __rtc_set_adjc_val(v) \ 4811#define __rtc_set_adjc_val(v) \
4812do{ \ 4812do{ \
4813 while(!__rtc_write_ready()); \ 4813 while(!__rtc_write_ready()); \
4814 REG_RTC_RGR = (REG_RTC_RGR & (~RTC_RGR_ADJC_MASK)) |(v << RTC_RGR_ADJC_BIT); \ 4814 REG_RTC_RGR = (REG_RTC_RGR & (~RTC_RGR_ADJC_MASK)) |(v << RTC_RGR_ADJC_BIT); \
4815}while(0) 4815}while(0)
4816 4816
4817#define __rtc_get_nc1Hz_val() \ 4817#define __rtc_get_nc1Hz_val() \
4818 ( (REG_RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT ) 4818 ( (REG_RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT )
4819 4819
4820#define __rtc_set_nc1Hz_val(v) \ 4820#define __rtc_set_nc1Hz_val(v) \
4821do{ \ 4821do{ \
4822 while(!__rtc_write_ready()); \ 4822 while(!__rtc_write_ready()); \
4823 REG_RTC_RGR = (REG_RTC_RGR & (~RTC_RGR_NC1HZ_MASK)) | (v << RTC_RGR_NC1HZ_BIT);\ 4823 REG_RTC_RGR = (REG_RTC_RGR & (~RTC_RGR_NC1HZ_MASK)) | (v << RTC_RGR_NC1HZ_BIT);\
4824}while(0) 4824}while(0)
4825#define __rtc_power_down() \ 4825#define __rtc_power_down() \
4826do{ \ 4826do{ \
4827 while(!__rtc_write_ready()); \ 4827 while(!__rtc_write_ready()); \
4828 REG_RTC_HCR |= RTC_HCR_PD; \ 4828 REG_RTC_HCR |= RTC_HCR_PD; \
4829}while(0) 4829}while(0)
4830 4830
4831#define __rtc_get_hwfcr_val() \ 4831#define __rtc_get_hwfcr_val() \
4832do{ \ 4832do{ \
4833 while(!__rtc_write_ready()); \ 4833 while(!__rtc_write_ready()); \
4834 REG_RTC_HWFCR & RTC_HWFCR_MASK; \ 4834 REG_RTC_HWFCR & RTC_HWFCR_MASK; \
4835}while(0) 4835}while(0)
4836#define __rtc_set_hwfcr_val(v) \ 4836#define __rtc_set_hwfcr_val(v) \
4837do{ \ 4837do{ \
4838 while(!__rtc_write_ready()); \ 4838 while(!__rtc_write_ready()); \
4839 REG_RTC_HWFCR = (v) & RTC_HWFCR_MASK; \ 4839 REG_RTC_HWFCR = (v) & RTC_HWFCR_MASK; \
4840}while(0) 4840}while(0)
4841 4841
4842#define __rtc_get_hrcr_val() \ 4842#define __rtc_get_hrcr_val() \
4843do{ \ 4843do{ \
4844 while(!__rtc_write_ready()); \ 4844 while(!__rtc_write_ready()); \
4845 ( REG_RTC_HRCR & RTC_HRCR_MASK ); \ 4845 ( REG_RTC_HRCR & RTC_HRCR_MASK ); \
4846}while(0) 4846}while(0)
4847#define __rtc_set_hrcr_val(v) \ 4847#define __rtc_set_hrcr_val(v) \
4848do{ \ 4848do{ \
4849 while(!__rtc_write_ready()); \ 4849 while(!__rtc_write_ready()); \
4850 ( REG_RTC_HRCR = (v) & RTC_HRCR_MASK ); \ 4850 ( REG_RTC_HRCR = (v) & RTC_HRCR_MASK ); \
4851}while(0) 4851}while(0)
4852 4852
4853#define __rtc_enable_alarm_wakeup() \ 4853#define __rtc_enable_alarm_wakeup() \
4854do{ \ 4854do{ \
4855 while(!__rtc_write_ready()); \ 4855 while(!__rtc_write_ready()); \
4856 ( REG_RTC_HWCR |= RTC_HWCR_EALM ); \ 4856 ( REG_RTC_HWCR |= RTC_HWCR_EALM ); \
4857}while(0) 4857}while(0)
4858 4858
4859#define __rtc_disable_alarm_wakeup() \ 4859#define __rtc_disable_alarm_wakeup() \
4860do{ \ 4860do{ \
4861 while(!__rtc_write_ready()); \ 4861 while(!__rtc_write_ready()); \
4862 ( REG_RTC_HWCR &= ~RTC_HWCR_EALM ); \ 4862 ( REG_RTC_HWCR &= ~RTC_HWCR_EALM ); \
4863}while(0) 4863}while(0)
4864 4864
4865#define __rtc_status_hib_reset_occur() \ 4865#define __rtc_status_hib_reset_occur() \
4866({ \ 4866({ \
4867 (REG_RTC_HWRSR & RTC_HWRSR_HR); \ 4867 (REG_RTC_HWRSR & RTC_HWRSR_HR); \
4868}) 4868})
4869#define __rtc_status_ppr_reset_occur() \ 4869#define __rtc_status_ppr_reset_occur() \
4870do{ \ 4870do{ \
4871 while(!__rtc_write_ready()); \ 4871 while(!__rtc_write_ready()); \
4872 ( (REG_RTC_HWRSR & RTC_HWRSR_PPR) & 0x1 ); \ 4872 ( (REG_RTC_HWRSR & RTC_HWRSR_PPR) & 0x1 ); \
4873}while(0) 4873}while(0)
4874#define __rtc_status_wakeup_pin_waken_up() \ 4874#define __rtc_status_wakeup_pin_waken_up() \
4875do{ \ 4875do{ \
4876 while(!__rtc_write_ready()); \ 4876 while(!__rtc_write_ready()); \
4877 ( (REG_RTC_HWRSR >> RTC_HWRSR_PIN) & 0x1 ); \ 4877 ( (REG_RTC_HWRSR >> RTC_HWRSR_PIN) & 0x1 ); \
4878}while(0) 4878}while(0)
4879#define __rtc_status_alarm_waken_up() \ 4879#define __rtc_status_alarm_waken_up() \
4880do{ \ 4880do{ \
4881 while(!__rtc_write_ready()); \ 4881 while(!__rtc_write_ready()); \
4882 ( (REG_RTC_HWRSR >> RTC_HWRSR_ALM) & 0x1 ); \ 4882 ( (REG_RTC_HWRSR >> RTC_HWRSR_ALM) & 0x1 ); \
4883}while(0) 4883}while(0)
4884#define __rtc_clear_hib_stat_all() \ 4884#define __rtc_clear_hib_stat_all() \
4885do{ \ 4885do{ \
4886 while(!__rtc_write_ready()); \ 4886 while(!__rtc_write_ready()); \
4887 ( REG_RTC_HWRSR = 0 ); \ 4887 ( REG_RTC_HWRSR = 0 ); \
4888}while(0) 4888}while(0)
4889 4889
4890#define __rtc_get_scratch_pattern() \ 4890#define __rtc_get_scratch_pattern() \
4891({ while(!__rtc_write_ready()); \ 4891({ while(!__rtc_write_ready()); \
4892 (REG_RTC_HSPR);}) 4892 (REG_RTC_HSPR);})
4893#define __rtc_set_scratch_pattern(n) \ 4893#define __rtc_set_scratch_pattern(n) \
4894do{ \ 4894do{ \
4895 while(!__rtc_write_ready()); \ 4895 while(!__rtc_write_ready()); \
4896 (REG_RTC_HSPR = n ); \ 4896 (REG_RTC_HSPR = n ); \
4897}while(0) 4897}while(0)
4898 4898
4899 4899
4900#endif /* !__ASSEMBLY__ */ 4900#endif /* !__ASSEMBLY__ */
4901 4901
4902#endif /* __JZ4740_H__ */ 4902#endif /* __JZ4740_H__ */
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