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Diffstat (limited to 'firmware/export/jz4740.h')
-rw-r--r--firmware/export/jz4740.h25
1 files changed, 13 insertions, 12 deletions
diff --git a/firmware/export/jz4740.h b/firmware/export/jz4740.h
index a025b94116..3688819b19 100644
--- a/firmware/export/jz4740.h
+++ b/firmware/export/jz4740.h
@@ -2354,31 +2354,32 @@
2354 2354
2355 2355
2356/* Power register bit masks */ 2356/* Power register bit masks */
2357#define USB_POWER_SUSPENDM 0x01 2357#define USB_POWER_SUSPENDM 0x01
2358#define USB_POWER_RESUME 0x04 2358#define USB_POWER_RESUME 0x04
2359#define USB_POWER_HSMODE 0x10 2359#define USB_POWER_HSMODE 0x10
2360#define USB_POWER_HSENAB 0x20 2360#define USB_POWER_HSENAB 0x20
2361#define USB_POWER_SOFTCONN 0x40 2361#define USB_POWER_SOFTCONN 0x40
2362 2362
2363/* Interrupt register bit masks */ 2363/* Interrupt register bit masks */
2364#define USB_INTR_SUSPEND 0x01 2364#define USB_INTR_SUSPEND 0x01
2365#define USB_INTR_RESUME 0x02 2365#define USB_INTR_RESUME 0x02
2366#define USB_INTR_RESET 0x04 2366#define USB_INTR_RESET 0x04
2367 2367
2368#define USB_INTR_EP0 0x0001 2368#define USB_INTR_EP0 0x0001
2369#define USB_INTR_INEP1 0x0002 2369#define USB_INTR_INEP1 0x0002
2370#define USB_INTR_INEP2 0x0004 2370#define USB_INTR_INEP2 0x0004
2371#define USB_INTR_OUTEP1 0x0002 2371#define USB_INTR_OUTEP1 0x0002
2372#define USB_INTR_OUTEP2 0x0004
2372 2373
2373/* CSR0 bit masks */ 2374/* CSR0 bit masks */
2374#define USB_CSR0_OUTPKTRDY 0x01 2375#define USB_CSR0_OUTPKTRDY 0x01
2375#define USB_CSR0_INPKTRDY 0x02 2376#define USB_CSR0_INPKTRDY 0x02
2376#define USB_CSR0_SENTSTALL 0x04 2377#define USB_CSR0_SENTSTALL 0x04
2377#define USB_CSR0_DATAEND 0x08 2378#define USB_CSR0_DATAEND 0x08
2378#define USB_CSR0_SETUPEND 0x10 2379#define USB_CSR0_SETUPEND 0x10
2379#define USB_CSR0_SENDSTALL 0x20 2380#define USB_CSR0_SENDSTALL 0x20
2380#define USB_CSR0_SVDOUTPKTRDY 0x40 2381#define USB_CSR0_SVDOUTPKTRDY 0x40
2381#define USB_CSR0_SVDSETUPEND 0x80 2382#define USB_CSR0_SVDSETUPEND 0x80
2382 2383
2383/* Endpoint CSR register bits */ 2384/* Endpoint CSR register bits */
2384#define USB_INCSRH_AUTOSET 0x80 2385#define USB_INCSRH_AUTOSET 0x80