diff options
Diffstat (limited to 'firmware/export/jz4740.h')
| -rw-r--r-- | firmware/export/jz4740.h | 72 |
1 files changed, 36 insertions, 36 deletions
diff --git a/firmware/export/jz4740.h b/firmware/export/jz4740.h index 409d1d5a6a..aa31a229f9 100644 --- a/firmware/export/jz4740.h +++ b/firmware/export/jz4740.h | |||
| @@ -2105,57 +2105,57 @@ | |||
| 2105 | *************************************************************************/ | 2105 | *************************************************************************/ |
| 2106 | 2106 | ||
| 2107 | #define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */ | 2107 | #define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */ |
| 2108 | #define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */ | 2108 | #define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */ |
| 2109 | #define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */ | 2109 | #define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */ |
| 2110 | #define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */ | 2110 | #define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */ |
| 2111 | #define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */ | 2111 | #define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */ |
| 2112 | 2112 | ||
| 2113 | #define REG_SLCD_CFG REG32(SLCD_CFG) | 2113 | #define REG_SLCD_CFG REG32(SLCD_CFG) |
| 2114 | #define REG_SLCD_CTRL REG8(SLCD_CTRL) | 2114 | #define REG_SLCD_CTRL REG8(SLCD_CTRL) |
| 2115 | #define REG_SLCD_STATE REG8(SLCD_STATE) | 2115 | #define REG_SLCD_STATE REG8(SLCD_STATE) |
| 2116 | #define REG_SLCD_DATA REG32(SLCD_DATA) | 2116 | #define REG_SLCD_DATA REG32(SLCD_DATA) |
| 2117 | #define REG_SLCD_FIFO REG32(SLCD_FIFO) | 2117 | #define REG_SLCD_FIFO REG32(SLCD_FIFO) |
| 2118 | 2118 | ||
| 2119 | /* SLCD Configure Register */ | 2119 | /* SLCD Configure Register */ |
| 2120 | #define SLCD_CFG_BURST_BIT 14 | 2120 | #define SLCD_CFG_BURST_BIT 14 |
| 2121 | #define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT) | 2121 | #define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT) |
| 2122 | #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT) | 2122 | #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT) |
| 2123 | #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT) | 2123 | #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT) |
| 2124 | #define SLCD_CFG_DWIDTH_BIT 10 | 2124 | #define SLCD_CFG_DWIDTH_BIT 10 |
| 2125 | #define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT) | 2125 | #define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT) |
| 2126 | #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT) | 2126 | #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT) |
| 2127 | #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT) | 2127 | #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT) |
| 2128 | #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT) | 2128 | #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT) |
| 2129 | #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT) | 2129 | #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT) |
| 2130 | #define SLCD_CFG_DWIDTH_8_x1 (4 << SLCD_CFG_DWIDTH_BIT) | 2130 | #define SLCD_CFG_DWIDTH_8_x1 (4 << SLCD_CFG_DWIDTH_BIT) |
| 2131 | #define SLCD_CFG_DWIDTH_9_x2 (7 << SLCD_CFG_DWIDTH_BIT) | 2131 | #define SLCD_CFG_DWIDTH_9_x2 (7 << SLCD_CFG_DWIDTH_BIT) |
| 2132 | #define SLCD_CFG_CWIDTH_BIT 8 | 2132 | #define SLCD_CFG_CWIDTH_BIT 8 |
| 2133 | #define SLCD_CFG_CWIDTH_MASK (0x3 << SLCD_CFG_CWIDTH_BIT) | 2133 | #define SLCD_CFG_CWIDTH_MASK (0x3 << SLCD_CFG_CWIDTH_BIT) |
| 2134 | #define SLCD_CFG_CWIDTH_16BIT (0 << SLCD_CFG_CWIDTH_BIT) | 2134 | #define SLCD_CFG_CWIDTH_16BIT (0 << SLCD_CFG_CWIDTH_BIT) |
| 2135 | #define SLCD_CFG_CWIDTH_8BIT (1 << SLCD_CFG_CWIDTH_BIT) | 2135 | #define SLCD_CFG_CWIDTH_8BIT (1 << SLCD_CFG_CWIDTH_BIT) |
| 2136 | #define SLCD_CFG_CWIDTH_18BIT (2 << SLCD_CFG_CWIDTH_BIT) | 2136 | #define SLCD_CFG_CWIDTH_18BIT (2 << SLCD_CFG_CWIDTH_BIT) |
| 2137 | #define SLCD_CFG_CS_ACTIVE_LOW (0 << 4) | 2137 | #define SLCD_CFG_CS_ACTIVE_LOW (0 << 4) |
| 2138 | #define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4) | 2138 | #define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4) |
| 2139 | #define SLCD_CFG_RS_CMD_LOW (0 << 3) | 2139 | #define SLCD_CFG_RS_CMD_LOW (0 << 3) |
| 2140 | #define SLCD_CFG_RS_CMD_HIGH (1 << 3) | 2140 | #define SLCD_CFG_RS_CMD_HIGH (1 << 3) |
| 2141 | #define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1) | 2141 | #define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1) |
| 2142 | #define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1) | 2142 | #define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1) |
| 2143 | #define SLCD_CFG_TYPE_PARALLEL (0 << 0) | 2143 | #define SLCD_CFG_TYPE_PARALLEL (0 << 0) |
| 2144 | #define SLCD_CFG_TYPE_SERIAL (1 << 0) | 2144 | #define SLCD_CFG_TYPE_SERIAL (1 << 0) |
| 2145 | 2145 | ||
| 2146 | /* SLCD Control Register */ | 2146 | /* SLCD Control Register */ |
| 2147 | #define SLCD_CTRL_DMA_EN (1 << 0) | 2147 | #define SLCD_CTRL_DMA_EN (1 << 0) |
| 2148 | 2148 | ||
| 2149 | /* SLCD Status Register */ | 2149 | /* SLCD Status Register */ |
| 2150 | #define SLCD_STATE_BUSY (1 << 0) | 2150 | #define SLCD_STATE_BUSY (1 << 0) |
| 2151 | 2151 | ||
| 2152 | /* SLCD Data Register */ | 2152 | /* SLCD Data Register */ |
| 2153 | #define SLCD_DATA_RS_DATA (0 << 31) | 2153 | #define SLCD_DATA_RS_DATA (0 << 31) |
| 2154 | #define SLCD_DATA_RS_COMMAND (1 << 31) | 2154 | #define SLCD_DATA_RS_COMMAND (1 << 31) |
| 2155 | 2155 | ||
| 2156 | /* SLCD FIFO Register */ | 2156 | /* SLCD FIFO Register */ |
| 2157 | #define SLCD_FIFO_RS_DATA (0 << 31) | 2157 | #define SLCD_FIFO_RS_DATA (0 << 31) |
| 2158 | #define SLCD_FIFO_RS_COMMAND (1 << 31) | 2158 | #define SLCD_FIFO_RS_COMMAND (1 << 31) |
| 2159 | 2159 | ||
| 2160 | 2160 | ||
| 2161 | /************************************************************************* | 2161 | /************************************************************************* |