diff options
Diffstat (limited to 'firmware/export/imx31l.h')
| -rwxr-xr-x | firmware/export/imx31l.h | 170 |
1 files changed, 84 insertions, 86 deletions
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h index e2ee7762f4..e38d4a2955 100755 --- a/firmware/export/imx31l.h +++ b/firmware/export/imx31l.h | |||
| @@ -682,92 +682,90 @@ | |||
| 682 | /* | 682 | /* |
| 683 | * UART Control Register 0 Bit Fields. | 683 | * UART Control Register 0 Bit Fields. |
| 684 | */ | 684 | */ |
| 685 | #define EUartUCR1_ADEN (1 << 15) // Auto detect interrupt | 685 | #define EUARTUCR1_ADEN (1 << 15) // Auto detect interrupt |
| 686 | #define EUartUCR1_ADBR (1 << 14) // Auto detect baud rate | 686 | #define EUARTUCR1_ADBR (1 << 14) // Auto detect baud rate |
| 687 | #define EUartUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable | 687 | #define EUARTUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable |
| 688 | #define EUartUCR1_IDEN (1 << 12) // Idle condition interrupt | 688 | #define EUARTUCR1_IDEN (1 << 12) // Idle condition interrupt |
| 689 | #define EUartUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable | 689 | #define EUARTUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable |
| 690 | #define EUartUCR1_RDMAEN (1 << 8) // Recv ready DMA enable | 690 | #define EUARTUCR1_RDMAEN (1 << 8) // Recv ready DMA enable |
| 691 | #define EUartUCR1_IREN (1 << 7) // Infrared interface enable | 691 | #define EUARTUCR1_IREN (1 << 7) // Infrared interface enable |
| 692 | #define EUartUCR1_TXMPTYEN (1 << 6) // Transimitter empt interrupt enable | 692 | #define EUARTUCR1_TXMPTYEN (1 << 6) // Transimitter empt interrupt enable |
| 693 | #define EUartUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable | 693 | #define EUARTUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable |
| 694 | #define EUartUCR1_SNDBRK (1 << 4) // Send break | 694 | #define EUARTUCR1_SNDBRK (1 << 4) // Send break |
| 695 | #define EUartUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable | 695 | #define EUARTUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable |
| 696 | #define EUartUCR1_DOZE (1 << 1) // Doze | 696 | #define EUARTUCR1_DOZE (1 << 1) // Doze |
| 697 | #define EUartUCR1_UARTEN (1 << 0) // UART enabled | 697 | #define EUARTUCR1_UARTEN (1 << 0) // UART enabled |
| 698 | #define EUartUCR2_ESCI (1 << 15) // Escape seq interrupt enable | 698 | #define EUARTUCR2_ESCI (1 << 15) // Escape seq interrupt enable |
| 699 | #define EUartUCR2_IRTS (1 << 14) // Ignore RTS pin | 699 | #define EUARTUCR2_IRTS (1 << 14) // Ignore RTS pin |
| 700 | #define EUartUCR2_CTSC (1 << 13) // CTS pin control | 700 | #define EUARTUCR2_CTSC (1 << 13) // CTS pin control |
| 701 | #define EUartUCR2_CTS (1 << 12) // Clear to send | 701 | #define EUARTUCR2_CTS (1 << 12) // Clear to send |
| 702 | #define EUartUCR2_ESCEN (1 << 11) // Escape enable | 702 | #define EUARTUCR2_ESCEN (1 << 11) // Escape enable |
| 703 | #define EUartUCR2_PREN (1 << 8) // Parity enable | 703 | #define EUARTUCR2_PREN (1 << 8) // Parity enable |
| 704 | #define EUartUCR2_PROE (1 << 7) // Parity odd/even | 704 | #define EUARTUCR2_PROE (1 << 7) // Parity odd/even |
| 705 | #define EUartUCR2_STPB (1 << 6) // Stop | 705 | #define EUARTUCR2_STPB (1 << 6) // Stop |
| 706 | #define EUartUCR2_WS (1 << 5) // Word size | 706 | #define EUARTUCR2_WS (1 << 5) // Word size |
| 707 | #define EUartUCR2_RTSEN (1 << 4) // Request to send interrupt enable | 707 | #define EUARTUCR2_RTSEN (1 << 4) // Request to send interrupt enable |
| 708 | #define EUartUCR2_ATEN (1 << 3) // Aging timer enable | 708 | #define EUARTUCR2_ATEN (1 << 3) // Aging timer enable |
| 709 | #define EUartUCR2_TXEN (1 << 2) // Transmitter enabled | 709 | #define EUARTUCR2_TXEN (1 << 2) // Transmitter enabled |
| 710 | #define EUartUCR2_RXEN (1 << 1) // Receiver enabled | 710 | #define EUARTUCR2_RXEN (1 << 1) // Receiver enabled |
| 711 | #define EUartUCR2_SRST_ (1 << 0) // SW reset | 711 | #define EUARTUCR2_SRST_ (1 << 0) // SW reset |
| 712 | #define EUartUCR3_PARERREN (1 << 12) // Parity enable | 712 | #define EUARTUCR3_PARERREN (1 << 12) // Parity enable |
| 713 | #define EUartUCR3_FRAERREN (1 << 11) // Frame error interrupt enable | 713 | #define EUARTUCR3_FRAERREN (1 << 11) // Frame error interrupt enable |
| 714 | #define EUartUCR3_ADNIMP (1 << 7) // Autobaud detection not improved | 714 | #define EUARTUCR3_ADNIMP (1 << 7) // Autobaud detection not improved |
| 715 | #define EUartUCR3_RXDSEN (1 << 6) // Receive status interrupt enable | 715 | #define EUARTUCR3_RXDSEN (1 << 6) // Receive status interrupt enable |
| 716 | #define EUartUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable | 716 | #define EUARTUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable |
| 717 | #define EUartUCR3_AWAKEN (1 << 4) // Async wake interrupt enable | 717 | #define EUARTUCR3_AWAKEN (1 << 4) // Async wake interrupt enable |
| 718 | #define EUartUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected | 718 | #define EUARTUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected |
| 719 | #define EUartUCR3_INVT (1 << 1) // Inverted Infrared transmission | 719 | #define EUARTUCR3_INVT (1 << 1) // Inverted Infrared transmission |
| 720 | #define EUartUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable | 720 | #define EUARTUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable |
| 721 | #define EUartUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars) | 721 | #define EUARTUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars) |
| 722 | #define EUartUCR4_INVR (1 << 9) // Inverted infrared reception | 722 | #define EUARTUCR4_INVR (1 << 9) // Inverted infrared reception |
| 723 | #define EUartUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable | 723 | #define EUARTUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable |
| 724 | #define EUartUCR4_WKEN (1 << 7) // Wake interrupt enable | 724 | #define EUARTUCR4_WKEN (1 << 7) // Wake interrupt enable |
| 725 | #define EUartUCR4_IRSC (1 << 5) // IR special case | 725 | #define EUARTUCR4_IRSC (1 << 5) // IR special case |
| 726 | #define EUartUCR4_LPBYP (1 << 4) // Low power bypass | 726 | #define EUARTUCR4_LPBYP (1 << 4) // Low power bypass |
| 727 | #define EUartUCR4_TCEN (1 << 3) // Transmit complete interrupt enable | 727 | #define EUARTUCR4_TCEN (1 << 3) // Transmit complete interrupt enable |
| 728 | #define EUartUCR4_BKEN (1 << 2) // Break condition interrupt enable | 728 | #define EUARTUCR4_BKEN (1 << 2) // Break condition interrupt enable |
| 729 | #define EUartUCR4_OREN (1 << 1) // Receiver overrun interrupt enable | 729 | #define EUARTUCR4_OREN (1 << 1) // Receiver overrun interrupt enable |
| 730 | #define EUartUCR4_DREN (1 << 0) // Recv data ready interrupt enable | 730 | #define EUARTUCR4_DREN (1 << 0) // Recv data ready interrupt enable |
| 731 | #define EUartUFCR_RXTL_SHF 0 // Receiver trigger level shift | 731 | #define EUARTUFCR_RXTL_SHF 0 // Receiver trigger level shift |
| 732 | #define EUartUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div> 1) | 732 | #define EUARTUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div> 1) |
| 733 | #define EUartUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div> 2) | 733 | #define EUARTUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div> 2) |
| 734 | #define EUartUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3) | 734 | #define EUARTUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3) |
| 735 | #define EUartUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4) | 735 | #define EUARTUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4) |
| 736 | #define EUartUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5) | 736 | #define EUARTUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5) |
| 737 | #define EUartUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6) | 737 | #define EUARTUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6) |
| 738 | #define EUartUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7) | 738 | #define EUARTUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7) |
| 739 | #define EUartUFCR_TXTL_SHF 10 // Transmitter trigger level shift | 739 | #define EUARTUFCR_TXTL_SHF 10 // Transmitter trigger level shift |
| 740 | #define EUartUSR1_PARITYERR (1 << 15) // Parity error interrupt flag | 740 | #define EUARTUSR1_PARITYERR (1 << 15) // Parity error interrupt flag |
| 741 | #define EUartUSR1_RTSS (1 << 14) // RTS pin status | 741 | #define EUARTUSR1_RTSS (1 << 14) // RTS pin status |
| 742 | #define EUartUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag | 742 | #define EUARTUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag |
| 743 | #define EUartUSR1_RTSD (1 << 12) // RTS delta | 743 | #define EUARTUSR1_RTSD (1 << 12) // RTS delta |
| 744 | #define EUartUSR1_ESCF (1 << 11) // Escape seq interrupt flag | 744 | #define EUARTUSR1_ESCF (1 << 11) // Escape seq interrupt flag |
| 745 | #define EUartUSR1_FRAMERR (1 << 10) // Frame error interrupt flag | 745 | #define EUARTUSR1_FRAMERR (1 << 10) // Frame error interrupt flag |
| 746 | #define EUartUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag | 746 | #define EUARTUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag |
| 747 | #define EUartUSR1_AGTIM (1 << 8) // Aging timeout interrupt status | 747 | #define EUARTUSR1_AGTIM (1 << 8) // Aging timeout interrupt status |
| 748 | #define EUartUSR1_RXDS (1 << 6) // Receiver idle interrupt flag | 748 | #define EUARTUSR1_RXDS (1 << 6) // Receiver idle interrupt flag |
| 749 | #define EUartUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag | 749 | #define EUARTUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag |
| 750 | #define EUartUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag | 750 | #define EUARTUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag |
| 751 | #define EUartUSR2_ADET (1 << 15) // Auto baud rate detect complete | 751 | #define EUARTUSR2_ADET (1 << 15) // Auto baud rate detect complete |
| 752 | #define EUartUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty | 752 | #define EUARTUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty |
| 753 | #define EUartUSR2_IDLE (1 << 12) // Idle condition | 753 | #define EUARTUSR2_IDLE (1 << 12) // Idle condition |
| 754 | #define EUartUSR2_ACST (1 << 11) // Autobaud counter stopped | 754 | #define EUARTUSR2_ACST (1 << 11) // Autobaud counter stopped |
| 755 | #define EUartUSR2_IRINT (1 << 8) // Serial infrared interrupt flag | 755 | #define EUARTUSR2_IRINT (1 << 8) // Serial infrared interrupt flag |
| 756 | #define EUartUSR2_WAKE (1 << 7) // Wake | 756 | #define EUARTUSR2_WAKE (1 << 7) // Wake |
| 757 | #define EUartUSR2_RTSF (1 << 4) // RTS edge interrupt flag | 757 | #define EUARTUSR2_RTSF (1 << 4) // RTS edge interrupt flag |
| 758 | #define EUartUSR2_TXDC (1 << 3) // Transmitter complete | 758 | #define EUARTUSR2_TXDC (1 << 3) // Transmitter complete |
| 759 | #define EUartUSR2_BRCD (1 << 2) // Break condition | 759 | #define EUARTUSR2_BRCD (1 << 2) // Break condition |
| 760 | #define EUartUSR2_ORE (1 << 1) // Overrun error | 760 | #define EUARTUSR2_ORE (1 << 1) // Overrun error |
| 761 | #define EUartUSR2_RDR (1 << 0) // Recv data ready | 761 | #define EUARTUSR2_RDR (1 << 0) // Recv data ready |
| 762 | #define EUartUTS_FRCPERR (1 << 13) // Force parity error | 762 | #define EUARTUTS_FRCPERR (1 << 13) // Force parity error |
| 763 | #define EUartUTS_LOOP (1 << 12) // Loop tx and rx | 763 | #define EUARTUTS_LOOP (1 << 12) // Loop tx and rx |
| 764 | #define EUartUTS_TXEMPTY (1 << 6) // TxFIFO empty | 764 | #define EUARTUTS_TXEMPTY (1 << 6) // TxFIFO empty |
| 765 | #define EUartUTS_RXEMPTY (1 << 5) // RxFIFO empty | 765 | #define EUARTUTS_RXEMPTY (1 << 5) // RxFIFO empty |
| 766 | #define EUartUTS_TXFULL (1 << 4) // TxFIFO full | 766 | #define EUARTUTS_TXFULL (1 << 4) // TxFIFO full |
| 767 | #define EUartUTS_RXFULL (1 << 3) // RxFIFO full | 767 | #define EUARTUTS_RXFULL (1 << 3) // RxFIFO full |
| 768 | #define EUartUTS_SOFTRST (1 << 0) // Software reset | 768 | #define EUARTUTS_SOFTRST (1 << 0) // Software reset |
| 769 | |||
| 770 | #define DelayTimerPresVal 3 | ||
| 771 | 769 | ||
| 772 | #define L2CC_ENABLED | 770 | #define L2CC_ENABLED |
| 773 | 771 | ||