diff options
Diffstat (limited to 'firmware/export/imx31l.h')
-rwxr-xr-x | firmware/export/imx31l.h | 77 |
1 files changed, 66 insertions, 11 deletions
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h index b1f35e80f2..b10fc1ea17 100755 --- a/firmware/export/imx31l.h +++ b/firmware/export/imx31l.h | |||
@@ -25,8 +25,6 @@ | |||
25 | 25 | ||
26 | /* Place in the section with the framebuffer */ | 26 | /* Place in the section with the framebuffer */ |
27 | #define TTB_BASE_ADDR (0x80100000 + 0x00100000 - TTB_SIZE) | 27 | #define TTB_BASE_ADDR (0x80100000 + 0x00100000 - TTB_SIZE) |
28 | #define IRAM_BASE_ADDR 0x1fffc000 | ||
29 | #define L2CC_BASE_ADDR 0x30000000 | ||
30 | 28 | ||
31 | /*Frame Buffer and TTB defines from gigabeat f/x build*/ | 29 | /*Frame Buffer and TTB defines from gigabeat f/x build*/ |
32 | #define FRAME ((short *)0x80100000) /* Framebuffer */ | 30 | #define FRAME ((short *)0x80100000) /* Framebuffer */ |
@@ -37,6 +35,8 @@ | |||
37 | /* | 35 | /* |
38 | * AIPS 1 | 36 | * AIPS 1 |
39 | */ | 37 | */ |
38 | #define IRAM_BASE_ADDR 0x1fffc000 | ||
39 | #define L2CC_BASE_ADDR 0x30000000 | ||
40 | #define AIPS1_BASE_ADDR 0x43F00000 | 40 | #define AIPS1_BASE_ADDR 0x43F00000 |
41 | #define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR | 41 | #define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR |
42 | #define MAX_BASE_ADDR 0x43F04000 | 42 | #define MAX_BASE_ADDR 0x43F04000 |
@@ -133,15 +133,70 @@ | |||
133 | 133 | ||
134 | 134 | ||
135 | /* ATA */ | 135 | /* ATA */ |
136 | #define TIME_OFF (*(REG8_PTR_T)0x43F8C000) | 136 | #define ATA_TIME_OFF (*(REG8_PTR_T)(ATA_BASE_ADDR+0x00)) |
137 | #define TIME_ON (*(REG8_PTR_T)0x43F8C001) | 137 | #define ATA_TIME_ON (*(REG8_PTR_T)(ATA_BASE_ADDR+0x01)) |
138 | #define TIME_1 (*(REG8_PTR_T)0x43F8C002) | 138 | #define ATA_TIME_1 (*(REG8_PTR_T)(ATA_BASE_ADDR+0x02)) |
139 | #define TIME_2W (*(REG8_PTR_T)0x43F8C003) | 139 | #define ATA_TIME_2W (*(REG8_PTR_T)(ATA_BASE_ADDR+0x03)) |
140 | #define TIME_2R (*(REG8_PTR_T)0x43F8C004) | 140 | /* PIO */ |
141 | #define TIME_AX (*(REG8_PTR_T)0x43F8C005) | 141 | #define ATA_TIME_2R (*(REG8_PTR_T)(ATA_BASE_ADDR+0x04)) |
142 | #define TIME_PIO_RDX (*(REG8_PTR_T)0x43F8C00F) | 142 | #define ATA_TIME_AX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x05)) |
143 | #define TIME_4 (*(REG8_PTR_T)0x43F8C007) | 143 | #define ATA_TIME_4 (*(REG8_PTR_T)(ATA_BASE_ADDR+0x07)) |
144 | #define TIME_9 (*(REG8_PTR_T)0x43F8C008) | 144 | #define ATA_TIME_9 (*(REG8_PTR_T)(ATA_BASE_ADDR+0x08)) |
145 | /* MDMA */ | ||
146 | #define ATA_TIME_M (*(REG8_PTR_T)(ATA_BASE_ADDR+0x09)) | ||
147 | #define ATA_TIME_JN (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0A)) | ||
148 | #define ATA_TIME_D (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0B)) | ||
149 | #define ATA_TIME_K (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0C)) | ||
150 | /* UDMA */ | ||
151 | #define ATA_TIME_ACK (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0D)) | ||
152 | #define ATA_TIME_ENV (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0E)) | ||
153 | #define ATA_TIME_PIO_RDX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0F)) | ||
154 | #define ATA_TIME_ZAH (*(REG8_PTR_T)(ATA_BASE_ADDR+0x10)) | ||
155 | #define ATA_TIME_MLIX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x11)) | ||
156 | #define ATA_TIME_DVH (*(REG8_PTR_T)(ATA_BASE_ADDR+0x12)) | ||
157 | #define ATA_TIME_DZFS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x13)) | ||
158 | #define ATA_TIME_DVS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x14)) | ||
159 | #define ATA_TIME_CVS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x15)) | ||
160 | #define ATA_TIME_SS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x16)) | ||
161 | #define ATA_TIME_CYC (*(REG8_PTR_T)(ATA_BASE_ADDR+0x17)) | ||
162 | /* */ | ||
163 | #define ATA_FIFO_DATA_32 (*(REG32_PTR_T)(ATA_BASE_ADDR+0x18)) | ||
164 | #define ATA_FIFO_DATA_16 (*(REG16_PTR_T)(ATA_BASE_ADDR+0x1c)) | ||
165 | #define ATA_FIFO_FILL (*(REG8_PTR_T)(ATA_BASE_ADDR+0x20)) | ||
166 | /* Actually ATA_CONTROL but conflicts arise */ | ||
167 | #define ATA_INTF_CONTROL (*(REG8_PTR_T)(ATA_BASE_ADDR+0x24)) | ||
168 | #define ATA_INTERRUPT_PENDING (*(REG8_PTR_T)(ATA_BASE_ADDR+0x28)) | ||
169 | #define ATA_INTERRUPT_ENABLE (*(REG8_PTR_T)(ATA_BASE_ADDR+0x2c)) | ||
170 | #define ATA_INTERRUPT_CLEAR (*(REG8_PTR_T)(ATA_BASE_ADDR+0x30)) | ||
171 | #define ATA_FIFO_ALARM (*(REG8_PTR_T)(ATA_BASE_ADDR+0x34)) | ||
172 | #define ATA_DRIVE_DATA (*(REG16_PTR_T)(ATA_BASE_ADDR+0xA0)) | ||
173 | #define ATA_DRIVE_FEATURES (*(REG8_PTR_T)(ATA_BASE_ADDR+0xA4)) | ||
174 | #define ATA_DRIVE_SECTOR_COUNT (*(REG8_PTR_T)(ATA_BASE_ADDR+0xA8)) | ||
175 | #define ATA_DRIVE_SECTOR_NUM (*(REG8_PTR_T)(ATA_BASE_ADDR+0xAC)) | ||
176 | #define ATA_DRIVE_CYL_LOW (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB0)) | ||
177 | #define ATA_DRIVE_CYL_HIGH (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB4)) | ||
178 | #define ATA_DRIVE_CYL_HEAD (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB8)) | ||
179 | #define ATA_DRIVE_STATUS (*(REG8_PTR_T)(ATA_BASE_ADDR+0xBC)) /* rd */ | ||
180 | #define ATA_DRIVE_COMMAND (*(REG8_PTR_T)(ATA_BASE_ADDR+0xBC)) /* wr */ | ||
181 | #define ATA_ALT_DRIVE_STATUS (*(REG8_PTR_T)(ATA_BASE_ADDR+0xD8)) /* rd */ | ||
182 | #define ATA_DRIVE_CONTROL (*(REG8_PTR_T)(ATA_BASE_ADDR+0xD8)) /* wr */ | ||
183 | |||
184 | /* ATA_INTF_CONTROL flags */ | ||
185 | #define ATA_FIFO_RST (1 << 7) | ||
186 | #define ATA_ATA_RST (1 << 6) | ||
187 | #define ATA_FIFO_TX_EN (1 << 5) | ||
188 | #define ATA_FIFO_RCV_EN (1 << 4) | ||
189 | #define ATA_DMA_PENDING (1 << 3) | ||
190 | #define ATA_DMA_ULTRA_SELECTED (1 << 2) | ||
191 | #define ATA_DMA_WRITE (1 << 1) | ||
192 | #define ATA_IORDY_EN (1 << 0) | ||
193 | |||
194 | /* ATA_INTERRUPT_PENDING, ATA_INTERRUPT_ENABLE, ATA_INTERRUPT_CLEAR flags */ | ||
195 | #define ATA_INTRQ1 (1 << 7) | ||
196 | #define ATA_FIFO_UNDERFLOW (1 << 6) | ||
197 | #define ATA_FIFO_OVERFLOW (1 << 5) | ||
198 | #define ATA_CONTROLLER_IDLE (1 << 4) | ||
199 | #define ATA_INTRQ2 (1 << 3) | ||
145 | 200 | ||
146 | /* Timers */ | 201 | /* Timers */ |
147 | #define EPITCR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x00)) | 202 | #define EPITCR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x00)) |