diff options
Diffstat (limited to 'firmware/export/imx31l.h')
| -rwxr-xr-x | firmware/export/imx31l.h | 115 |
1 files changed, 49 insertions, 66 deletions
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h index 777fa6981c..9fc51337b1 100755 --- a/firmware/export/imx31l.h +++ b/firmware/export/imx31l.h | |||
| @@ -494,74 +494,57 @@ | |||
| 494 | #define EPITSR_OCIF (1 << 0) | 494 | #define EPITSR_OCIF (1 << 0) |
| 495 | 495 | ||
| 496 | /* GPIO */ | 496 | /* GPIO */ |
| 497 | #define GPIO_DR_I 0x00 /* Offset - 0x00 */ | 497 | #define GPIO1_DR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x00)) |
| 498 | #define GPIO_GDIR_I 0x01 /* Offset - 0x04 */ | 498 | #define GPIO1_GDIR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x04)) |
| 499 | #define GPIO_PSR_I 0x02 /* Offset - 0x08 */ | 499 | #define GPIO1_PSR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x08)) |
| 500 | #define GPIO_ICR1_I 0x03 /* Offset - 0x0C */ | 500 | #define GPIO1_ICR1 (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x0C)) |
| 501 | #define GPIO_ICR2_I 0x04 /* Offset - 0x10 */ | 501 | #define GPIO1_ICR2 (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x10)) |
| 502 | #define GPIO_IMR_I 0x05 /* Offset - 0x14 */ | 502 | #define GPIO1_IMR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x14)) |
| 503 | #define GPIO_ISR_I 0x06 /* Offset - 0x18 */ | 503 | #define GPIO1_ISR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x18)) |
| 504 | 504 | ||
| 505 | #define GPIO1_DR (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_DR_I]) | 505 | #define GPIO2_DR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x00)) |
| 506 | #define GPIO1_GDIR (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_GDIR_I]) | 506 | #define GPIO2_GDIR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x04)) |
| 507 | #define GPIO1_PSR (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_PSR_I]) | 507 | #define GPIO2_PSR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x08)) |
| 508 | #define GPIO1_ICR1 (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_ICR1_I]) | 508 | #define GPIO2_ICR1 (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x0C)) |
| 509 | #define GPIO1_ICR2 (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_ICR2_I]) | 509 | #define GPIO2_ICR2 (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x10)) |
| 510 | #define GPIO1_IMR (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_IMR_I]) | 510 | #define GPIO2_IMR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x14)) |
| 511 | #define GPIO1_ISR (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_ISR_I]) | 511 | #define GPIO2_ISR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x18)) |
| 512 | 512 | ||
| 513 | #define GPIO2_DR (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_DR_I]) | 513 | #define GPIO3_DR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x00)) |
| 514 | #define GPIO2_GDIR (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_GDIR_I]) | 514 | #define GPIO3_GDIR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x04)) |
| 515 | #define GPIO2_PSR (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_PSR_I]) | 515 | #define GPIO3_PSR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x08)) |
| 516 | #define GPIO2_ICR1 (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_ICR1_I]) | 516 | #define GPIO3_ICR1 (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x0C)) |
| 517 | #define GPIO2_ICR2 (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_ICR2_I]) | 517 | #define GPIO3_ICR2 (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x10)) |
| 518 | #define GPIO2_IMR (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_IMR_I]) | 518 | #define GPIO3_IMR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x14)) |
| 519 | #define GPIO2_ISR (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_ISR_I]) | 519 | #define GPIO3_ISR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x18)) |
| 520 | |||
| 521 | #define GPIO3_DR (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_DR_I]) | ||
| 522 | #define GPIO3_GDIR (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_GDIR_I]) | ||
| 523 | #define GPIO3_PSR (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_PSR_I]) | ||
| 524 | #define GPIO3_ICR1 (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_ICR1_I]) | ||
| 525 | #define GPIO3_ICR2 (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_ICR2_I]) | ||
| 526 | #define GPIO3_IMR (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_IMR_I]) | ||
| 527 | #define GPIO3_ISR (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_ISR_I]) | ||
| 528 | 520 | ||
| 529 | /* CSPI */ | 521 | /* CSPI */ |
| 530 | #define CSPI_RXDATA_I 0x00 /* Offset - 0x00 */ | 522 | #define CSPI_RXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x00)) |
| 531 | #define CSPI_TXDATA_I 0x01 /* Offset - 0x04 */ | 523 | #define CSPI_TXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x04)) |
| 532 | #define CSPI_CONREG_I 0x02 /* Offset - 0x08 */ | 524 | #define CSPI_CONREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x08)) |
| 533 | #define CSPI_INTREG_I 0x03 /* Offset - 0x0C */ | 525 | #define CSPI_INTREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x0C)) |
| 534 | #define CSPI_DMAREG_I 0x04 /* Offset - 0x10 */ | 526 | #define CSPI_DMAREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x10)) |
| 535 | #define CSPI_STATREG_I 0x05 /* Offset - 0x14 */ | 527 | #define CSPI_STATREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x14)) |
| 536 | #define CSPI_PERIODREG_I 0x06 /* Offset - 0x18 */ | 528 | #define CSPI_PERIODREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x18)) |
| 537 | #define CSPI_TESTREG_I 0x70 /* Offset - 0x1C0 */ | 529 | #define CSPI_TESTREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x1C0)) |
| 538 | 530 | ||
| 539 | #define CSPI_RXDATA1 (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_RXDATA_I]) | 531 | #define CSPI_RXDATA2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x00)) |
| 540 | #define CSPI_TXDATA1 (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_TXDATA_I]) | 532 | #define CSPI_TXDATA2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x04)) |
| 541 | #define CSPI_CONREG1 (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_CONREG_I]) | 533 | #define CSPI_CONREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x08)) |
| 542 | #define CSPI_INTREG1 (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_INTREG_I]) | 534 | #define CSPI_INTREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x0C)) |
| 543 | #define CSPI_DMAREG1 (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_DMAREG_I]) | 535 | #define CSPI_DMAREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x10)) |
| 544 | #define CSPI_STATREG1 (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_STATREG_I]) | 536 | #define CSPI_STATREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x14)) |
| 545 | #define CSPI_PERIODREG1 (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_PERIODREG_I]) | 537 | #define CSPI_PERIODREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x18)) |
| 546 | #define CSPI_TESTREG1 (((REG32_PTR_T)CSPI1_BASE_ADDR)[CSPI_TESTREG_I]) | 538 | #define CSPI_TESTREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x1C0)) |
| 547 | 539 | ||
| 548 | #define CSPI_RXDATA2 (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_RXDATA_I]) | 540 | #define CSPI_RXDATA3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x00)) |
| 549 | #define CSPI_TXDATA2 (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_TXDATA_I]) | 541 | #define CSPI_TXDATA3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x04)) |
| 550 | #define CSPI_CONREG2 (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_CONREG_I]) | 542 | #define CSPI_CONREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x08)) |
| 551 | #define CSPI_INTREG2 (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_INTREG_I]) | 543 | #define CSPI_INTREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x0C)) |
| 552 | #define CSPI_DMAREG2 (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_DMAREG_I]) | 544 | #define CSPI_DMAREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x10)) |
| 553 | #define CSPI_STATREG2 (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_STATREG_I]) | 545 | #define CSPI_STATREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x14)) |
| 554 | #define CSPI_PERIODREG2 (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_PERIODREG_I]) | 546 | #define CSPI_PERIODREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x18)) |
| 555 | #define CSPI_TESTREG2 (((REG32_PTR_T)CSPI2_BASE_ADDR)[CSPI_TESTREG_I]) | 547 | #define CSPI_TESTREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x1C0)) |
| 556 | |||
| 557 | #define CSPI_RXDATA3 (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_RXDATA_I]) | ||
| 558 | #define CSPI_TXDATA3 (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_TXDATA_I]) | ||
| 559 | #define CSPI_CONREG3 (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_CONREG_I]) | ||
| 560 | #define CSPI_INTREG3 (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_INTREG_I]) | ||
| 561 | #define CSPI_DMAREG3 (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_DMAREG_I]) | ||
| 562 | #define CSPI_STATREG3 (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_STATREG_I]) | ||
| 563 | #define CSPI_PERIODREG3 (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_PERIODREG_I]) | ||
| 564 | #define CSPI_TESTREG3 (((REG32_PTR_T)CSPI3_BASE_ADDR)[CSPI_TESTREG_I]) | ||
| 565 | 548 | ||
| 566 | /* CSPI CONREG flags/fields */ | 549 | /* CSPI CONREG flags/fields */ |
| 567 | #define CSPI_CONREG_CHIP_SELECT_SS0 (0 << 24) | 550 | #define CSPI_CONREG_CHIP_SELECT_SS0 (0 << 24) |