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-rw-r--r--firmware/export/imx31l.h203
1 files changed, 203 insertions, 0 deletions
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h
index dea5588e59..6ad50f0a16 100644
--- a/firmware/export/imx31l.h
+++ b/firmware/export/imx31l.h
@@ -1410,6 +1410,101 @@
1410#define CCM_PDR1_SSI1_PODF (0x3f << 0) 1410#define CCM_PDR1_SSI1_PODF (0x3f << 0)
1411#define CCM_PDR1_SSI1_PODF_POS (0) 1411#define CCM_PDR1_SSI1_PODF_POS (0)
1412 1412
1413/* RCSR */
1414#define CCM_RCSR_NF16B (1 << 31)
1415
1416#define CCM_RCSR_NFMS (1 << 30)
1417
1418#define CCM_RCSR_BTP4 (1 << 27)
1419#define CCM_RCSR_BTP3 (1 << 26)
1420#define CCM_RCSR_BTP2 (1 << 25)
1421#define CCM_RCSR_BTP1 (1 << 24)
1422#define CCM_RCSR_BTP0 (1 << 23)
1423
1424#define CCM_RCSR_OSCNT (0x7f << 16)
1425#define CCM_RCSR_OSCNT_POS (16)
1426
1427#define CCM_RCSR_PERES (1 << 15)
1428
1429#define CCM_RCSR_SDM (0x3 << 12)
1430#define CCM_RCSR_SDM_POS (12)
1431
1432#define CCM_RCSR_GPF (0x7 << 5)
1433#define CCM_RCSR_GPF_POS (5)
1434
1435#define CCM_RCSR_WFIS (1 << 4)
1436
1437#define CCM_RCSR_REST (0x7 << 0)
1438#define CCM_RCSR_REST_POS (0)
1439#define CCM_RCSR_REST_POR_EXT (0x0)
1440#define CCM_RCSR_REST_QUALIFIED_EXT (0x1)
1441#define CCM_RCSR_REST_WATCHDOG_TMO (0x2)
1442/* 0x3 - 0x5: reserved */
1443#define CCM_RCSR_REST_JTAG (0x6)
1444#define CCM_RCSR_REST_ARM11P_GATING (0x7)
1445
1446/* MPCTL */
1447#define CCM_MPCTL_BRM (1 << 31)
1448#define CCM_MPCTL_PD (0xf << 26)
1449#define CCM_MPCTL_PD_POS (26)
1450#define CCM_MPCTL_MFD (0x3ff << 16)
1451#define CCM_MPCTL_MFD_POS (16)
1452#define CCM_MPCTL_MFI (0xf << 10)
1453#define CCM_MPCTL_MFI_POS (10)
1454#define CCM_MPCTL_MFN (0x3ff << 0)
1455#define CCM_MPCTL_MFN_POS (0)
1456
1457/* UPCTL */
1458#define CCM_UPCTL_BRM (1 << 31)
1459#define CCM_UPCTL_PD (0xf << 26)
1460#define CCM_UPCTL_PD_POS (26)
1461#define CCM_UPCTL_MFD (0x3ff << 16)
1462#define CCM_UPCTL_MFD_POS (16)
1463#define CCM_UPCTL_MFI (0xf << 10)
1464#define CCM_UPCTL_MFI_POS (10)
1465#define CCM_UPCTL_MFN (0x3ff << 0)
1466#define CCM_UPCTL_MFN_POS (0)
1467
1468/* SPCTL */
1469#define CCM_SPCTL_BRM (1 << 31)
1470#define CCM_SPCTL_PD (0xf << 26)
1471#define CCM_SPCTL_PD_POS (26)
1472#define CCM_SPCTL_MFD (0x3ff << 16)
1473#define CCM_SPCTL_MFD_POS (16)
1474#define CCM_SPCTL_MFI (0xf << 10)
1475#define CCM_SPCTL_MFI_POS (10)
1476#define CCM_SPCTL_MFN (0x3ff << 0)
1477#define CCM_SPCTL_MFN_POS (0)
1478
1479/* COSR */
1480#define CCM_COSR_CLKOEN (1 << 9)
1481#define CCM_COSR_CLKOUTDIV (0x7 << 6)
1482#define CCM_COSR_CLKOUTDIV_POS (6)
1483#define CCM_COSR_CLKOSEL (0xf << 0)
1484#define CCM_COSR_CLKOSEL_POS (0)
1485#define CCM_COSR_CLKOSEL_MPL_DPDGCK_CLK (0x0)
1486#define CCM_COSR_CLKOSEL_IPG_CLK_CCM (0x1)
1487#define CCM_COSR_CLKOSEL_UPL_DPDGCK_CLK (0x2)
1488#define CCM_COSR_CLKOSEL_PLL_REF_CLK (0x3)
1489#define CCM_COSR_CLKOSEL_FPM_CKIL512_CLK (0x4)
1490#define CCM_COSR_CLKOSEL_IPG_CLK_AHB_ARM (0x5)
1491#define CCM_COSR_CLKOSEL_IPG_CLK_ARM (0x6)
1492#define CCM_COSR_CLKOSEL_SPL_DPDGCK_CLK (0x7)
1493#define CCM_COSR_CLKOSEL_CKIH (0x8)
1494#define CCM_COSR_CLKOSEL_IPG_CLK_AHB_EMI_CLK (0x9)
1495#define CCM_COSR_CLKOSEL_IPG_CLK_IPU_HSP (0x9)
1496#define CCM_COSR_CLKOSEL_IPG_CLK_NFC_20M (0xa)
1497#define CCM_COSR_CLKOSEL_IPG_CLK_PERCLK_UART1 (0xb)
1498#define CCM_COSR_CLKOSEL_IPG_REF_CIR1 (0xc) /* ref_cir_gateload */
1499#define CCM_COSR_CLKOSEL_IPG_REF_CIR2 (0xc) /* ref_cir_intrcload */
1500#define CCM_COSR_CLKOSEL_IPG_REF_CIR3 (0xc) /* ref_cir_path */
1501
1502/* CGR0 */
1503/* CGR1 */
1504/* CGR2 */
1505/* Handled in ccm-imx31.h and ccm-imx31.c */
1506
1507
1413#define CCM_WIMR0_GPIO3 (1 << 0) 1508#define CCM_WIMR0_GPIO3 (1 << 0)
1414#define CCM_WIMR0_GPIO2 (1 << 1) 1509#define CCM_WIMR0_GPIO2 (1 << 1)
1415#define CCM_WIMR0_GPIO1 (1 << 2) 1510#define CCM_WIMR0_GPIO1 (1 << 2)
@@ -1443,6 +1538,114 @@
1443#define CCM_WIMR0_RESERVED30 (1 << 30) 1538#define CCM_WIMR0_RESERVED30 (1 << 30)
1444#define CCM_WIMR0_RESERVED31 (1 << 31) 1539#define CCM_WIMR0_RESERVED31 (1 << 31)
1445 1540
1541/* LDC */
1542/* 32 bits specify value */
1543
1544/* DCVR0-DCVR3 */
1545#define CCM_DCVR_ULV (0x3ff << 22) /* Upper limit */
1546#define CCM_DCVR_ULV_POS (22)
1547#define CCM_DCVR_LLV (0x3ff << 12) /* Lower limit */
1548#define CCM_DCVR_LLV_POS (12)
1549#define CCM_DCVR_ELV (0x3ff << 2) /* Emergency limit */
1550#define CCM_DCVR_ELV_POS (2)
1551
1552#if 0
1553enum DVFS_W_SIGS
1554{
1555 DVFS_W_SIGS_M3IF_M0_BUF = 0, /* Hready signal of M3IF's master #0
1556 (L2 Cache) */
1557 DVFS_W_SIGS_M3IF_M1 = 1, /* Hready signal of M3IF's master #1
1558 (L2 Cache) */
1559 DVFS_W_SIGS_MBX_MBXCLKGATE = 2, /* Hready signal of M3IF's master #2
1560 (MBX) */
1561 DVFS_W_SIGS_M3IF_M3 = 3, /* Hready signal of M3IF's master #3
1562 (MAX) */
1563 DVFS_W_SIGS_M3IF_M4 = 4, /* Hready signal of M3IF's master #4
1564 (SDMA) */
1565 DVFS_W_SIGS_M3IF_M5 = 5, /* Hready signal of M3IF's master #5
1566 (mpeg4_vga_encoder) */
1567 DVFS_W_SIGS_M3IF_M6 = 6, /* Hready signal of M3IF's master #6
1568 (IPU) */
1569 DVFS_W_SIGS_M3IF_M7 = 7, /* Hready signal of M3IF's master #7
1570 (IPU) */
1571 DVFS_W_SIGS_ARM11_P_IRQ_B_RBT_GATE = 8, /* ARM normal interrupt */
1572 DVFS_W_SIGS_ARM11_P_FIQ_B_RBT_GATE = 9, /* ARM fast interrupt */
1573 DVFS_W_SIGS_IPI_GPIO1_INT0 = 10, /* Interrupt line from GPIO */
1574 DVFS_W_SIGS_IPI_INT_IPU_FUNC = 11, /* Interrupt line from IPU */
1575 DVFS_W_SIGS_DVGP0 = 12, /* Software-controllable general-purpose
1576 bits from the CCM */
1577 DVFS_W_SIGS_DVGP1 = 13, /* Software-controllable general-purpose
1578 bits from the CCM */
1579 DVFS_W_SIGS_DVGP2 = 14, /* Software-controllable general-purpose
1580 bits from the CCM */
1581 DVFS_W_SIGS_DVGP3 = 15, /* Software-controllable general-purpose
1582 bits from the CCM */
1583};
1584#endif
1585
1586/* LTR0 */
1587#define CCM_LTR0_UPTHR (0x3f << 22)
1588#define CCM_LTR0_UPTHR_POS (22)
1589#define CCM_LTR0_DNTHR (0x3f << 16)
1590#define CCM_LTR0_DNTHR_POS (16)
1591/* for div_3_clk */
1592#define CCM_LTR0_DIV3CK (0x3 << 1)
1593#define CCM_LTR0_DIV3CK_POS (1)
1594#define CCM_LTR0_DIV3CK_2048 (0x0 << 1) /* 1/2048 ARM clock */
1595#define CCM_LTR0_DIV3CK_8192 (0x1 << 1) /* 1/8192 ARM clock */
1596#define CCM_LTR0_DIV3CK_32768 (0x2 << 1) /* 1/32768 ARM clock */
1597#define CCM_LTR0_DIV3CK_131072 (0x3 << 1) /* 1/131072 ARM clock */
1598
1599/* PMCR0 */
1600#define CCM_PMCR0_DVSUP_MCUPLL (1 << 31)
1601#define CCM_PMCR0_DVSUP_POST_DIVIDERS (1 << 30)
1602#define CCM_PMCR0_DVSUP_DVS (0x3 << 28)
1603#define CCM_PMCR0_DVS1_0_DVS0_0 (0x0 << 28) /* Highest frequency/voltage */
1604#define CCM_PMCR0_DVS1_0_DVS0_1 (0x1 << 28) /* ... */
1605#define CCM_PMCR0_DVS1_1_DVS0_0 (0x2 << 28) /* ... */
1606#define CCM_PMCR0_DVS1_1_DVS0_1 (0x3 << 28) /* Lowest frequency/voltage */
1607#define CCM_PMCR0_DVS_POS (28)
1608#define CCM_PMCR0_UDSC (1 << 27)
1609#define CCM_PMCR0_VSCNT (0x7 << 24)
1610#define CCM_PMCR0_VSCNT_POS (24)
1611#define CCM_PMCR0_DVFEV (1 << 23)
1612#define CCM_PMCR0_DVFIS (1 << 22)
1613#define CCM_PMCR0_LBMI (1 << 21)
1614#define CCM_PMCR0_LBFL (1 << 20)
1615#define CCM_PMCR0_LBCF (0x3 << 18)
1616#define CCM_PMCR0_LBCF_4 (0x0 << 18)
1617#define CCM_PMCR0_LBCF_8 (0x1 << 18)
1618#define CCM_PMCR0_LBCF_12 (0x2 << 18)
1619#define CCM_PMCR0_LBCF_16 (0x3 << 18)
1620#define CCM_PMCR0_PTVIS (1 << 17)
1621#define CCM_PMCR0_UPDTEN (1 << 16)
1622#define CCM_PMCR0_FSVAIM (1 << 15)
1623#define CCM_PMCR0_FSVAI (0x3 << 13)
1624#define CCM_PMCR0_FSVAI_NO_INT (0x0 << 13)
1625#define CCM_PMCR0_FSVAI_INCREASE (0x1 << 13)
1626#define CCM_PMCR0_FSVAI_DECREASE (0x2 << 13)
1627#define CCM_PMCR0_FSVAI_INCREASE_NOW (0x3 << 13)
1628#define CCM_PMCR0_FSVAI_POS (13)
1629#define CCM_PMCR0_DPVCR (1 << 12)
1630#define CCM_PMCR0_DPVV (1 << 11)
1631#define CCM_PMCR0_WFIM (1 << 10)
1632#define CCM_PMCR0_DRCE3 (1 << 9)
1633#define CCM_PMCR0_DRCE2 (1 << 8)
1634#define CCM_PMCR0_DRCE1 (1 << 7)
1635#define CCM_PMCR0_DRCE0 (1 << 6)
1636#define CCM_PMCR0_DCR (1 << 5) /* 512 vs 256 count */
1637#define CCM_PMCR0_DVFEN (1 << 4)
1638#define CCM_PMCR0_PTVAIM (1 << 3)
1639#define CCM_PMCR0_PTVAI (0x3 << 1)
1640#define CCM_PMCR0_PTVAI_NO_INT (0x0 << 1)
1641#define CCM_PMCR0_PTVAI_DECREASE (0x1 << 1)
1642#define CCM_PMCR0_PTVAI_INCREASE (0x2 << 1)
1643#define CCM_PMCR0_PTVAI_INCREASE_NOW (0x3 << 1)
1644#define CCM_PMCR0_DPTEN (1 << 0)
1645
1646
1647
1648
1446/* WEIM - CS0 */ 1649/* WEIM - CS0 */
1447#define CSCRU 0x00 1650#define CSCRU 0x00
1448#define CSCRL 0x04 1651#define CSCRL 0x04