summaryrefslogtreecommitdiff
path: root/firmware/export/imx31l.h
diff options
context:
space:
mode:
Diffstat (limited to 'firmware/export/imx31l.h')
-rwxr-xr-xfirmware/export/imx31l.h11
1 files changed, 9 insertions, 2 deletions
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h
index c9ef446e90..e31f30f1b0 100755
--- a/firmware/export/imx31l.h
+++ b/firmware/export/imx31l.h
@@ -28,12 +28,14 @@
28#define REG32_PTR_T volatile unsigned long * 28#define REG32_PTR_T volatile unsigned long *
29 29
30/* Place in the section with the framebuffer */ 30/* Place in the section with the framebuffer */
31#define TTB_BASE_ADDR (0x80100000 + 0x00100000 - TTB_SIZE) 31#define TTB_BASE_ADDR (CSD0_BASE_ADDR + (MEM*0x100000) - TTB_SIZE)
32#define TTB_SIZE (0x4000) 32#define TTB_SIZE (0x4000)
33#define IRAM_SIZE (0x4000) 33#define IRAM_SIZE (0x4000)
34#define TTB_BASE ((unsigned long *)TTB_BASE_ADDR) 34#define TTB_BASE ((unsigned long *)TTB_BASE_ADDR)
35#define FRAME ((void*)0x03f00000)
36#define FRAME_SIZE (240*320*2) 35#define FRAME_SIZE (240*320*2)
36/* Rockbox framebuffer address, not retail OS */
37#define FRAME_PHYS_ADDR (TTB_BASE_ADDR - FRAME_SIZE)
38#define FRAME ((void *)(FRAME_PHYS_ADDR-CSD0_BASE_ADDR))
37 39
38#define DEVBSS_ATTR __attribute__((section(".devbss"),nocommon)) 40#define DEVBSS_ATTR __attribute__((section(".devbss"),nocommon))
39/* USBOTG */ 41/* USBOTG */
@@ -411,6 +413,11 @@
411#define IPU_BRK_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x54)) 413#define IPU_BRK_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x54))
412#define IPU_BRK_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x58)) 414#define IPU_BRK_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x58))
413#define IPU_DIAGB_CTRL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x60)) 415#define IPU_DIAGB_CTRL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x60))
416#define IPU_IDMAC_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xA4))
417#define IPU_IDMAC_CHA_EN (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xA8))
418#define IPU_IDMAC_CHA_PRI (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xAC))
419#define IPU_IDMAC_CHA_BUSY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xB0))
420
414 421
415 422
416/* ATA */ 423/* ATA */