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author | Michael Sevakis <jethead71@rockbox.org> | 2009-02-07 10:09:13 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2009-02-07 10:09:13 +0000 |
commit | 4d3a020f274d49c2b8f10cfdad8c67aaa153bebe (patch) | |
tree | ec04c17d0579a27f6e1f8b2085d5996e6e59f430 /firmware/export/imx31l.h | |
parent | f747d9d39e48c8bbf938220427584c4d8bf41b4c (diff) | |
download | rockbox-4d3a020f274d49c2b8f10cfdad8c67aaa153bebe.tar.gz rockbox-4d3a020f274d49c2b8f10cfdad8c67aaa153bebe.zip |
Gigabeat S: Move the LCD framebuffer address so that DRAM can be mapped flat between physical and virtual addresses. NO BOOTLOADER UPDATE SHOULD BE NEEDED. The firmware image now handles low-level system setup as well.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19935 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export/imx31l.h')
-rwxr-xr-x | firmware/export/imx31l.h | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h index c9ef446e90..e31f30f1b0 100755 --- a/firmware/export/imx31l.h +++ b/firmware/export/imx31l.h | |||
@@ -28,12 +28,14 @@ | |||
28 | #define REG32_PTR_T volatile unsigned long * | 28 | #define REG32_PTR_T volatile unsigned long * |
29 | 29 | ||
30 | /* Place in the section with the framebuffer */ | 30 | /* Place in the section with the framebuffer */ |
31 | #define TTB_BASE_ADDR (0x80100000 + 0x00100000 - TTB_SIZE) | 31 | #define TTB_BASE_ADDR (CSD0_BASE_ADDR + (MEM*0x100000) - TTB_SIZE) |
32 | #define TTB_SIZE (0x4000) | 32 | #define TTB_SIZE (0x4000) |
33 | #define IRAM_SIZE (0x4000) | 33 | #define IRAM_SIZE (0x4000) |
34 | #define TTB_BASE ((unsigned long *)TTB_BASE_ADDR) | 34 | #define TTB_BASE ((unsigned long *)TTB_BASE_ADDR) |
35 | #define FRAME ((void*)0x03f00000) | ||
36 | #define FRAME_SIZE (240*320*2) | 35 | #define FRAME_SIZE (240*320*2) |
36 | /* Rockbox framebuffer address, not retail OS */ | ||
37 | #define FRAME_PHYS_ADDR (TTB_BASE_ADDR - FRAME_SIZE) | ||
38 | #define FRAME ((void *)(FRAME_PHYS_ADDR-CSD0_BASE_ADDR)) | ||
37 | 39 | ||
38 | #define DEVBSS_ATTR __attribute__((section(".devbss"),nocommon)) | 40 | #define DEVBSS_ATTR __attribute__((section(".devbss"),nocommon)) |
39 | /* USBOTG */ | 41 | /* USBOTG */ |
@@ -411,6 +413,11 @@ | |||
411 | #define IPU_BRK_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x54)) | 413 | #define IPU_BRK_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x54)) |
412 | #define IPU_BRK_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x58)) | 414 | #define IPU_BRK_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x58)) |
413 | #define IPU_DIAGB_CTRL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x60)) | 415 | #define IPU_DIAGB_CTRL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x60)) |
416 | #define IPU_IDMAC_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xA4)) | ||
417 | #define IPU_IDMAC_CHA_EN (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xA8)) | ||
418 | #define IPU_IDMAC_CHA_PRI (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xAC)) | ||
419 | #define IPU_IDMAC_CHA_BUSY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xB0)) | ||
420 | |||
414 | 421 | ||
415 | 422 | ||
416 | /* ATA */ | 423 | /* ATA */ |