summaryrefslogtreecommitdiff
path: root/firmware/export/imx31l.h
diff options
context:
space:
mode:
Diffstat (limited to 'firmware/export/imx31l.h')
-rwxr-xr-xfirmware/export/imx31l.h584
1 files changed, 311 insertions, 273 deletions
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h
index 2bcb3492f9..4cc51e9bc6 100755
--- a/firmware/export/imx31l.h
+++ b/firmware/export/imx31l.h
@@ -19,16 +19,21 @@
19 19
20/* Most(if not all) of these defines are copied from Nand-Boot v4 provided w/ the Imx31 Linux Bsp*/ 20/* Most(if not all) of these defines are copied from Nand-Boot v4 provided w/ the Imx31 Linux Bsp*/
21 21
22#define REG8_PTR_T volatile unsigned char *
23#define REG16_PTR_T volatile unsigned short *
24#define REG32_PTR_T volatile unsigned long *
25
26#define TTB_BASE_ADDR (0x80000000 + (64*1024*1024)-TTB_SIZE)
27#define IRAM_BASE_ADDR 0x1fffc000
22#define L2CC_BASE_ADDR 0x30000000 28#define L2CC_BASE_ADDR 0x30000000
23 29
24/*Frame Buffer and TTB defines from gigabeat f/x build*/ 30/*Frame Buffer and TTB defines from gigabeat f/x build*/
25#define LCDSADDR1 (*(volatile int *)0x80100000) /* STN/TFT: frame buffer start address 1 */ 31#define FRAME ((short *)0x80100000) /* Framebuffer */
26#define FRAME1 ((short *)0x80100000) //Foreground FB
27#define FRAME2 ((short *)0x84100000) //Background FB - Set to Graphic Window, hence the reason why text is only visible
28 //when background memory is written.
29#define LCD_BUFFER_SIZE ((320*240*2)) 32#define LCD_BUFFER_SIZE ((320*240*2))
30#define TTB_SIZE (0x4000) 33#define TTB_SIZE (0x4000)
31#define TTB_BASE ((unsigned int *)(0x88000000 + (64*1024*1024)-TTB_SIZE)) 34#define TTB_BASE ((unsigned int *)TTB_BASE_ADDR)
35#define FRAME1 ALIGN_DOWN((TTB_BASE - LCD_BUFFER_SIZE), 32)
36#define FRAME2 ALIGN_DOWN((TTB_BASE - LCD_BUFFER_SIZE), 32)
32/* 37/*
33 * AIPS 1 38 * AIPS 1
34 */ 39 */
@@ -97,136 +102,126 @@
97#define PWM_BASE_ADDR 0x53FE0000 102#define PWM_BASE_ADDR 0x53FE0000
98#define RTIC_BASE_ADDR 0x53FEC000 103#define RTIC_BASE_ADDR 0x53FEC000
99 104
100#define WDOG1_BASE_ADDR WDOG_BASE_ADDR 105#define WDOG1_BASE_ADDR WDOG_BASE_ADDR
101#define CRM_MCU_BASE_ADDR CCM_BASE_ADDR 106#define CRM_MCU_BASE_ADDR CCM_BASE_ADDR
107
108/* IPU */
109#define IPU_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x00))
110#define IPU_CHA_BUF0_RDY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x04))
111#define IPU_CHA_BUF1_RDY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x08))
112#define IPU_CHA_DB_MODE_SEL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0C))
113#define IPU_CHA_CUR_BUF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x10))
114#define IPU_FS_PROC_FLOW (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x14))
115#define IPU_FS_DISP_FLOW (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x18))
116#define IPU_TASKS_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1C))
117#define IPU_IMA_ADDR (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x20))
118#define IPU_IMA_DATA (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x24))
119#define IPU_INT_CTRL_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x28))
120#define IPU_INT_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x2C))
121#define IPU_INT_CTRL_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x30))
122#define IPU_INT_CTRL_4 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x34))
123#define IPU_INT_CTRL_5 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x38))
124#define IPU_INT_STAT_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x3C))
125#define IPU_INT_STAT_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x40))
126#define IPU_INT_STAT_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x44))
127#define IPU_INT_STAT_4 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x48))
128#define IPU_INT_STAT_5 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x4C))
129#define IPU_BRK_CTRL_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x50))
130#define IPU_BRK_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x54))
131#define IPU_BRK_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x58))
132#define IPU_DIAGB_CTRL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x60))
133
102 134
103/* ATA */ 135/* ATA */
104#define TIME_OFF (*(volatile unsigned char*)0x43F8C000) 136#define TIME_OFF (*(REG8_PTR_T)0x43F8C000)
105#define TIME_ON (*(volatile unsigned char*)0x43F8C001) 137#define TIME_ON (*(REG8_PTR_T)0x43F8C001)
106#define TIME_1 (*(volatile unsigned char*)0x43F8C002) 138#define TIME_1 (*(REG8_PTR_T)0x43F8C002)
107#define TIME_2W (*(volatile unsigned char*)0x43F8C003) 139#define TIME_2W (*(REG8_PTR_T)0x43F8C003)
108#define TIME_2R (*(volatile unsigned char*)0x43F8C004) 140#define TIME_2R (*(REG8_PTR_T)0x43F8C004)
109#define TIME_AX (*(volatile unsigned char*)0x43F8C005) 141#define TIME_AX (*(REG8_PTR_T)0x43F8C005)
110#define TIME_PIO_RDX (*(volatile unsigned char*)0x43F8C00F) 142#define TIME_PIO_RDX (*(REG8_PTR_T)0x43F8C00F)
111#define TIME_4 (*(volatile unsigned char*)0x43F8C007) 143#define TIME_4 (*(REG8_PTR_T)0x43F8C007)
112#define TIME_9 (*(volatile unsigned char*)0x43F8C008) 144#define TIME_9 (*(REG8_PTR_T)0x43F8C008)
113 145
114/* Timers */ 146/* Timers */
115#define EPITCR1 (*(volatile long*)EPIT1_BASE_ADDR) 147#define EPITCR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x00))
116#define EPITSR1 (*(volatile long*)(EPIT1_BASE_ADDR+0x04)) 148#define EPITSR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x04))
117#define EPITLR1 (*(volatile long*)(EPIT1_BASE_ADDR+0x08)) 149#define EPITLR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x08))
118#define EPITCMPR1 (*(volatile long*)(EPIT1_BASE_ADDR+0x0C)) 150#define EPITCMPR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x0C))
119#define EPITCNT1 (*(volatile long*)(EPIT1_BASE_ADDR+0x10)) 151#define EPITCNT1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x10))
120#define EPITCR2 (*(volatile long*)EPIT2_BASE_ADDR) 152#define EPITCR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x00))
121#define EPITSR2 (*(volatile long*)(EPIT2_BASE_ADDR+0x04)) 153#define EPITSR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x04))
122#define EPITLR2 (*(volatile long*)(EPIT2_BASE_ADDR+0x08)) 154#define EPITLR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x08))
123#define EPITCMPR2 (*(volatile long*)(EPIT2_BASE_ADDR+0x0C)) 155#define EPITCMPR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x0C))
124#define EPITCNT2 (*(volatile long*)(EPIT2_BASE_ADDR+0x10)) 156#define EPITCNT2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x10))
125 157
126/* GPIO */ 158/* GPIO */
127#define GPIO1_DR (*(volatile long*)GPIO1_BASE_ADDR) 159#define GPIO1_DR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x00))
128#define GPIO1_GDIR (*(volatile long*)(GPIO1_BASE_ADDR+0x04)) 160#define GPIO1_GDIR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x04))
129#define GPIO1_PSR (*(volatile long*)(GPIO1_BASE_ADDR+0x08)) 161#define GPIO1_PSR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x08))
130#define GPIO1_ICR1 (*(volatile long*)(GPIO1_BASE_ADDR+0x0C)) 162#define GPIO1_ICR1 (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x0C))
131#define GPIO1_ICR2 (*(volatile long*)(GPIO1_BASE_ADDR+0x10)) 163#define GPIO1_ICR2 (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x10))
132#define GPIO1_IMR (*(volatile long*)(GPIO1_BASE_ADDR+0x14)) 164#define GPIO1_IMR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x14))
133#define GPIO1_ISR (*(volatile long*)(GPIO1_BASE_ADDR+0x18)) 165#define GPIO1_ISR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x18))
134 166
135#define GPIO2_DR (*(volatile long*)GPIO2_BASE_ADDR) 167#define GPIO2_DR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x00))
136#define GPIO2_GDIR (*(volatile long*)(GPIO2_BASE_ADDR+0x04)) 168#define GPIO2_GDIR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x04))
137#define GPIO2_PSR (*(volatile long*)(GPIO2_BASE_ADDR+0x08)) 169#define GPIO2_PSR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x08))
138#define GPIO2_ICR1 (*(volatile long*)(GPIO2_BASE_ADDR+0x0C)) 170#define GPIO2_ICR1 (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x0C))
139#define GPIO2_ICR2 (*(volatile long*)(GPIO2_BASE_ADDR+0x10)) 171#define GPIO2_ICR2 (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x10))
140#define GPIO2_IMR (*(volatile long*)(GPIO2_BASE_ADDR+0x14)) 172#define GPIO2_IMR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x14))
141#define GPIO2_ISR (*(volatile long*)(GPIO2_BASE_ADDR+0x18)) 173#define GPIO2_ISR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x18))
142 174
143#define GPIO3_DR (*(volatile long*)GPIO3_BASE_ADDR) 175#define GPIO3_DR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x00))
144#define GPIO3_GDIR (*(volatile long*)(GPIO3_BASE_ADDR+0x04)) 176#define GPIO3_GDIR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x04))
145#define GPIO3_PSR (*(volatile long*)(GPIO3_BASE_ADDR+0x08)) 177#define GPIO3_PSR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x08))
146#define GPIO3_ICR1 (*(volatile long*)(GPIO3_BASE_ADDR+0x0C)) 178#define GPIO3_ICR1 (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x0C))
147#define GPIO3_ICR2 (*(volatile long*)(GPIO3_BASE_ADDR+0x10)) 179#define GPIO3_ICR2 (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x10))
148#define GPIO3_IMR (*(volatile long*)(GPIO3_BASE_ADDR+0x14)) 180#define GPIO3_IMR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x14))
149#define GPIO3_ISR (*(volatile long*)(GPIO3_BASE_ADDR+0x18)) 181#define GPIO3_ISR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x18))
150 182
151/* SPI */ 183/* SPI */
152#define CSPI_RXDATA1 (*(volatile long*)CSPI1_BASE_ADDR) 184#define CSPI_RXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x00))
153#define CSPI_TXDATA1 (*(volatile long*)(CSPI1_BASE_ADDR+0x04)) 185#define CSPI_TXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x04))
154#define CSPI_CONREG1 (*(volatile long*)(CSPI1_BASE_ADDR+0x08)) 186#define CSPI_CONREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x08))
155#define CSPI_INTREG1 (*(volatile long*)(CSPI1_BASE_ADDR+0x0C)) 187#define CSPI_INTREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x0C))
156#define CSPI_DMAREG1 (*(volatile long*)(CSPI1_BASE_ADDR+0x10)) 188#define CSPI_DMAREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x10))
157#define CSPI_STATREG1 (*(volatile long*)(CSPI1_BASE_ADDR+0x14)) 189#define CSPI_STATREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x14))
158#define CSPI_PERIODREG1 (*(volatile long*)(CSPI1_BASE_ADDR+0x18)) 190#define CSPI_PERIODREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x18))
159#define CSPI_TESTREG1 (*(volatile long*)(CSPI1_BASE_ADDR+0x1C0)) 191#define CSPI_TESTREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x1C0))
160 192
161#define CSPI_RXDATA2 (*(volatile long*)CSPI2_BASE_ADDR) 193#define CSPI_RXDATA2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x00))
162#define CSPI_TXDATA2 (*(volatile long*)(CSPI2_BASE_ADDR+0x04)) 194#define CSPI_TXDATA2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x04))
163#define CSPI_CONREG2 (*(volatile long*)(CSPI2_BASE_ADDR+0x08)) 195#define CSPI_CONREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x08))
164#define CSPI_INTREG2 (*(volatile long*)(CSPI2_BASE_ADDR+0x0C)) 196#define CSPI_INTREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x0C))
165#define CSPI_DMAREG2 (*(volatile long*)(CSPI2_BASE_ADDR+0x10)) 197#define CSPI_DMAREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x10))
166#define CSPI_STATREG2 (*(volatile long*)(CSPI2_BASE_ADDR+0x14)) 198#define CSPI_STATREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x14))
167#define CSPI_PERIODREG2 (*(volatile long*)(CSPI2_BASE_ADDR+0x18)) 199#define CSPI_PERIODREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x18))
168#define CSPI_TESTREG2 (*(volatile long*)(CSPI2_BASE_ADDR+0x1C0)) 200#define CSPI_TESTREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x1C0))
169 201
170/* RTC */ 202/* RTC */
171#define RTC_HOURMIN (*(volatile long*)RTC_BASE_ADDR) 203#define RTC_HOURMIN (*(REG32_PTR_T)(RTC_BASE_ADDR+0x00))
172#define RTC_SECONDS (*(volatile long*)(RTC_BASE_ADDR+0x04)) 204#define RTC_SECONDS (*(REG32_PTR_T)(RTC_BASE_ADDR+0x04))
173#define RTC_ALRM_HM (*(volatile long*)(RTC_BASE_ADDR+0x08)) 205#define RTC_ALRM_HM (*(REG32_PTR_T)(RTC_BASE_ADDR+0x08))
174#define RTC_ALRM_SEC (*(volatile long*)(RTC_BASE_ADDR+0x0C)) 206#define RTC_ALRM_SEC (*(REG32_PTR_T)(RTC_BASE_ADDR+0x0C))
175#define RTC_CTL (*(volatile long*)(RTC_BASE_ADDR+0x10)) 207#define RTC_CTL (*(REG32_PTR_T)(RTC_BASE_ADDR+0x10))
176#define RTC_ISR (*(volatile long*)(RTC_BASE_ADDR+0x14)) 208#define RTC_ISR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x14))
177#define RTC_IENR (*(volatile long*)(RTC_BASE_ADDR+0x18)) 209#define RTC_IENR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x18))
178#define RTC_STPWCH (*(volatile long*)(RTC_BASE_ADDR+0x1C)) 210#define RTC_STPWCH (*(REG32_PTR_T)(RTC_BASE_ADDR+0x1C))
179#define RTC_DAYR (*(volatile long*)(RTC_BASE_ADDR+0x20)) 211#define RTC_DAYR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x20))
180#define RTC_DAYALARM (*(volatile long*)(RTC_BASE_ADDR+0x24)) 212#define RTC_DAYALARM (*(REG32_PTR_T)(RTC_BASE_ADDR+0x24))
181 213
182/* Keypad */ 214/* Keypad */
183#define KPP_KPCR (*(volatile short*)KPP_BASE_ADDR) 215#define KPP_KPCR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x0))
184#define KPP_KPSR (*(volatile short*)(KPP_BASE_ADDR+0x2)) 216#define KPP_KPSR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x2))
185#define KPP_KDDR (*(volatile short*)(KPP_BASE_ADDR+0x4)) 217#define KPP_KDDR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x4))
186#define KPP_KPDR (*(volatile short*)(KPP_BASE_ADDR+0x6)) 218#define KPP_KPDR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x6))
187 219
188/* ROMPATCH and AVIC */ 220/* ROMPATCH and AVIC */
189#define ROMPATCH_BASE_ADDR 0x60000000 221#define ROMPATCH_BASE_ADDR 0x60000000
190#define AVIC_BASE_ADDR 0x68000000
191
192#define INTCNTL (*(volatile long*)AVIC_BASE_ADDR)
193#define NIMASK (*(volatile long*)(AVIC_BASE_ADDR+0x004))
194#define INTENNUM (*(volatile long*)(AVIC_BASE_ADDR+0x008))
195#define INTDISNUM (*(volatile long*)(AVIC_BASE_ADDR+0x00C))
196#define INTENABLEH (*(volatile long*)(AVIC_BASE_ADDR+0x010))
197#define INTENABLEL (*(volatile long*)(AVIC_BASE_ADDR+0x014))
198#define INTTYPEH (*(volatile long*)(AVIC_BASE_ADDR+0x018))
199#define INTTYPEL (*(volatile long*)(AVIC_BASE_ADDR+0x01C))
200#define NIPRIORITY7 (*(volatile long*)(AVIC_BASE_ADDR+0x020))
201#define NIPRIORITY6 (*(volatile long*)(AVIC_BASE_ADDR+0x024))
202#define NIPRIORITY5 (*(volatile long*)(AVIC_BASE_ADDR+0x028))
203#define NIPRIORITY4 (*(volatile long*)(AVIC_BASE_ADDR+0x02C))
204#define NIPRIORITY3 (*(volatile long*)(AVIC_BASE_ADDR+0x030))
205#define NIPRIORITY2 (*(volatile long*)(AVIC_BASE_ADDR+0x034))
206#define NIPRIORITY1 (*(volatile long*)(AVIC_BASE_ADDR+0x038))
207#define NIPRIORITY0 (*(volatile long*)(AVIC_BASE_ADDR+0x03C))
208#define NIVECSR (*(volatile long*)(AVIC_BASE_ADDR+0x040))
209#define FIVECSR (*(volatile long*)(AVIC_BASE_ADDR+0x044))
210#define INTSRCH (*(volatile long*)(AVIC_BASE_ADDR+0x048))
211#define INTSRCL (*(volatile long*)(AVIC_BASE_ADDR+0x04C))
212#define INTFRCH (*(volatile long*)(AVIC_BASE_ADDR+0x050))
213#define INTFRCL (*(volatile long*)(AVIC_BASE_ADDR+0x054))
214#define NIPNDH (*(volatile long*)(AVIC_BASE_ADDR+0x058))
215#define NIPNDL (*(volatile long*)(AVIC_BASE_ADDR+0x05C))
216#define FIPNDH (*(volatile long*)(AVIC_BASE_ADDR+0x060))
217#define FIPNDL (*(volatile long*)(AVIC_BASE_ADDR+0x064))
218 222
219/* The vectors go all the way up to 63. 4 bytes for each */
220#define VECTOR_BASE_ADDR AVIC_BASE_ADDR+0x100
221#define VECTOR0 (*(volatile long*)VECTOR_BASE_ADDR)
222
223#define NIDIS (1 << 22)
224#define FIDIS (1 << 21)
225
226/* Since AVIC vector registers are NOT used, we reserve some for various 223/* Since AVIC vector registers are NOT used, we reserve some for various
227 * purposes. Copied from Linux source code. */ 224 * purposes. Copied from Linux source code. */
228#define AVIC_VEC_0 0x100 /* For WFI workaround used by Linux kernel */
229#define AVIC_VEC_1 0x104 /* For system revision used by Linux kernel */
230#define CHIP_REV_1_0 0x10 225#define CHIP_REV_1_0 0x10
231#define CHIP_REV_2_0 0x20 226#define CHIP_REV_2_0 0x20
232#define SYSTEM_REV_ID_REG (AVIC_BASE_ADDR + AVIC_VEC_1) 227#define SYSTEM_REV_ID_REG (AVIC_BASE_ADDR + AVIC_VEC_1)
@@ -239,11 +234,11 @@
239#define NFC_BASE EXT_MEM_CTRL_BASE 234#define NFC_BASE EXT_MEM_CTRL_BASE
240#define ESDCTL_BASE 0xB8001000 235#define ESDCTL_BASE 0xB8001000
241#define WEIM_BASE_ADDR 0xB8002000 236#define WEIM_BASE_ADDR 0xB8002000
242#define WEIM_CTRL_CS0 WEIM_BASE_ADDR 237#define WEIM_CTRL_CS0 (WEIM_BASE_ADDR+0x00)
243#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10) 238#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR+0x10)
244#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20) 239#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR+0x20)
245#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30) 240#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR+0x30)
246#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40) 241#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR+0x40)
247#define M3IF_BASE 0xB8003000 242#define M3IF_BASE 0xB8003000
248#define PCMCIA_CTL_BASE 0xB8004000 243#define PCMCIA_CTL_BASE 0xB8004000
249 244
@@ -264,15 +259,52 @@
264 259
265#define INTERNAL_ROM_VA 0xF0000000 260#define INTERNAL_ROM_VA 0xF0000000
266 261
267// SDRAM 262/*
263 * SDRAM
264 */
268#define RAM_BANK0_BASE SDRAM_BASE_ADDR 265#define RAM_BANK0_BASE SDRAM_BASE_ADDR
269 266
270/* 267/*
271 * IRQ Controller Register Definitions. 268 * IRQ Controller Register Definitions.
272 */ 269 */
273#define AVIC_NIMASK REG32_PTR(AVIC_BASE_ADDR + (0x04)) 270#define AVIC_BASE_ADDR 0x68000000
274#define AVIC_INTTYPEH REG32_PTR(AVIC_BASE_ADDR + (0x18)) 271#define INTCNTL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x00))
275#define AVIC_INTTYPEL REG32_PTR(AVIC_BASE_ADDR + (0x1C)) 272#define NIMASK (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x04))
273#define INTENNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x08))
274#define INTDISNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x0C))
275#define INTENABLEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x10))
276#define INTENABLEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x14))
277#define INTTYPEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x18))
278#define INTTYPEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x1C))
279#define NIPRIORITY7 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x20))
280#define NIPRIORITY6 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x24))
281#define NIPRIORITY5 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x28))
282#define NIPRIORITY4 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x2C))
283#define NIPRIORITY3 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x30))
284#define NIPRIORITY2 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x34))
285#define NIPRIORITY1 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x38))
286#define NIPRIORITY0 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x3C))
287#define NIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x40))
288#define FIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x44))
289#define INTSRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x48))
290#define INTSRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x4C))
291#define INTFRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x50))
292#define INTFRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x54))
293#define NIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x58))
294#define NIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x5C))
295#define FIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x60))
296#define FIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x64))
297#define VECTOR_BASE_ADDR (AVIC_BASE_ADDR+0x100)
298#define VECTOR(n) (*(REG32_PTR_T)(VECTOR_BASE_ADDR+((n)*4)))
299
300/* The vectors go all the way up to 63. 4 bytes for each */
301#define INTCNTL_ABFLAG (1 << 25)
302#define INTCNTL_ABFEN (1 << 24)
303#define INTCNTL_NIDIS (1 << 22)
304#define INTCNTL_FIDIS (1 << 21)
305#define INTCNTL_NIAD (1 << 20)
306#define INTCNTL_FIAD (1 << 19)
307#define INTCNTL_NM (1 << 18)
276 308
277/* L210 */ 309/* L210 */
278#define L2CC_BASE_ADDR 0x30000000 310#define L2CC_BASE_ADDR 0x30000000
@@ -285,17 +317,23 @@
285#define L2_CACHE_CLEAN_LINE_REG 0x7B0 317#define L2_CACHE_CLEAN_LINE_REG 0x7B0
286#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0 318#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0
287 319
320#define L2CC_CACHE_SYNC (*(REG32_PTR_T)(L2CC_BASE_ADDR+L2_CACHE_SYNC_REG))
321
288/* CCM */ 322/* CCM */
289#define CLKCTL_CCMR (*(volatile long*)(CCM_BASE_ADDR+0x00)) 323#define CLKCTL_CCMR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x00))
290#define CLKCTL_PDR0 (*(volatile long*)(CCM_BASE_ADDR+0x04)) 324#define CLKCTL_PDR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x04))
291#define CLKCTL_PDR1 (*(volatile long*)(CCM_BASE_ADDR+0x08)) 325#define CLKCTL_PDR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x08))
292#define CLKCTL_PDR2 (*(volatile long*)(CCM_BASE_ADDR+0x64)) 326#define CLKCTL_PDR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64))
293#define CLKCTL_RCSR (*(volatile long*)(CCM_BASE_ADDR+0x0C)) 327#define CLKCTL_RCSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x0C))
294#define CLKCTL_MPCTL (*(volatile long*)(CCM_BASE_ADDR+0x10)) 328#define CLKCTL_MPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x10))
295#define CLKCTL_UPCTL (*(volatile long*)(CCM_BASE_ADDR+0x14)) 329#define CLKCTL_UPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x14))
296#define CLKCTL_SPCTL (*(volatile long*)(CCM_BASE_ADDR+0x18)) 330#define CLKCTL_SPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x18))
297#define CLKCTL_COSR (*(volatile long*)(CCM_BASE_ADDR+0x1C)) 331#define CLKCTL_COSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x1C))
298#define CLKCTL_PMCR0 (*(volatile long*)(CCM_BASE_ADDR+0x5C)) 332#define CLKCTL_CGR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x20))
333#define CLKCTL_CGR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x24))
334#define CLKCTL_CGR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x28))
335#define CLKCTL_WIMR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x2C))
336#define CLKCTL_PMCR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x5C))
299#define PLL_REF_CLK 26000000 337#define PLL_REF_CLK 26000000
300 338
301/* WEIM - CS0 */ 339/* WEIM - CS0 */
@@ -311,114 +349,114 @@
311#define ESDCTL_ESDMISC 0x10 349#define ESDCTL_ESDMISC 0x10
312 350
313/* More UART 1 Register defines */ 351/* More UART 1 Register defines */
314#define URXD1 (*(volatile int*)UART1_BASE_ADDR) 352#define URXD1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x00))
315#define UTXD1 (*(volatile int*)(UART1_BASE_ADDR+0x40)) 353#define UTXD1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x40))
316#define UCR1_1 (*(volatile int *)(UART1_BASE_ADDR+0x80)) 354#define UCR1_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x80))
317#define UCR2_1 (*(volatile int* )(UART1_BASE_ADDR+0x84)) 355#define UCR2_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x84))
318#define UCR3_1 (*(volatile int* )(UART1_BASE_ADDR+0x88)) 356#define UCR3_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x88))
319#define UCR4_1 (*(volatile int* )(UART1_BASE_ADDR+0x8C)) 357#define UCR4_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x8C))
320#define UFCR1 (*(volatile int *)(UART1_BASE_ADDR+ 0x90)) 358#define UFCR1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x90))
321#define USR1_1 (*(volatile int *)(UART1_BASE_ADDR+0x94)) 359#define USR1_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x94))
322#define USR2_1 (*(volatile int *)(UART1_BASE_ADDR+0x98)) 360#define USR2_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x98))
323#define UTS1 (*(volatile int *)(UART1_BASE_ADDR+0xB4)) 361#define UTS1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0xB4))
324 362
325/* 363/*
326 * UART Control Register 0 Bit Fields. 364 * UART Control Register 0 Bit Fields.
327 */ 365 */
328#define EUartUCR1_ADEN (1 << 15) // Auto detect interrupt 366#define EUartUCR1_ADEN (1 << 15) // Auto detect interrupt
329#define EUartUCR1_ADBR (1 << 14) // Auto detect baud rate 367#define EUartUCR1_ADBR (1 << 14) // Auto detect baud rate
330#define EUartUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable 368#define EUartUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable
331#define EUartUCR1_IDEN (1 << 12) // Idle condition interrupt 369#define EUartUCR1_IDEN (1 << 12) // Idle condition interrupt
332#define EUartUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable 370#define EUartUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable
333#define EUartUCR1_RDMAEN (1 << 8) // Recv ready DMA enable 371#define EUartUCR1_RDMAEN (1 << 8) // Recv ready DMA enable
334#define EUartUCR1_IREN (1 << 7) // Infrared interface enable 372#define EUartUCR1_IREN (1 << 7) // Infrared interface enable
335#define EUartUCR1_TXMPTYEN (1 << 6) // Transimitter empt interrupt enable 373#define EUartUCR1_TXMPTYEN (1 << 6) // Transimitter empt interrupt enable
336#define EUartUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable 374#define EUartUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable
337#define EUartUCR1_SNDBRK (1 << 4) // Send break 375#define EUartUCR1_SNDBRK (1 << 4) // Send break
338#define EUartUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable 376#define EUartUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable
339#define EUartUCR1_DOZE (1 << 1) // Doze 377#define EUartUCR1_DOZE (1 << 1) // Doze
340#define EUartUCR1_UARTEN (1 << 0) // UART enabled 378#define EUartUCR1_UARTEN (1 << 0) // UART enabled
341#define EUartUCR2_ESCI (1 << 15) // Escape seq interrupt enable 379#define EUartUCR2_ESCI (1 << 15) // Escape seq interrupt enable
342#define EUartUCR2_IRTS (1 << 14) // Ignore RTS pin 380#define EUartUCR2_IRTS (1 << 14) // Ignore RTS pin
343#define EUartUCR2_CTSC (1 << 13) // CTS pin control 381#define EUartUCR2_CTSC (1 << 13) // CTS pin control
344#define EUartUCR2_CTS (1 << 12) // Clear to send 382#define EUartUCR2_CTS (1 << 12) // Clear to send
345#define EUartUCR2_ESCEN (1 << 11) // Escape enable 383#define EUartUCR2_ESCEN (1 << 11) // Escape enable
346#define EUartUCR2_PREN (1 << 8) // Parity enable 384#define EUartUCR2_PREN (1 << 8) // Parity enable
347#define EUartUCR2_PROE (1 << 7) // Parity odd/even 385#define EUartUCR2_PROE (1 << 7) // Parity odd/even
348#define EUartUCR2_STPB (1 << 6) // Stop 386#define EUartUCR2_STPB (1 << 6) // Stop
349#define EUartUCR2_WS (1 << 5) // Word size 387#define EUartUCR2_WS (1 << 5) // Word size
350#define EUartUCR2_RTSEN (1 << 4) // Request to send interrupt enable 388#define EUartUCR2_RTSEN (1 << 4) // Request to send interrupt enable
351#define EUartUCR2_ATEN (1 << 3) // Aging timer enable 389#define EUartUCR2_ATEN (1 << 3) // Aging timer enable
352#define EUartUCR2_TXEN (1 << 2) // Transmitter enabled 390#define EUartUCR2_TXEN (1 << 2) // Transmitter enabled
353#define EUartUCR2_RXEN (1 << 1) // Receiver enabled 391#define EUartUCR2_RXEN (1 << 1) // Receiver enabled
354#define EUartUCR2_SRST_ (1 << 0) // SW reset 392#define EUartUCR2_SRST_ (1 << 0) // SW reset
355#define EUartUCR3_PARERREN (1 << 12) // Parity enable 393#define EUartUCR3_PARERREN (1 << 12) // Parity enable
356#define EUartUCR3_FRAERREN (1 << 11) // Frame error interrupt enable 394#define EUartUCR3_FRAERREN (1 << 11) // Frame error interrupt enable
357#define EUartUCR3_ADNIMP (1 << 7) // Autobaud detection not improved 395#define EUartUCR3_ADNIMP (1 << 7) // Autobaud detection not improved
358#define EUartUCR3_RXDSEN (1 << 6) // Receive status interrupt enable 396#define EUartUCR3_RXDSEN (1 << 6) // Receive status interrupt enable
359#define EUartUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable 397#define EUartUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable
360#define EUartUCR3_AWAKEN (1 << 4) // Async wake interrupt enable 398#define EUartUCR3_AWAKEN (1 << 4) // Async wake interrupt enable
361#define EUartUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected 399#define EUartUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected
362#define EUartUCR3_INVT (1 << 1) // Inverted Infrared transmission 400#define EUartUCR3_INVT (1 << 1) // Inverted Infrared transmission
363#define EUartUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable 401#define EUartUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable
364#define EUartUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars) 402#define EUartUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars)
365#define EUartUCR4_INVR (1 << 9) // Inverted infrared reception 403#define EUartUCR4_INVR (1 << 9) // Inverted infrared reception
366#define EUartUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable 404#define EUartUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable
367#define EUartUCR4_WKEN (1 << 7) // Wake interrupt enable 405#define EUartUCR4_WKEN (1 << 7) // Wake interrupt enable
368#define EUartUCR4_IRSC (1 << 5) // IR special case 406#define EUartUCR4_IRSC (1 << 5) // IR special case
369#define EUartUCR4_LPBYP (1 << 4) // Low power bypass 407#define EUartUCR4_LPBYP (1 << 4) // Low power bypass
370#define EUartUCR4_TCEN (1 << 3) // Transmit complete interrupt enable 408#define EUartUCR4_TCEN (1 << 3) // Transmit complete interrupt enable
371#define EUartUCR4_BKEN (1 << 2) // Break condition interrupt enable 409#define EUartUCR4_BKEN (1 << 2) // Break condition interrupt enable
372#define EUartUCR4_OREN (1 << 1) // Receiver overrun interrupt enable 410#define EUartUCR4_OREN (1 << 1) // Receiver overrun interrupt enable
373#define EUartUCR4_DREN (1 << 0) // Recv data ready interrupt enable 411#define EUartUCR4_DREN (1 << 0) // Recv data ready interrupt enable
374#define EUartUFCR_RXTL_SHF 0 // Receiver trigger level shift 412#define EUartUFCR_RXTL_SHF 0 // Receiver trigger level shift
375#define EUartUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div> 1) 413#define EUartUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div> 1)
376#define EUartUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div> 2) 414#define EUartUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div> 2)
377#define EUartUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3) 415#define EUartUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3)
378#define EUartUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4) 416#define EUartUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4)
379#define EUartUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5) 417#define EUartUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5)
380#define EUartUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6) 418#define EUartUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6)
381#define EUartUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7) 419#define EUartUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7)
382#define EUartUFCR_TXTL_SHF 10 // Transmitter trigger level shift 420#define EUartUFCR_TXTL_SHF 10 // Transmitter trigger level shift
383#define EUartUSR1_PARITYERR (1 << 15) // Parity error interrupt flag 421#define EUartUSR1_PARITYERR (1 << 15) // Parity error interrupt flag
384#define EUartUSR1_RTSS (1 << 14) // RTS pin status 422#define EUartUSR1_RTSS (1 << 14) // RTS pin status
385#define EUartUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag 423#define EUartUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag
386#define EUartUSR1_RTSD (1 << 12) // RTS delta 424#define EUartUSR1_RTSD (1 << 12) // RTS delta
387#define EUartUSR1_ESCF (1 << 11) // Escape seq interrupt flag 425#define EUartUSR1_ESCF (1 << 11) // Escape seq interrupt flag
388#define EUartUSR1_FRAMERR (1 << 10) // Frame error interrupt flag 426#define EUartUSR1_FRAMERR (1 << 10) // Frame error interrupt flag
389#define EUartUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag 427#define EUartUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag
390#define EUartUSR1_AGTIM (1 << 8) // Aging timeout interrupt status 428#define EUartUSR1_AGTIM (1 << 8) // Aging timeout interrupt status
391#define EUartUSR1_RXDS (1 << 6) // Receiver idle interrupt flag 429#define EUartUSR1_RXDS (1 << 6) // Receiver idle interrupt flag
392#define EUartUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag 430#define EUartUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag
393#define EUartUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag 431#define EUartUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag
394#define EUartUSR2_ADET (1 << 15) // Auto baud rate detect complete 432#define EUartUSR2_ADET (1 << 15) // Auto baud rate detect complete
395#define EUartUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty 433#define EUartUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty
396#define EUartUSR2_IDLE (1 << 12) // Idle condition 434#define EUartUSR2_IDLE (1 << 12) // Idle condition
397#define EUartUSR2_ACST (1 << 11) // Autobaud counter stopped 435#define EUartUSR2_ACST (1 << 11) // Autobaud counter stopped
398#define EUartUSR2_IRINT (1 << 8) // Serial infrared interrupt flag 436#define EUartUSR2_IRINT (1 << 8) // Serial infrared interrupt flag
399#define EUartUSR2_WAKE (1 << 7) // Wake 437#define EUartUSR2_WAKE (1 << 7) // Wake
400#define EUartUSR2_RTSF (1 << 4) // RTS edge interrupt flag 438#define EUartUSR2_RTSF (1 << 4) // RTS edge interrupt flag
401#define EUartUSR2_TXDC (1 << 3) // Transmitter complete 439#define EUartUSR2_TXDC (1 << 3) // Transmitter complete
402#define EUartUSR2_BRCD (1 << 2) // Break condition 440#define EUartUSR2_BRCD (1 << 2) // Break condition
403#define EUartUSR2_ORE (1 << 1) // Overrun error 441#define EUartUSR2_ORE (1 << 1) // Overrun error
404#define EUartUSR2_RDR (1 << 0) // Recv data ready 442#define EUartUSR2_RDR (1 << 0) // Recv data ready
405#define EUartUTS_FRCPERR (1 << 13) // Force parity error 443#define EUartUTS_FRCPERR (1 << 13) // Force parity error
406#define EUartUTS_LOOP (1 << 12) // Loop tx and rx 444#define EUartUTS_LOOP (1 << 12) // Loop tx and rx
407#define EUartUTS_TXEMPTY (1 << 6) // TxFIFO empty 445#define EUartUTS_TXEMPTY (1 << 6) // TxFIFO empty
408#define EUartUTS_RXEMPTY (1 << 5) // RxFIFO empty 446#define EUartUTS_RXEMPTY (1 << 5) // RxFIFO empty
409#define EUartUTS_TXFULL (1 << 4) // TxFIFO full 447#define EUartUTS_TXFULL (1 << 4) // TxFIFO full
410#define EUartUTS_RXFULL (1 << 3) // RxFIFO full 448#define EUartUTS_RXFULL (1 << 3) // RxFIFO full
411#define EUartUTS_SOFTRST (1 << 0) // Software reset 449#define EUartUTS_SOFTRST (1 << 0) // Software reset
412 450
413#define DelayTimerPresVal 3 451#define DelayTimerPresVal 3
414 452
415#define L2CC_ENABLED 453#define L2CC_ENABLED
416 454
417/* Assuming 26MHz input clock */ 455/* Assuming 26MHz input clock */
418/* PD MFD MFI MFN */ 456/* PD MFD MFI MFN */
419#define MPCTL_PARAM_208 ((1 << 26) + (0 << 16) + (8 << 10) + (0 << 0)) 457#define MPCTL_PARAM_208 ((1 << 26) + (0 << 16) + (8 << 10) + (0 << 0))
420#define MPCTL_PARAM_399 ((0 << 26) + (51 << 16) + (7 << 10) + (35 << 0)) 458#define MPCTL_PARAM_399 ((0 << 26) + (51 << 16) + (7 << 10) + (35 << 0))
421#define MPCTL_PARAM_532 ((0 << 26) + (51 << 16) + (10 << 10) + (12 << 0)) 459#define MPCTL_PARAM_532 ((0 << 26) + (51 << 16) + (10 << 10) + (12 << 0))
422 460
423/* UPCTL PD MFD MFI MFN */ 461/* UPCTL PD MFD MFI MFN */
424#define UPCTL_PARAM_288 (((1-1) << 26) + ((13-1) << 16) + (5 << 10) + (7 << 0)) 462#define UPCTL_PARAM_288 (((1-1) << 26) + ((13-1) << 16) + (5 << 10) + (7 << 0))
@@ -434,43 +472,43 @@
434 472
435#define PBC_BASE CS4_BASE_ADDR /* Peripheral Bus Controller */ 473#define PBC_BASE CS4_BASE_ADDR /* Peripheral Bus Controller */
436 474
437#define PBC_BSTAT2 0x2 475#define PBC_BSTAT2 0x2
438#define PBC_BCTRL1 0x4 476#define PBC_BCTRL1 0x4
439#define PBC_BCTRL1_CLR 0x6 477#define PBC_BCTRL1_CLR 0x6
440#define PBC_BCTRL2 0x8 478#define PBC_BCTRL2 0x8
441#define PBC_BCTRL2_CLR 0xA 479#define PBC_BCTRL2_CLR 0xA
442#define PBC_BCTRL3 0xC 480#define PBC_BCTRL3 0xC
443#define PBC_BCTRL3_CLR 0xE 481#define PBC_BCTRL3_CLR 0xE
444#define PBC_BCTRL4 0x10 482#define PBC_BCTRL4 0x10
445#define PBC_BCTRL4_CLR 0x12 483#define PBC_BCTRL4_CLR 0x12
446#define PBC_BSTAT1 0x14 484#define PBC_BSTAT1 0x14
447#define MX31EVB_CS_LAN_BASE (CS4_BASE_ADDR + 0x00020000 + 0x300) 485#define MX31EVB_CS_LAN_BASE (CS4_BASE_ADDR + 0x00020000 + 0x300)
448#define MX31EVB_CS_UART_BASE (CS4_BASE_ADDR + 0x00010000) 486#define MX31EVB_CS_UART_BASE (CS4_BASE_ADDR + 0x00010000)
449 487
450#define REDBOOT_IMAGE_SIZE 0x40000 488#define REDBOOT_IMAGE_SIZE 0x40000
451 489
452#define SDRAM_WORKAROUND_FULL_PAGE 490#define SDRAM_WORKAROUND_FULL_PAGE
453 491
454#define ARMHIPG_208_52_52 /* ARM: 208MHz, HCLK=IPG=52MHz*/ 492#define ARMHIPG_208_52_52 /* ARM: 208MHz, HCLK=IPG=52MHz*/
455#define ARMHIPG_52_52_52 /* ARM: 52MHz, HCLK=IPG=52MHz*/ 493#define ARMHIPG_52_52_52 /* ARM: 52MHz, HCLK=IPG=52MHz*/
456#define ARMHIPG_399_66_66 494#define ARMHIPG_399_66_66
457#define ARMHIPG_399_133_66 495#define ARMHIPG_399_133_66
458 496
459/* MX31 EVB SDRAM is from 0x80000000, 64M */ 497/* MX31 EVB SDRAM is from 0x80000000, 64M */
460#define SDRAM_BASE_ADDR CSD0_BASE_ADDR 498#define SDRAM_BASE_ADDR CSD0_BASE_ADDR
461#define SDRAM_SIZE 0x04000000 499#define SDRAM_SIZE 0x04000000
462 500
463#define UART_WIDTH_32 /* internal UART is 32bit access only */ 501#define UART_WIDTH_32 /* internal UART is 32bit access only */
464#define EXT_UART_x16 502#define EXT_UART_x16
465 503
466#define UART_WIDTH_32 /* internal UART is 32bit access only */ 504#define UART_WIDTH_32 /* internal UART is 32bit access only */
467 505
468#define FLASH_BURST_MODE_ENABLE 1 506#define FLASH_BURST_MODE_ENABLE 1
469#define SDRAM_COMPARE_CONST1 0x55555555 507#define SDRAM_COMPARE_CONST1 0x55555555
470#define SDRAM_COMPARE_CONST2 0xAAAAAAAA 508#define SDRAM_COMPARE_CONST2 0xAAAAAAAA
471#define UART_FIFO_CTRL 0x881 509#define UART_FIFO_CTRL 0x881
472#define TIMEOUT 1000 510#define TIMEOUT 1000
473#define writel(v,a) (*(volatile int *) (a) = (v)) 511#define writel(v,a) (*(REG32_PTR_T)(a) = (v))
474#define readl(a) (*(volatile int *)(a)) 512#define readl(a) (*(REG32_PTR_T)(a))
475#define writew(v,a) (*(volatile short *) (a) = (v)) 513#define writew(v,a) (*(REG16_PTR_T)(a) = (v))
476#define readw(a) (*(volatile short *)(a)) 514#define readw(a) (*(REG16_PTR_T)(a))
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-17 23:14:20 +0000